Welcome to Our Presentation Submitted to our Honorable Fernaz Narin Nur
Nand gate latch (sequential circuit )
Jul 19, 2015
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Welcome to Our Presentation
Submitted to our Honorable
Fernaz Narin Nur
Welcome to Blackbaud
Our Team Members :
No Name ID
01
02
03
04
05
Shammi Akter Urmi
Sazzad Hossain Nirjhor
Sazzad Hossain Nirjhor
Sazzad Hossain Nirjhor
Sazzad Hossain Nirjhor
133-15-3029
133-15-2927
133-15-3029
133-15-3029
133-15-3029
NAND Gate Latch
Combinational Logic:1.Output depends only on current inputs
Sequential Logic:
2.Need some type of memory to remember the past input
values .
1.Output depends not only on current inputs but also on
past input values .
NAND Latch is Sequential Logic:
Cross Coupled inverters
Basic Latch – is a feedback connection of two NOR gates or two
NAND gates, which can store one bit of information. It can be set using
the One input and reset to 0 using the Another input.
Basic Latch
NAND Latch NOR Latch
NAND Latch :
For storing one bit of information if we use two NAND gates
to make a feedback connection , then it called NAND Latch .
NAND Latch
NAND Gate Latch
The two NAND gates are cross-
coupled so that the output of to
one of the input of NAND-2, and
vice versa. The gate output, labeled
Q and Q’, respectively, are latch
out-put. Under normal conditions,
these output will always be the
inverse of each other.
NAND-1
NAND-2
NAND Latch
10
NAND Latch
NAND Gate LatchS R Q0 Q Q’
0 0 0
1
1
0
0
1 1 Q = Q’
Initial Value
S
R
Q
Q
11
NAND Latch
NAND Gate LatchS’ R’ Q0 Q Q’
0 0 0 1 1
0 0 1
1
1
0
0
1 1 Q = Q’
Q = Q’
S
R
Q
Q
12
NAND Latch
NAND Gate LatchS R Q0 Q Q’
0 0 0 1 1
0 0 1 1 1
0 1 0 00
1
1
0
1
Q = Q’
S
R
Q
Q
Q = Q0
13
NAND Latch
NAND Gate LatchS R Q0 Q Q’
0 0 0 0 1
0 0 1 1 0
0 1 0 0 1
0 1 10
1
1
0
0 1
Q = Q0
Q = 0S
R
Q
Q
Q = Q0
14
NAND Latch
NAND Gate LatchS R Q0 Q Q’
0 0 0 0 1
0 0 1 1 0
0 1 0 0 1
0 1 1 0 1
1 0 0
0
1
0
1
1 0
Q = 0
Q = Q0
Q = 1S
R
Q
Q
15
NAND Latch
NAND Gate Latch
S R Q0 Q Q’
0 0 0 0 1
0 0 1 1 0
0 1 0 0 1
0 1 1 0 1
1 0 0 1 0
1 0 1
1
0
0
1
1 0
Q = 0
Q = Q0
Q = 1
Q = 1
S
R
Q
Q
16
NAND Latch
NAND Gate Latch
S R Q0 Q Q’
0 0 0 0 1
0 0 1 1 0
0 1 0 0 1
0 1 1 0 1
1 0 0 1 0
1 0 1 1 0
1 1 0
0
1
1
1
0 0
Q = 0
Q = Q0
Q = 1
Q = Q’
0
S
R
Q
Q
17
NAND Latch
NAND Gate Latch
S R Q0 Q Q’
0 0 0 0 1
0 0 1 1 0
0 1 0 0 1
0 1 1 0 1
1 0 0 1 0
1 0 1 1 0
1 1 0 0 0
1 1 1
1
0
1
1
0 0
Q = 0
Q = 1
Q = 1
Q = Q’
0
Q = Q’
S
R
Q
Q
18
NAND Latch
S’ R’ Q
0 0 Q=Q’=1
0 1 1
1 0 0
1 1 Q0
Invalid
Set
Reset
No change
S
R
Q
Q
Any
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