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Msc Thesis Final

Aug 23, 2014

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K-Band Low-Noise Amplifier Design in CMOSTechnologybyDustin DunwellA thesis submitted to theDepartment of Electrical and Computer Engineeringin conformity with the requirements forthe degree of Master of Science (Engineering)Queens UniversityKingston, Ontario, CanadaAugust 2006Copyright c Dustin Dunwell, 2006AbstractThis thesis investigates some the challenges associated with high-speed circuit designin silicon CMOS. It begins with the use of on-chip inductor structures, which consumea large chip area, are dicult to accurately model and create signicant sources of lossand noise at high-frequencies. By modifying a standard microstrip transmission linestructure to include a series-stub section, a novel inductor structure is presented withdimensions that are easily implementable on-chip. Measured results show that thisstructure is able to provide Q factor improvements of up to 20% over spiral inductorsat frequencies above 25 GHz.Secondly, the use of accumulation-mode MOS (AMOS) varactors is investigatedat frequencies above 20 GHz and a new model for their behaviour is presented. Thismodel relies on physical equations for each of its components, making it easily adapt-able to any technology node or layout dimensions. Comparison to measured resultsshows good agreement even for capacitances on the order of tens of femtofarads.Finally, two low-noise ampliers (LNAs) are presented in order to demonstrate theusefulness and functionality of the above concepts. The rst amplier makes use ofthe SSTL inductor structures to implement a two-stage cascode device for operationat 23 GHz. This cascode conguration improves reverse isolation helping to stabilizethe amplier and simplify matching network design. Although cascode topologiesiincur a penalty to the noise gure, this penalty is oset by the improved modelingand Q factor of the SSTL inductors, allowing the amplier to achieve a measured NFof 5.9 dB and a gain of 13.5 dB at 23 GHz.The second amplier uses the varactor models to implement a capacitive neutral-ization scheme to improve the reverse isolation of a dierential LNA. This topologyhas not been reported in a high-frequency amplier to date as very few publicationsexist examining dierential LNA performance at frequencies above 20 GHz. Mea-sured results show that while the gain of 5.2 dB of this amplier falls short of thatpredicted by simulation results, it is still able to produce a NF of only 4.5 dB atapproximately 23 GHz.iiAcknowledgmentsThis section is to acknowledge and thank the many parties that generously assistedin the completion of this thesis.Firstly, the interest and enthusiasm shown by Dr. Brian Frank in his teachinghas played a large part in sparking my own interest in very high speed silicon circuitdesign. His continuing guidance and support, not to mention his problem solvingskills, have been instrumental in the successful completion of my graduate studies inthe area.Secondly, thanks is owed to the other graduate students in the Very High SpeedCircuits research lab at Queens University who were never too busy to lend a helpinghand and whose company during long hours at the lab was a comfort during the moststressful times.Financial support for much of this work was sponsored by the Natural Sciencesand Research Council (NSERC) as well as Queens University.I would also like to thank my family whose tolerance in my continued absence andbusy schedule has not gone unnoticed. Finally, I would like to thank my girlfriendand best friend for her understanding and perseverance during the past two years.Kelly: your pride and devotion means the world to me. You have never and will nevercome second.iiiAcronyms, Abbreviations, andSymbolsAbbreviation Denition channel thermal noise coecient noise parameter gate noise coecient

ox oxide permittivity

si silicon permittivityn electron mobility frequency in rad/sADS Advanced Design System (from Agilent)AMOS Accumulation-mode metal oxide semiconductorc correlation coecientCAD Computer aided designCG Common gateCS Common sourceCMOS Complimentary metal oxide semiconductorivCNM Classical noise matchingCPW Coplanar waveguideCTM Capacitor top metalDC Direct currentDSP Digital signal processingEM Electromagneticf frequency in HertzfMAX Maximum frequency of oscillationfT Unity current gain frequencyFET Field eect transistorGaAs Gallium arsenideHFNM High frequency noise matchingInP Indium phosphidek Boltzmanns constantLNA Low noise amplierMAG Maximum available gainMIM Metal-insulator-metalMOSFET Metal oxide semiconductor eld eect transistorMOS Metal oxide semiconductorMPG Metal 1 patterned groundNF Noise gureNwell n well carrier concentrationNsub p substrate carrier concentrationNi Intrinsic silicon carrier concentrationvNSERC Natural Sciences and Research CouncilPCNO Power constrained noise optimizationPPG Polysilicon patterned groundQ Quality factorq Electron chargeRF Radio FrequencySiGe Silicon germaniumSOI Silicon on insulatorSSTL Series stub transmission lineT Temperature in KelvinVCO Voltage controlled oscillatorVNA Vector network analyzerviContentsAbstract iAcknowledgments iiiAcronyms, Abbreviations, and Symbols ivList of Tables xiList of Figures xii1 Introduction 11.1 Wireless Communication . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 The RF CMOS Challenge . . . . . . . . . . . . . . . . . . . . . . . . 21.3 Literature Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.3.1 Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.3.2 Varactors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.3.3 Low-Noise Ampliers . . . . . . . . . . . . . . . . . . . . . . . 81.4 Thesis Overview and Major Contributions . . . . . . . . . . . . . . . 102 On-Chip Inductors 13vii2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.2 Spiral Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.3 Series Stub Transmission Line Inductors . . . . . . . . . . . . . . . . 182.3.1 SSTL Optimization . . . . . . . . . . . . . . . . . . . . . . . . 232.3.2 Simulation and Measurement Results . . . . . . . . . . . . . . 272.4 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Varactors 343.1 NMOS Varactors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343.2 AMOS Varactors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383.3 AMOS Varactor Modeling . . . . . . . . . . . . . . . . . . . . . . . . 393.3.1 Channel Capacitance Model . . . . . . . . . . . . . . . . . . . 423.3.2 Overlap Capacitance Model . . . . . . . . . . . . . . . . . . . 433.3.3 Channel Resistance Model . . . . . . . . . . . . . . . . . . . . 473.3.4 Substrate Model . . . . . . . . . . . . . . . . . . . . . . . . . 483.3.5 Additional Parasitics . . . . . . . . . . . . . . . . . . . . . . . 553.4 Measured Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573.5 The Diusion Biased Alternative . . . . . . . . . . . . . . . . . . . . 633.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674 Single-Ended LNA Design 694.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694.2 Transistor Size and Bias Condition . . . . . . . . . . . . . . . . . . . 704.3 The Cascode Structure . . . . . . . . . . . . . . . . . . . . . . . . . . 74viii4.4 Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774.5 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804.6 Measured Results . . . . . . . . . . . . . . .