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Monday, 08 September 2008 Time 08:00 08:30 08:45 09:30 10:00 10:30 11:00 11:30 12:00 12:45 14:00 14:30 15:00 15:30 16:00 16:30 17:00 17:30 17:45 18:15 HS2 Encryption Applications Session Chairs: Tom Kean, Lionel Torres M1B_1 Bitstream Encryption and Authentication with AES-GCM in Dynamically Reconfigurable Systems Yohei Hori, Akashi Satoh, Hirofumi Sakane and Kenji Toda M1B_2 Three-stage Pipeline Implementation for SHA2 using Data Forwarding Hoang Anh Tuan, Katsuhiro Yamazaki and Shigeru Oyanagi M1B_3 Chosen-Message SPA Attacks against FPGA-Based RSA Hardware Implementations Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki and Akashi Satoh Image and Video Processing Session Chairs: Martin Herbordt, Fernando Concalves M2B_1 How fast is an FPGA in image pro- cessing ? Takashi Saegusa, Tsutomu Maruyama and Yoshiki Yamaguchi M2B_2 A Scalable Computing and Memory Architecture for Variable Block Size Motion Estimation on Field-programmable Gate Arrays Theepan Moorthy and Andy Ye M2B_3 Real-Time Image Super Resolution Using an FPGA Oliver Bowen and Christos- Savvas Bouganis Search and Matching Acceleration Session Chairs: Tom VanCourt, Horacio Neto M3B_1 High-Speed Regular Expression Matching Engine using Multi-Character NFA Norio Yamagaki, Reetinder Sidhu and Satoshi Kamiya M3B_2 Scalable High-Throughput SRAM- based Architecture for IP-Lookup Using FPGA Hoang Le, Weirong Jiang and Viktor Prasanna M3B_3 Mining Association Rules with Systolic Trees Song Sun and Joseph Zambreno ROOM 1.404 (First Floor) Networks on Chip I Session Chairs: Christophe Bobda, Hideharu Amano M1C_1 Exploring FPGA Network on Chip Implementations Across Various Application and Network Loads Graham Schelle and Dirk Grunwald M1C_2 Reducing Interconnection Cost in Coarse- Grained Dynamic Computing through Multistage Network Ricardo Ferreira, Marcone Laure, Mateus Rutzig, Antonio C. Beck and Luigi Carro M1C_3 NOC Architecture Design for Multi- cluster Chips Henrique Freitas, Philippe Navaux and Tatiana Santos FPGA Architecture Session Chairs: Bernard Pottier, Marco Platzner M2C_1 SFPGA - A Scalable Switch based FPGA Architecture and Design Methodology Shakith Fernando, Xiaolei Chen and Yajun Ha M2C_2 FPGA Family Composition and Effects of Specialized Blocks Pongstorn Maidee, Nagib Hakim and Kia Bazargan M2C_3 A Variation-aware Constant-Order Optimization Scheme Utilizing Delay Detectors to Search for Fastest Paths on FPGAs Kazutoshi Kobayashi, Yohei Kume, Cam Lai Ngo, Yuuri Sugihara and Hidetoshi Onodera Reconfigurable ASIP Design Session Chairs: Koen Bertels, Enno Lübbers M3C_1 A Configurable and Programmable Motion Estimation Processor for the H.264 Video Codec Jose Luis Nunez-Yanez, Eddie Hung and Vassilios Chouliaras M3C_2 A Flexible and Reliable Embedded System for Detector Control in a High Energy Physics Experiment Tobias Krawutschke M3C_3 Area Optimization of Cryptographic Co-Processors Implemented in Dual-Rail with Precharge Positive Logic Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger and Philippe Hoogvorst HS1 Registration Opening Remarks Keynote 1- Break Modelling Session Chairs: Neil Bergmann, Thilo Pionteck M1A_1 Increasing the Level of Abstraction in FPGA-Based Designs Martin Danek, Jiri Kadlec, Roman Bartosinski and Lukas Kohout M1A_2 Modeling Recursion Data Structures for FPGA-based Implementation Spyridon Ninos and Apostolos Dollas M1A_3 A Portable Abstraction Layer for Hardware Threads Enno Lübbers and Marco Platzner Break/Poster Session Keynote 2- Lunch Analysis of Reconfigurability Session Chairs: Joao Cardoso, Felix Reimann M2A_1 Fast and Accurate Resource Estimation of RTL-based Designs Targeting FPGAs Paul Schumacher and Pradip Jha M2A_2 Fast Toggle Rate Computation for FPGA Circuits Tomasz Czajkowski and Stephen Brown M2A_3 On-the-fly Attestation of Reconfigurable Hardware Ricardo Chaves, Georgi Kuzmanov and Leonel Sousa Break/Poster Session Dynamic Reconfiguration Session Chairs: Patrick Lysaght, Gordon Brebner M3A_1 No-Break Dynamic Defragmentation of Reconfigurable Devices Sándor Fekete,Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch and Jürgen Teich M3A_2 ReCoBus-Builder - a Novel Tool and Technique to Build Statically and Dynamically Reconfigurable Systems for FPGAs Dirk Koch, Christian Beckhoff and Jürgen Teich M3A_3 An Efficient Run-time Router for Connecting Modules in FPGAs Jorge Surís, Cameron Patterson and Peter Athanas Break PhD Forum Wine Reception Tuesday, 09 September 2008 Time 08:00 08:30 09:15 09:30 10:00 10:30 11:00 11:30 12:00 12:30 13:00 14:00 14:30 15:00 15:30 16:00 16:30 17:00 17:30 18:00 19:00-22:00 HS2 Novel Applications Session Chairs: Roger Woods, Suhaib Fahmy T1B_1 FPGA Implementation of a flexible decoder for long LDPC codes Christiane Beuschel and Hans-Jörg Pfleiderer T1B_2 Towards an "Early Neural Circuit Simulator": A FPGA Implementation of Processing In the Rat Whisker System Brian Leung,Yan Pan, Chris Schroeder, Seda Memik, Gokhan Memik and Mitra Hartmann T1B_3 Decimal Multiplier on FPGA using Embedded Binary Multipliers Horácio Neto and Mário Véstias Random Number Generation & PLL Session Chairs: Eduardo Boemo, Jose Nunez- Yanez T2B_1 Sampling from the Exponential Distribution using Independent Bernoulli Variates David Barrie Thomas and Wayne Luk T2B_2 Enhancing security of ring oscillator-based TRNG implemented in FPGA Viktor Fischer, Florent Bernard, Nathalie Bochard and Michal Varchola T2B_3 Digital Hilbert Transformers for FPGA- based Phase-Locked Loops Martin Kumm and M. Shahab Sanjari FPGA Application in High Energy Physics Session Chairs: Luciano Musa, Volker Lindenstruth T3B_1 ATCA-based Computation Platform for Data Acquisition and Triggering in Particle Physics Experiments Ming Liu, Tiago Perez, Johannes Lang, Shuo Yang, Wolfgang Kuehn, Hao Xu, Dapeng Jin, Qiang Wang, Lu Li, Zhen'An Liu, Zhonghai Lu and Axel Jantsch T3B_2 An FPGA-based High-speed, Low- latency Trigger Processor for High-energy Physics Jan de Cuveland, Felix Rettig, Venelin Angelov and Volker Lindenstruth High Performance Computing for Financial and Biological Modelling Session Chairs: Tarek El-Ghazawi, George Constantinides T4B_1 FPGA Acceleration of Monte-Carlo Based Credit Derivative Pricing Alexander Kaganov, Asif Lakhany and Paul Chow T4B_2 FPGA Acceleration of Quasi-Monte Carlo in Finance Nathan Woods and Tom VanCourt T4B_3 Acceleration of a Production Rigid Molecule Docking Code Bharat Sukhwani and Martin Herbordt ROOM 1.404 (First Floor) Reconfigurable Processors Session Chairs: Christian Hochberger, Jürgen Becker T1C_1 A Computation- and Communication- Infrastructure for Modular Special Instructions in a Dynamically Reconfigurable Processor Lars Bauer, Muhammad Shafique and Jörg Henkel T1C_2 Application-Adaptive Reconfiguration of Memory Address Shuffler for FPGA- Embedded Instruction-Set Processor Young- Su Kwon and Bon-Tae Koo and Nak-Woong Eum T1C_3 Instruction Buffer Mode for Multi- Context Dynamically Reconfigurable Processors Toru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Hasegawa and Hideharu Amano Networks on Chip II Session Chairs: Klaus Danne, Thilo Streichert T2C_1 MetaWire: Using FPGA Configuration Circuitry to Emulate a Network-on-Chip Matthew Shelburne, Cameron Patterson, Peter Athanas, Mark Jones, Brian Martin and Ryan Fong T2C_2 GICS: Generic Interconnection System Tomáš Málek,Tomáš Martínek and Jan Kořenek T2C_3 A Link Removal Methodology for Networks-on-Chip on Reconfigurable Systems Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi and Hideharu Amano Reconfigurable Processor Arrays Session Chairs: Mladen Berekovic, Stephan Wong T3C_1 Shared Reconfigurable Architectures for CMPs Matthew Watkins, Mark Cianchetti and David Albonesi T3C_2 Power Reduction Techniques for Dynamically Reconfigurable Processor Arrays Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito, Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbunheng and Hideharu Amano DFG Session Foreword DFG Session Exhibition Floor: Fine Grain Reconfigurable Architectures, Coarse-Grained Reconfiguration, Application-Specific Reconfigurable Processors, Seamless Design Flow for Reconfigurable Systems, Network Prosessors, Hyperreconfigurable Architectures HS1 Registration Keynote 3- Break Compilers for Reconfigurable Architectures Session Chairs: Andreas Koch, David Andrews T1A_1 Loop Unrolling and Shifting for Reconfigurable Architectures Ozana Dragomir, Todor Stefanov and Koen Bertels T1A_2 CHiMPS: A C-Level Compilation Flow for Hybrid CPU/FPGA Architectures Andrew Putnam, Dave Bennett, Eric Dellinger, Jeff Mason, Prasanna Sundararajan and Susan Eggers T1A_3 Combining Data Reuse Exploitation with Data-Level Parallelization for FPGA Targeted Hard- ware Compilation: A Geometric Programming Framework Qiang Liu, George Constantinides, Konstantinos Masselos and Peter Cheung Break/Poster Session Analysis of Reconfigurability II Session Chairs: Christophe Wolinski, Josef Angermeier T2A_1 An Analytical Model Describing The Relationships Between Logic Architecture and FPGA Density Andrew Lam, Steve Wilton, Philip Leong and Wayne Luk T2A_2 Rapid Estimation of Power Consumption for Hybrid FPGAs Chun Hok Ho, Philip Leong, Wayne Luk and Steven Wilton T2A_3 A Technique for Minimizing Power During FPGA Placement Kristofer Vorwerk, Madhu Raman, Julien Dunoyer, Yaun-chung Hsu, Arun Kundu and Andrew Kennings Lunch Codesign Session Chairs: Gilles Sassatelli, Peter Zipf T3A_1 Mapping and Scheduling with Task Clustering for Heterogeneous Computing Systems Yuet Ming Lam,Jose Gabriel F. Coutinho, Wayne Luk and Philip Heng Wai Leong T3A_2 Low-Latency High-Bandwidth HW/SW Communication in a Virtual Memory Environment Holger Lange and Andreas Koch Tutorial Break/Poster Session Tools for FPGA Design Session Chairs: Markus Weinhardt, Heiner Giefers T4A_1 An Integrated Debugging Environment for FPGA Computing Platforms Kevin Camera and Robert Brodersen T4A_2 Secure FPGA Configuration Architecture Preventing System Downgrade Benoît Badrignans, Reouven Elbaz and Lionel Torres T4A_3 Bitstream Compression Techniques for Virtex 4 FPGAs Radu Stefan and Sorin Coţ ofană Break/Poster Session Tram/Bus to castle Gala Dinner Ivo Bolsens: FPGA: THE FUTURE PLATFORM FOR TRANSFORMING, TRANSPORTING AND COMPUTING DATA Dan Werthimer: SEARCHING FOR ET WITH FPGAS Peter Alfke: Xilinx Virtex 5 FXT Luciano Musa: FPGAS IN HIGH ENERGY PHYSICS EXPERIMENTS AT CERN Wednesday, 10 September 2008 Time 08:00 08:30 09:15 09:30 10:00 10:30 11:00 11:30 12:00 12:30 13:00 HS2 Algorithm Acceleration Session Chairs: Manfred Glesner, Donald Bailey W1B_1 Novel FPGA based Haar Classifier Face Detection Algorithm Acceleration Changjian Gao and Shih-Lien Lu W1B_2 An FPGA-Based Implementation of the MINRES Algorithm David Boland and George Constantinides W1B_3 Efficient FPGA Mapping of Gilbert`s Algorithm for SVM Training on Large-scale Classification Problems Markos Papadonikolakis and Christos-Savvas Bouganis Surveys and Trends Session Chairs: Michael Hübner, Reiner Hartenstein W2B_1 Reconfigurable Hardware: The Holy Grail of Matching Performance with Programming Productivity Claudio Brunelli, Fabio Campi, Damien Picard, Fabio Garzia and Jari Nurmi W2B_2 Fault Tolerant Methods for Reliability in FPGAs Edward Stott, Pete Sedcole and Peter Cheung W2B_3 A Non-voltile Run-time FPGA using Thermally Assisted Switching MRAMs Yoann Guillemenet, Lionel Torres, Gilles Sassatelli, Nicolas Bruchon and Ilham Hassoune ROOM 1.404 (First Floor) Industrial Presentations Session Chair: Endric Schubert, Christophe Layer W1C_1: Beyond FPGAs: Flexible Coarse-Grained Reconfigurable Multi-Cores Solving Impeding Performance, Power and Cost Constraints Paul Heysters Recore Systems W1C_2 Next Generation Algorithmic Synthesis Crossing the Gap between Algorithm and Hardware Architecture Michael Bierl Mentor Graphics W1C_3 Top-down design flow for implemen- ting hardware and software systems Prashant Rao, The MathWorks Industrial Presentations Session Chairs: Thomas Irmen, Christophe Layer W2C_1 Mixed Signal FPGA for Integrated System Management Mike Brogley W2C_2 : C to gates: different tools for different tasks Tom Van Court, Altera W2C_3: Software Defined Silicon - a revolution in electronic product design Henk Muller, XMOS Semiconductor HS1 Registration Keynote 4- Break Synthesis Session Chairs: Uli Heinkel, Dirk Koch W1A_1 Floating Point Datapath Synthesis for FPGAs Martin Langhammer W1A_2 Automatic Generation of Run-time Parameterizable Configurations Karel Bruneel and Dirk Stroobandt W1A_3 Generation of partial FPGA configura- tions at run-time Miguel L. Silva and João Canas Ferreira Break/Poster Session Optimization Session Chairs: Christian Plessl, Wayne Luk W2A_1 Area and Reconfiguration Time Minimization of the Communication Network in Regular 2D Reconfigurable Architectures Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich and Frank Hannig W2A_2 An Symbolic Decomposition of Functions with Multi-valued Inputs and Outputs for FPGA-based Implementation Stanislaw Deniziak and Mariusz Wiśniewski W2A_3 Memory Access Parallelization in High- Level Language Compilation for Reconfigurable Adaptive Computers Hagen Gädke, Florian Stock and Andreas Koch Closing remarks Conference Close Otto Wohlmuth: HIGH PERFORMANCE COMPUTING BASED ON FPGAS Workshops Wednesday, 10 September 2008 Thursday, September 11 - Friday, September 12, 2008 THE MATHWORKS:Top Down System Flow - A detailed Technical Demonstration, Room 3.401 (Third Floor) SYNPLICITY: Prototyping as a Productive Verification Methodology, Room 2.404 (Second Floor) XILINX: Introduction to PlanAhead and Partial Reconfiguration, Room 1.404 (First Floor) XILINX: Embedded Systems Design and Partial Reconfiguration, Room 1.404 (First Floor) Time 14:00 Time 09:00 Programm FPL1 Kopie1:Programm FPL1 22.08.2008 8:31 Uhr Seite 1
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Monday, 08 September 2008 Tuesday, 09 September 2008 … · 2008-09-04 · Monday, 08 September 2008 Time 08:00 08:30 08:45 09:30 10:00 10:30 11:00 11:30 12:00 12:45 14:00 14:30 15:00

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Page 1: Monday, 08 September 2008 Tuesday, 09 September 2008 … · 2008-09-04 · Monday, 08 September 2008 Time 08:00 08:30 08:45 09:30 10:00 10:30 11:00 11:30 12:00 12:45 14:00 14:30 15:00

Monday, 08 September 2008Time08:0008:3008:4509:3010:00

10:30

11:00

11:3012:0012:4514:00

14:30

15:00

15:3016:00

16:30

17:00

17:3017:4518:15

HS2

Encryption ApplicationsSession Chairs: Tom Kean, Lionel Torres

M1B_1 Bitstream Encryption andAuthentication with AES-GCM in DynamicallyReconfigurable Systems Yohei Hori, Akashi Satoh,Hirofumi Sakane and Kenji Toda

M1B_2 Three-stage Pipeline Implementationfor SHA2 using Data Forwarding Hoang AnhTuan, Katsuhiro Yamazaki and Shigeru Oyanagi

M1B_3 Chosen-Message SPA Attacksagainst FPGA-Based RSA HardwareImplementations Atsushi Miyamoto, NaofumiHomma, Takafumi Aoki and Akashi Satoh

Image and Video ProcessingSession Chairs: Martin Herbordt, FernandoConcalves

M2B_1 How fast is an FPGA in image pro-cessing ? Takashi Saegusa, TsutomuMaruyama and Yoshiki Yamaguchi

M2B_2 A Scalable Computing and MemoryArchitecture for Variable Block Size MotionEstimation on Field-programmable GateArrays Theepan Moorthy and Andy YeM2B_3 Real-Time Image Super ResolutionUsing an FPGA Oliver Bowen and Christos-Savvas Bouganis

Search and Matching AccelerationSession Chairs: Tom VanCourt, Horacio Neto

M3B_1 High-Speed Regular ExpressionMatching Engine using Multi-Character NFANorio Yamagaki, Reetinder Sidhu and Satoshi

Kamiya

M3B_2 Scalable High-Throughput SRAM-based Architecture for IP-Lookup Using FPGAHoang Le,Weirong Jiang and Viktor Prasanna

M3B_3 Mining Association Rules withSystolic Trees Song Sun and Joseph Zambreno

ROOM 1.404 (First Floor)

Networks on Chip ISession Chairs: Christophe Bobda, Hideharu Amano

M1C_1 Exploring FPGA Network on ChipImplementations Across Various Application andNetwork Loads Graham Schelle and Dirk Grunwald

M1C_2 Reducing Interconnection Cost in Coarse-Grained Dynamic Computing through MultistageNetwork Ricardo Ferreira, Marcone Laure, MateusRutzig,Antonio C. Beck and Luigi Carro

M1C_3 NOC Architecture Design for Multi-cluster Chips Henrique Freitas, Philippe Navauxand Tatiana Santos

FPGA ArchitectureSession Chairs: Bernard Pottier, Marco Platzner

M2C_1 SFPGA - A Scalable Switch basedFPGA Architecture and Design MethodologyShakith Fernando, Xiaolei Chen and Yajun Ha

M2C_2 FPGA Family Composition and Effectsof Specialized Blocks Pongstorn Maidee, NagibHakim and Kia Bazargan

M2C_3 A Variation-aware Constant-OrderOptimization Scheme Utilizing Delay Detectors toSearch for Fastest Paths on FPGAs KazutoshiKobayashi,Yohei Kume, Cam Lai Ngo,Yuuri Sugihara

and Hidetoshi Onodera

Reconfigurable ASIP DesignSession Chairs: Koen Bertels, Enno Lübbers

M3C_1 A Configurable and ProgrammableMotion Estimation Processor for the H.264Video Codec Jose Luis Nunez-Yanez, EddieHung and Vassilios Chouliaras

M3C_2 A Flexible and Reliable EmbeddedSystem for Detector Control in a High EnergyPhysics Experiment Tobias Krawutschke

M3C_3 Area Optimization of CryptographicCo-Processors Implemented in Dual-Rail withPrecharge Positive Logic Sylvain Guilley, LaurentSauvage, Jean-Luc Danger and Philippe Hoogvorst

HS1RegistrationOpening RemarksKeynote 1-BreakModellingSession Chairs: Neil Bergmann, Thilo Pionteck

M1A_1 Increasing the Level of Abstractionin FPGA-Based Designs Martin Danek, JiriKadlec, Roman Bartosinski and Lukas Kohout

M1A_2 Modeling Recursion Data Structuresfor FPGA-based Implementation SpyridonNinos and Apostolos Dollas

M1A_3 A Portable Abstraction Layer forHardware Threads Enno Lübbers and MarcoPlatzner

Break/Poster SessionKeynote 2-LunchAnalysis of ReconfigurabilitySession Chairs: Joao Cardoso, Felix Reimann

M2A_1 Fast and Accurate ResourceEstimation of RTL-based Designs TargetingFPGAs Paul Schumacher and Pradip JhaM2A_2 Fast Toggle Rate Computation forFPGA Circuits Tomasz Czajkowski and StephenBrown

M2A_3 On-the-fly Attestation of ReconfigurableHardware Ricardo Chaves, Georgi Kuzmanovand Leonel Sousa

Break/Poster SessionDynamic ReconfigurationSession Chairs: Patrick Lysaght, Gordon Brebner

M3A_1 No-Break Dynamic Defragmentation ofReconfigurableDevicesSándorFekete,TomKamphans,

Nils Schweer, Christopher Tessars, Jan van der Veen,

Josef Angermeier, Dirk Koch and Jürgen Teich

M3A_2 ReCoBus-Builder - a Novel Tool andTechnique to Build Statically and DynamicallyReconfigurable Systems for FPGAs Dirk Koch,Christian Beckhoff and Jürgen Teich

M3A_3 An Efficient Run-time Router forConnecting Modules in FPGAs Jorge Surís,Cameron Patterson and Peter Athanas

BreakPhD ForumWine Reception

Tuesday, 09 September 2008Time08:0008:3009:1509:30

10:00

10:30

11:0011:30

12:00

12:30

13:0014:00

14:30

15:0015:3016:00

16:30

17:00

17:3018:0019:00-22:00

HS2

Novel ApplicationsSession Chairs: Roger Woods, Suhaib Fahmy

T1B_1 FPGA Implementation of a flexibledecoder for long LDPC codes ChristianeBeuschel and Hans-Jörg Pfleiderer

T1B_2 Towards an "Early Neural Circuit Simulator":A FPGA Implementation of Processing In the RatWhisker SystemBrianLeung,YanPan,ChrisSchroeder,

SedaMemik,GokhanMemik andMitra Hartmann

T1B_3 Decimal Multiplier on FPGA usingEmbedded Binary Multipliers Horácio Netoand Mário Véstias

Random Number Generation & PLLSession Chairs: Eduardo Boemo, Jose Nunez-Yanez

T2B_1 Sampling from the ExponentialDistribution using Independent BernoulliVariates David Barrie Thomas and Wayne Luk

T2B_2 Enhancing security of ring oscillator-basedTRNG implemented in FPGA Viktor Fischer, FlorentBernard, Nathalie Bochard and Michal Varchola

T2B_3 Digital Hilbert Transformers for FPGA-based Phase-Locked Loops Martin Kumm and

M. Shahab Sanjari

FPGA Application in High Energy PhysicsSession Chairs: Luciano Musa, Volker Lindenstruth

T3B_1 ATCA-based Computation Platform forData Acquisition and Triggering in Particle PhysicsExperimentsMing Liu,Tiago Perez, Johannes Lang,ShuoYang,Wolfgang Kuehn,Hao Xu,Dapeng Jin,Qiang

Wang,Lu Li, Zhen'An Liu,Zhonghai Lu andAxel Jantsch

T3B_2 An FPGA-based High-speed, Low-latency Trigger Processor for High-energyPhysics Jan de Cuveland, Felix Rettig, VenelinAngelov and Volker Lindenstruth

High Performance Computing forFinancial and Biological ModellingSession Chairs: Tarek El-Ghazawi, GeorgeConstantinides

T4B_1 FPGA Acceleration of Monte-Carlo BasedCredit Derivative PricingAlexander Kaganov,AsifLakhany and Paul Chow

T4B_2 FPGA Acceleration of Quasi-Monte Carloin Finance NathanWoods and TomVanCourt

T4B_3 Acceleration of a Production RigidMoleculeDocking Code Bharat Sukhwani andMartin Herbordt

ROOM 1.404 (First Floor)

Reconfigurable ProcessorsSession Chairs: Christian Hochberger, JürgenBecker

T1C_1 A Computation- and Communication-Infrastructure for Modular Special Instructionsin a Dynamically Reconfigurable Processor LarsBauer, Muhammad Shafique and Jörg Henkel

T1C_2 Application-Adaptive Reconfigurationof Memory Address Shuffler for FPGA-Embedded Instruction-Set Processor Young-Su Kwon and Bon-Tae Koo and Nak-Woong Eum

T1C_3 Instruction Buffer Mode for Multi-Context Dynamically Reconfigurable ProcessorsToru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei

Hasegawa and Hideharu Amano

Networks on Chip IISession Chairs: Klaus Danne, Thilo Streichert

T2C_1 MetaWire: Using FPGA ConfigurationCircuitry to Emulate a Network-on-ChipMatthew Shelburne, Cameron Patterson, Peter

Athanas, Mark Jones, Brian Martin and Ryan Fong

T2C_2 GICS: Generic Interconnection SystemTomáš Málek, Tomáš Martínek and Jan Kořenek

T2C_3 A Link Removal Methodology forNetworks-on-Chip on Reconfigurable SystemsDaihanWang, Hiroki Matsutani,Michihiro Koibuchi

and Hideharu Amano

Reconfigurable Processor ArraysSession Chairs: Mladen Berekovic, StephanWong

T3C_1 Shared Reconfigurable Architecturesfor CMPs Matthew Watkins, Mark Cianchetti

and David Albonesi

T3C_2 Power Reduction Techniques forDynamically Reconfigurable Processor ArraysTakashi Nishimura, Keiichiro Hirai,Yoshiki Saito,Takuro

Nakamura,Yohei Hasegawa,Satoshi Tsutsumi,

VasutanTunbunheng and HideharuAmano

DFG Session

Foreword DFG Session

Exhibition Floor:Fine Grain Reconfigurable Architectures,

Coarse-Grained Reconfiguration,

Application-Specific Reconfigurable Processors,

Seamless Design Flow for Reconfigurable

Systems,

Network Prosessors,

Hyperreconfigurable Architectures

HS1RegistrationKeynote 3-BreakCompilers for Reconfigurable ArchitecturesSession Chairs: Andreas Koch, David Andrews

T1A_1 Loop Unrolling and Shifting forReconfigurable Architectures Ozana Dragomir,Todor Stefanov and Koen Bertels

T1A_2 CHiMPS: A C-Level Compilation Flow forHybrid CPU/FPGA Architectures Andrew Putnam,

Dave Bennett, Eric Dellinger, Jeff Mason, Prasanna

Sundararajan and Susan Eggers

T1A_3 Combining Data Reuse Exploitation withData-Level Parallelization for FPGA Targeted Hard-ware Compilation: A Geometric ProgrammingFramework Qiang Liu, George Constantinides,Konstantinos Masselos and Peter Cheung

Break/Poster SessionAnalysis of Reconfigurability IISession Chairs: Christophe Wolinski, JosefAngermeier

T2A_1 An Analytical Model Describing TheRelationships Between Logic Architecture andFPGA DensityAndrew Lam, SteveWilton, Philip

Leong andWayne Luk

T2A_2 Rapid Estimation of Power Consumptionfor Hybrid FPGAs Chun Hok Ho, Philip Leong,Wayne Luk and Steven Wilton

T2A_3 A Technique for Minimizing PowerDuring FPGA Placement Kristofer Vorwerk,Madhu Raman, Julien Dunoyer, Yaun-chung Hsu,

Arun Kundu and Andrew Kennings

LunchCodesignSession Chairs: Gilles Sassatelli, Peter Zipf

T3A_1 Mapping and Scheduling with TaskClustering for Heterogeneous ComputingSystems Yuet Ming Lam, Jose Gabriel F. Coutinho,Wayne Luk and Philip HengWai Leong

T3A_2 Low-Latency High-Bandwidth HW/SWCommunication in a Virtual Memory EnvironmentHolger Lange and Andreas Koch

TutorialBreak/Poster SessionTools for FPGA Design

Session Chairs: Markus Weinhardt, Heiner Giefers

T4A_1 An Integrated Debugging Environmentfor FPGA Computing Platforms Kevin Cameraand Robert Brodersen

T4A_2 Secure FPGA Configuration ArchitecturePreventing System Downgrade Benoît Badrignans,Reouven Elbaz and Lionel Torres

T4A_3 Bitstream Compression Techniques forVirtex 4 FPGAs Radu Stefan and Sorin CoţofanăBreak/Poster SessionTram/Bus to castleGala Dinner

Ivo Bolsens: FPGA: THE FUTURE PLATFORM FOR TRANSFORMING, TRANSPORTING AND COMPUTING DATADan Werthimer: SEARCHING FOR ET WITH FPGAS

Peter Alfke: Xilinx Virtex 5 FXT

Luciano Musa: FPGAS IN HIGH ENERGY PHYSICS EXPERIMENTS AT CERN

Wednesday, 10 September 2008Time08:0008:3009:1509:30

10:00

10:30

11:0011:30

12:00

12:30

13:00

HS2

Algorithm AccelerationSession Chairs: Manfred Glesner, Donald Bailey

W1B_1 Novel FPGA based Haar Classifier FaceDetection Algorithm Acceleration ChangjianGao and Shih-Lien Lu

W1B_2 An FPGA-Based Implementation of theMINRES Algorithm David Boland and George

Constantinides

W1B_3 Efficient FPGA Mapping of Gilbert`sAlgorithm for SVM Training on Large-scaleClassification Problems Markos Papadonikolakisand Christos-Savvas Bouganis

Surveys and TrendsSession Chairs: Michael Hübner, ReinerHartenstein

W2B_1 Reconfigurable Hardware: The Holy Grailof Matching Performance with ProgrammingProductivity Claudio Brunelli, Fabio Campi, DamienPicard, Fabio Garzia and Jari Nurmi

W2B_2 Fault Tolerant Methods for Reliabilityin FPGAs Edward Stott, Pete Sedcole and PeterCheung

W2B_3 A Non-voltile Run-time FPGA usingThermally Assisted Switching MRAMs YoannGuillemenet, Lionel Torres, Gilles Sassatelli, Nicolas

Bruchon and Ilham Hassoune

ROOM 1.404 (First Floor)

Industrial PresentationsSession Chair: Endric Schubert, Christophe Layer

W1C_1: Beyond FPGAs: Flexible Coarse-GrainedReconfigurableMulti-Cores Solving ImpedingPerformance, Power and Cost Constraints PaulHeysters Recore Systems

W1C_2 Next Generation Algorithmic SynthesisCrossing the Gap between Algorithm andHardware ArchitectureMichael Bierl Mentor GraphicsW1C_3 Top-down design flow for implemen-ting hardware and software systemsPrashant Rao, The MathWorks

Industrial PresentationsSession Chairs: Thomas Irmen, ChristopheLayer

W2C_1 Mixed Signal FPGA for IntegratedSystemManagementMike Brogley

W2C_2 : C to gates: different tools for differenttasks Tom Van Court, Altera

W2C_3: Software Defined Silicon - a revolutionin electronic product designHenk Muller, XMOS Semiconductor

HS1RegistrationKeynote 4-BreakSynthesisSession Chairs: Uli Heinkel, Dirk Koch

W1A_1 Floating Point Datapath Synthesis forFPGAs Martin Langhammer

W1A_2 Automatic Generation of Run-timeParameterizable Configurations Karel Bruneeland Dirk Stroobandt

W1A_3 Generation of partial FPGA configura-tions at run-time Miguel L. Silva and JoãoCanas Ferreira

Break/Poster SessionOptimizationSession Chairs: Christian Plessl, Wayne Luk

W2A_1 Area and Reconfiguration TimeMinimization of the Communication Networkin Regular 2D Reconfigurable ArchitecturesChristophe Wolinski, Krzysztof Kuchcinski, Jürgen

Teich and Frank Hannig

W2A_2 An Symbolic Decomposition ofFunctions with Multi-valued Inputs andOutputs for FPGA-based ImplementationStanislaw Deniziak and Mariusz WiśniewskiW2A_3 Memory Access Parallelization in High-Level Language Compilation for ReconfigurableAdaptive Computers Hagen Gädke, Florian Stockand Andreas Koch

Closing remarksConference Close

Otto Wohlmuth: HIGH PERFORMANCE COMPUTING BASED ON FPGAS

WorkshopsWednesday, 10 September 2008

Thursday, September 11 - Friday, September 12, 2008

THE MATHWORKS: Top Down System Flow - A detailed Technical Demonstration, Room 3.401 (Third Floor)

SYNPLICITY: Prototyping as a Productive Verification Methodology, Room 2.404 (Second Floor)

XILINX: Introduction to PlanAhead and Partial Reconfiguration, Room 1.404 (First Floor)

XILINX: Embedded Systems Design and Partial Reconfiguration, Room 1.404 (First Floor)

Time14:00

Time09:00

Programm FPL1 Kopie1:Programm FPL1 22.08.2008 8:31 Uhr Seite 1

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Reconfigurable ArchitecturesP1.01: THE EFFECT OF SPARSE SWITCH PATTERNS ON THE AREA EFFICIENCY OF MULTI-BIT ROUTING RESOURCES IN FIELD-PROGRAMMABLE GATE ARRAYSPing Chen and Andy YeP1.02: AN EMBEDDED DYNAMICALLY SELF-RECONFIGURABLE MASTER-SLAVES MPSOC ARCHITECTURE Kimon Karras and Elias ManolakosP1.03: EMMA - A SUGGESTION FOR AN EMBEDDED MULTI-PRECISION MULTIPLIER ARRAY FOR FPGAS Oliver A. Pfänder and Hans-Jörg PfleidererP1.04: THE HARDWARE APPLICATION PLATFORM OF THE HARTES PROJECT Immacolata Colacicco, Giacomo Marchiori and Raffaele TripiccioneDesign Methods and ToolsP1_05: SCALABLE HIGH PERFORMANCE COMPUTING ON FPGA CLUSTERS USING MESSAGE PASSING Eoin Creedon and Michael ManzkeP1_06: FPGA INTERCONNECT DESIGN USING LOGICAL EFFORT Haile Yu, Yuk Hei Chan and Philip H. W. LeongP1_07: AN ILP FORMULATION FOR ARCHITECTURAL SYNTHESIS AND APPLICATION MAPPING ON FPGA-BASED HYBRID MULTI-PROCESSOR SOC JasonWu, John Williams and Neil BergmannP1_08: OPERATING SYSTEM SUPPORT FOR ONLINE PARTIAL DYNAMIC RECONFIGURATION MANAGEMENT Marco Domenico Santambrogio, VincenzoRana and Donatella SciutoP1_09: LOOP SCHEDULING AND ASSIGNMENT TO MINIMIZE ENERGY WHILE HIDING LATENCY FOR HETEROGENEOUS MULTI-BANK MEMORY MeikangQiu and Edwin ShaP1_10: NUMERICAL FUNCTION GENERATORS USING BILINEAR INTERPOLATION Shinobu Nagayama, Tsutomu Sasao and Jon ButlerApplicationsP1_11: A VERSATILE HARDWARE ARCHITECTURE FOR A CFAR DETECTOR BASED ON A LINEAR INSERTION SORTER Roberto Perez-Andrade, ReneCumplido, Claudia Feregrino-Uribe and Fernando Martin Del CampoP1_12: POLYMORPHIC WAVELET ARCHITECTURES USING RECONFIGURABLE HARDWARE Amit Pande and Joseph ZambrenoP1_13: DIRECT SIGMA-DELTA MODULATED SIGNAL PROCESSING IN FPGA Chiu-Wa Ng, Ngai Wong, Hayden Kwok-Hay So and Tung-Sang NgP1_14: A LIFTING-BASED DWT AND IDWT PROCESSOR WITH MULTI-CONTEXT CONFIGURATION AND NORMALIZATION FACTOR Andre Guntoro andManfred Glesner

Reconfigurable ArchitecturesP2_01: RECONFIGURABLE PLATFORMS AND THE CHALLENGES FOR LARGE-SCALE IMPLEMENTATIONS OF SPIKING NEURAL NETWORKS Jim Harkin,Liam McDaid, Fearghal Morgan, Thomas Dowrick and Steve HallP2_02: A DEDICATED DMA LOGIC ADDRESSING A TIME-MULTIPLEXED MEMORY TO REDUCE THE EFFECTS OF THE SYSTEM BUS BOTTLENECK ClaudioBrunelli, Fabio Garzia, Carmelo Giliberto and Jari NurmiP2_03: CUSTOMIZED RECONFIGURABLE INTERCONNECTION NETWORKS FOR MULTIPLE APPLICATION SOCSHongbing Fan, Yu-Liang Wu and Jason ErnstP2_04: NEW DIMENSIONS FOR MULTIPROCESSOR ARCHITECTURES: ON DEMAND HETEROGENEITY, INFRASTRUCTURE AND PERFORMANCE THROUGHRECONFIGURABILITY THE RAMPSOC APPROACH Diana Göhringer, Michael Hübner, Thomas Perschke and Jürgen BeckerDesign Methods and ToolsP2_05: CVC: THE C TO RTL COMPILER FOR CALLBACK BASED VERIFICATION MODEL Yasuhiro Ito, Yutaka Sugawara, Mary Inaba and Kei HirakiP2_06: PERFORMANCE OPTIMIZATION BY TRACK SWAPPING ON CRITICAL PATHS UTILIZING RANDOM VARIATIONS FOR FPGAS Yuuri Sugihara, YoheiKume, Kazutoshi Kobayashi and Hidetoshi OnoderaP2_07: SAT-BASED RESOURCE BINDING FOR REDUCING CRITICAL PATH DELAYS Kenshu Seto, Yuta Nonaka, Takuya Maruizumi and Yasuhiro ShirakiP2_08: BOUNCE, A NEW APPROACH TO MEASURE SUB-NANOSECOND TIME INTERVALS Ralf Joost and Ralf SalomonP2_09: POWER EFFICIENT DSP DATAPATH CONFIGURATION METHODOLOGY FOR FPGA Stephen McKeown, Roger Woods and John McAllisterApplicationsP2_10: IEEE802.16-2004 OFDM FUNCTIONS IMPLEMENTATION ON FPGAS WITH DESIGN EXPLORATION Ahmad Sghaier, Shawki Areibi and Robert DonyP2_11: AN FPGA ARCHITECTURE FOR THE PAGERANK EIGENVECTOR PROBLEM Séamas McGettrick, Dermot Geraghty and Ciarán McElroyP2_12: RECONFIGURABLE CELL ARCHITECTURE FOR MULTI-STANDARD INTERLEAVING AND DEINTERLEAVING IN DIGITAL COMMUNICATION SYSTEMSErik Rijshouwer, Alexander Danilin and Sergei SawitzkiP2_13: SEPARABLE IMPLEMENTATION OF THE SECOND ORDER VOLTERRA FILTER (SOVF) IN XILINX VIRTEX-E FPGA Mamoun Al-Mistarihi

PhD_01: FPGA INTERCONNECT SIZING USING EXTENDED LOGICAL EFFORT MODEL Haile YuPhD_02: BIO-INSPIRATION HELPS COMPUTERS: A NEW MACHINE Nicolas Saint-Jean, G. Sassatelli, P. Benoit, L. Torres and M. RobertPhD_03: EXPLOITATION OF DYNAMIC AND PARTIAL HARDWARE RECONFIGURATION FOR ON-LINE POWER/PERFORMANCE OPTIMIZATION KatarinaPaulsson, Michael Hübner and Jürgen BeckerPhD_04: THERMAL AWARE FPGA ARCHITECTURES AND CAD Shilpa BhojPhD_05: COMBATING PROCESS VARIATION ON FPGAS WITH PRECISE AT-SPEED DELAY MEASUREMENT METHOD Justin S. J. Wong, Peter Y. K. Cheungand Pete SedcolePhD_06: ADAPTIVE PRECISION TECHNIQUE FOR GENETIC ALGORITHMS Chun Tak ChowPhD_07: RECONFIGURABLE MANY-CORES WITH LEAN INTERCONNECT Heiner Giefers

Reconfigurable ArchitecturesP3_01: A MULTI-PLATFORM CONTROLLER ALLOWING FOR MAXIMUM DYNAMIC PARTIAL RECONFIGURATION THROUGHPUT Christopher Claus, BinZhang, Walter Stechele, Lars Braun, Michael Hübner and Jürgen BeckerP3_02: COARSE-GRAIN DYNAMICALLY RECONFIGURABLE COPROCESSOR FOR IMAGE PROCESSING IN SOPC Almudena Lindoso, Luis Entrena, JuanIzquierdo and Judith Liu-JimenezP3_03: EXPLORING COMPACT DESIGN ON HIGH THROUGHPUT COARSE GRAINED RECONFIGURABLE ARCHITECTURES Kazuya Tanigawa, Tetsuya Zuyama,Takuro Uchida and Tetsuo HironakaP3_04: EVALUATING DYNAMIC PARTIAL RECONFIGURATION IN THE INTEGER PIPELINE OF A FPGA-BASED OPENSOURCE PROCESSOR Izhar Zaidi,Atukem Nabina, C. Canagarajah and Jose Nunez-Yanez

Monday, 08 September 2008Time11:30

15:30

17:45

InternationalConference onFieldProgrammableLogic andApplications

Heidelberg, Germany, September 08-10

2008FPL

Poster Sessions

Tuesday, 09 September 200811:00

The International Conference on Field Programmable Logic andApplications is sponsored by:

Poster Sessions

Design Methods and ToolsP3_05: A NEW METHODOLOGY FOR DEBUGGING AND VALIDATION OF SOFT CORES Christian Hochberger and Alexander WeißP3_06: A SCALABLE APPROACH FOR DISTRIBUTED RUN-TIME OPTIMIZATION ON MP-SOC USING GAME THEORY Diego Puschini, Fabien Clermidy,Pascal Benoit, Gilles Sassatelli and Lionel TorresP3_07: MACROMAP: A TECHNOLOGY MAPPING ALGORITHM FOR HETEROGENEOUS FPGAS WITH EFFECTIVE AREA ESTIMATION Wei Xing, Zhou Qiangand Chen JuanjuanP3_08: PARALLEL HARDWARE OBJECTS FOR DYNAMICALLY PARTIAL RECONFIGURATION Norbert Abel and Udo KebschullP3_09: FILE SYSTEM ACCESS FROM RECONFIGURABLE FPGA HARDWARE PROCESSES IN BORPH Hayden So and Robert BrodersenP3_10: SELF-RECONFIGURABLE EMBEDDED SYSTEMS ON SPARTAN-3 Enrique Cantó, Francesc Fons and Mariano LópezApplicationsP3_11: AN ELEMENT-BY-ELEMENT PRECONDITIONED CONJUGATE GRADIENT SOLVER OF 3D TETRAHEDRAL FINITE ELEMENTS ON AN FPGA COPROCESSORJing Hu, Steven F. Quigley and Andrew ChanP3_12: CREATING UNIQUE IDENTIFIERS ON FIELD PROGRAMMABLE GATE ARRAYS USING NATURAL PROCESSING VARIATIONS James Crouch, HirenPatel, Yong Kim and Robert BenningtonP3_13: DESIGN OF A HIGH SPEED PSEUDO-RANDOM BIT SEQUENCE BASED TIME RESOLVED SINGLE PHOTON COUNTER ON FPGA Haiting Tian,Shakith Fernando, Hock Wei Soon, Yajun Ha and Nanguang Chen

European Commission Projects on Reconfigurable Computing

Reconfigurable ArchitecturesP4_01: A COMPARISON OF EMBEDDED RECONFIGURABLE VIDEO-PROCESSING ARCHITECTURES Christopher Claus, Walter Stechele, Matthias Kovatsch,Josef Angermeier and Jürgen TeichP4_02: INTERFACE AND RECONFIGURATION CONTROLLER FOR A WIRELESS MAC-ORIENTED DYNAMICALLY RECONFIGURABLE HARDWARE CO-PRO-CESSOR Syed Waqar Nabi, Cade C. Wells and Wim VanderbauwhedeP4_03: CLUSTER ARCHITECTURE BASED ON LOW COST RECONFIGURABLE HARDWARE Cesar Pedraza, Javier Castillo, Emilio Castillo, Cristobal Camarero,José L. Bosque, Rafael Menendez and José I. MartínezP4_04: A HIGH PERFORMANCE MICROPROCESSOR WITH DSP EXTENSIONS OPTIMIZED FOR THE VIRTEX-4 FPGA Andreas Ehliar, Per Karlström andDake LiuDesign Methods and ToolsP4_05: COMPARING THROUGHPUT AND POWER CONSUMPTION IN BOTH SEQUENTIAL AND RECONFIGURABLE PROCESSORS Kevin K. Liu, Charles B.Cameron and Antal SarkadyP4_06: DATA PATH DRIVEN WAVEFORM-LIKE RECONFIGURATION Lars Braun, Katarina Paulsson, Herrmann Krömer, Michael Hübner and Jürgen BeckerP4_07: ACTIVE KERNEL MONITORING TO COMBAT SCHEDULER GAMING IN RECONFIGURABLE COMPUTING SYSTEMSWenyin Fu and Katherine ComptonP4_08: AN ARCHITECTURE AND TIMING-DRIVEN ROUTING ALGORITHM FOR AREA-EFFICIENT FPGAS WITH TIME-MULTIPLEXED INTERCONNECTS HanyuLiu, Xiaolei Chen and Yajun HaP4_09:A HARDWARE COMPILATION FLOW FOR INSTANCE-SPECIFICVLIW CORESMarkus Koester,Wayne Luk and Geoffrey BrownApplicationsP4_10: A RECONFIGURABLE ACCELERATOR FOR QUANTUM COMPUTATIONS Michail Zampetakis, Vasilis Samoladas and Apostolos DollasP4_11: HIGH-PERFORMANCE FPGA-BASED FLOATING-POINT ADDERWITH THREE INPUTS Andre Guntoro and Manfred GlesnerP4_12: A RATE-BASED PREFILTERING APPROACH TO BLAST ACCELERATION Panagiotis Afratis, Euripides Sotiriades, Grigorios Chrysos, Sotiria Fytrakiand Dionisios PnevmatikatosP4_13: ENHANCING ADC RESOLUTION THROUGH FIELD PROGRAMMABLE ANALOG ARRAY DYNAMIC RECONFIGURATION Diego P. Morales, Antonio García,Alberto J. Palma, Miguel A. Carvajal and Encanación CastilloP4_14: ARCHITECTURE AND IMPLEMENTATION OF A FRAME AGGREGATION UNIT FOR OPTICAL FRAME-BASED SWITCHING George Kornaros

Reconfigurable ArchitecturesP5_01: A LOW OVERHEAD FAULT TOLERANT FPGA WITH NEW CONNECTION BOX Fujie Wong and Yajun HaDesign Methods and ToolsP5_02: AN OPTIMIZATION METHOD OF DMA TRANSFER FOR A GENERAL PURPOSE RECONFIGURABLE MACHINE Sayaka Shida, Yuichiro Shibata,Kiyoshi Oguri and Duncan A. BuellP5_03: RESOURCE ALLOCATION ALGORITHM AND OPENMP EXTENSIONS FOR PARALLEL EXECUTION ON A HETEROGENEOUS RECONFIGURABLE PLATFORMVlad-Mihai Sima, Elena Moscu Panainte and Koen BertelsP5_04: COMPILER GENERATED SYSTOLIC ARRAYS FOR WAVEFRONT ALGORITHM ACCELERATION ON FPGAS Betul Buyukkurt and Walid A. NajjarP5_05: A DYNAMIC TEMPERATURE CONTROL SIMULATION SYSTEM FOR FPGAS Shilpa Bhoj and Dinesh BhatiaP5_06: PRACTICAL IMPLEMENTATION OF A NETWORK-BASED STOCHASTIC BIOCHEMICAL SIMULATION SYSTEM ON AN FPGA Masato Yoshimi, YuriNishikawa, Yasunori Osana, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Hideki Yamada, Hiroaki Kitano and Hideharu AmanoP5_07: EXPLORATION OF COMPILED HARDWARE ACCELERATION OF MOLECULAR DYNAMICS CODE Jason Villarreal and Walid NajjarP5_08: AREA OPTIMIZATION OF BIT PARALLEL FINITE FIELD MULTIPLIERS WITH FAST CARRY LOGIC ON FPGAS Gang Zhou, Li Li and Harald MichalikP5_09: ENHANCING COPACOBANA FOR ADVANCED APPLICATIONS IN CRYPTOGRAPHY AND CRYPTANALYSIS Tim Güneysu, Christof Paar, Gerd Pfeifferand Manfred SchimmlerP5_10: CONNECTED COMPONENTS ANALYSIS OF STREAMED IMAGES Donald Bailey, Christopher Johnston and Ni MaSurveys, Trends and EducationP5_11: ON THE DESIGN PARAMETERS OF RUNTIME RECONFIGURABLE SYSTEMS Thilo Pionteck, Carsten Albrecht, Roman Koch and Erik MaehleP5_12: TEACHING FPGA SYSTEM DESIGN VIA A REMOTE LABORATORY FACILITY Yamuna Rajasekhar,William V. Kritikos, Andrew G. Schmidt and Ron SassP5_13: TOWARDS BENCHMARKING ENERGY EFFICIENCY OF RECONFIGURABLE ARCHITECTURES Tobias Becker, Peter Jamieson,Wayne Luk, Peter Cheungand Tero Rissa

Time11:00

15:30

17:30

Wednesday, 10 September 2011:00

PhD Forum

Programm FPL1 Kopie1:Programm FPL1 22.08.2008 8:32 Uhr Seite 2