Monday, 08 September 2008 Tuesday, 09 September 2008 · PDF file 2008-09-04 · Monday, 08 September 2008 Time 08:00 08:30 08:45 09:30 10:00 10:30 11:00 11:30 12:00 12:45 14:00 14:30

Monday, 08 September 2008 Time 08:00 08:30 08:45 09:30 10:00

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HS2

Encryption Applications Session Chairs: Tom Kean, Lionel Torres

M1B_1 Bitstream Encryption and Authentication with AES-GCM in Dynamically Reconfigurable Systems Yohei Hori, Akashi Satoh, Hirofumi Sakane and Kenji Toda

M1B_2 Three-stage Pipeline Implementation for SHA2 using Data Forwarding Hoang Anh Tuan, Katsuhiro Yamazaki and Shigeru Oyanagi

M1B_3 Chosen-Message SPA Attacks against FPGA-Based RSA Hardware Implementations Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki and Akashi Satoh

Image and Video Processing Session Chairs: Martin Herbordt, Fernando Concalves

M2B_1 How fast is an FPGA in image pro- cessing ? Takashi Saegusa, Tsutomu Maruyama and Yoshiki Yamaguchi

M2B_2 A Scalable Computing and Memory Architecture for Variable Block Size Motion Estimation on Field-programmable Gate Arrays Theepan Moorthy and Andy Ye M2B_3 Real-Time Image Super Resolution Using an FPGA Oliver Bowen and Christos- Savvas Bouganis

Search and Matching Acceleration Session Chairs: Tom VanCourt, Horacio Neto

M3B_1 High-Speed Regular Expression Matching Engine using Multi-Character NFA Norio Yamagaki, Reetinder Sidhu and Satoshi

Kamiya

M3B_2 Scalable High-Throughput SRAM- based Architecture for IP-Lookup Using FPGA Hoang Le,Weirong Jiang and Viktor Prasanna

M3B_3 Mining Association Rules with Systolic Trees Song Sun and Joseph Zambreno

ROOM 1.404 (First Floor)

Networks on Chip I Session Chairs: Christophe Bobda, Hideharu Amano

M1C_1 Exploring FPGA Network on Chip Implementations Across Various Application and Network Loads Graham Schelle and Dirk Grunwald

M1C_2 Reducing Interconnection Cost in Coarse- Grained Dynamic Computing through Multistage Network Ricardo Ferreira, Marcone Laure, Mateus Rutzig,Antonio C. Beck and Luigi Carro

M1C_3 NOC Architecture Design for Multi- cluster Chips Henrique Freitas, Philippe Navaux and Tatiana Santos

FPGA Architecture Session Chairs: Bernard Pottier, Marco Platzner

M2C_1 SFPGA - A Scalable Switch based FPGA Architecture and Design Methodology Shakith Fernando, Xiaolei Chen and Yajun Ha

M2C_2 FPGA Family Composition and Effects of Specialized Blocks Pongstorn Maidee, Nagib Hakim and Kia Bazargan

M2C_3 A Variation-aware Constant-Order Optimization Scheme Utilizing Delay Detectors to Search for Fastest Paths on FPGAs Kazutoshi Kobayashi,Yohei Kume, Cam Lai Ngo,Yuuri Sugihara

and Hidetoshi Onodera

Reconfigurable ASIP Design Session Chairs: Koen Bertels, Enno Lübbers

M3C_1 A Configurable and Programmable Motion Estimation Processor for the H.264 Video Codec Jose Luis Nunez-Yanez, Eddie Hung and Vassilios Chouliaras

M3C_2 A Flexible and Reliable Embedded System for Detector Control in a High Energy Physics Experiment Tobias Krawutschke

M3C_3 Area Optimization of Cryptographic Co-Processors Implemented in Dual-Rail with Precharge Positive Logic Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger and Philippe Hoogvorst

HS1 Registration Opening Remarks Keynote 1- Break Modelling Session Chairs: Neil Bergmann, Thilo Pionteck

M1A_1 Increasing the Level of Abstraction in FPGA-Based Designs Martin Danek, Jiri Kadlec, Roman Bartosinski and Lukas Kohout

M1A_2 Modeling Recursion Data Structures for FPGA-based Implementation Spyridon Ninos and Apostolos Dollas

M1A_3 A Portable Abstraction Layer for Hardware Threads Enno Lübbers and Marco Platzner

Break/Poster Session Keynote 2- Lunch Analysis of Reconfigurability Session Chairs: Joao Cardoso, Felix Reimann

M2A_1 Fast and Accurate Resource Estimation of RTL-based Designs Targeting FPGAs Paul Schumacher and Pradip Jha M2A_2 Fast Toggle Rate Computation for FPGA Circuits Tomasz Czajkowski and Stephen Brown

M2A_3 On-the-fly Attestation of Reconfigurable Hardware Ricardo Chaves, Georgi Kuzmanov and Leonel Sousa

Break/Poster Session Dynamic Reconfiguration Session Chairs: Patrick Lysaght, Gordon Brebner

M3A_1 No-Break Dynamic Defragmentation of ReconfigurableDevicesSándorFekete,TomKamphans, Nils Schweer, Christopher Tessars, Jan van der Veen,

Josef Angermeier, Dirk Koch and Jürgen Teich

M3A_2 ReCoBus-Builder - a Novel Tool and Technique to Build Statically and Dynamically Reconfigurable Systems for FPGAs Dirk Koch, Christian Beckhoff and Jürgen Teich

M3A_3 An Efficient Run-time Router for Connecting Modules in FPGAs Jorge Surís, Cameron Patterson and Peter Athanas

Break PhD Forum Wine Reception

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HS2

Novel Applications Session Chairs: Roger Woods, Suhaib Fahmy

T1B_1 FPGA Implementation of a flexible decoder for long LDPC codes Christiane Beuschel and Hans-Jörg Pfleiderer

T1B_2 Towards an "Early Neural Circuit Simulator": A FPGA Implementation of Processing In the Rat Whisker SystemBrianLeung,YanPan,ChrisSchroeder, SedaMemik,GokhanMemik andMitra Hartmann

T1B_3 Decimal Multiplier on FPGA using Embedded Binary Multipliers Horácio Neto and Mário Véstias

Random Number Generation & PLL Session Chairs: Eduardo Boemo, Jose Nunez- Yanez

T2B_1 Sampling from the Exponential Distribution using Independent Bernoulli Variates David Barrie Thomas and Wayne Luk

T2B_2 Enhancing security of ring oscillator-based TRNG implemented in FPGA Viktor Fischer, Florent Bernard, Nathalie Bochard and Michal Varchola

T2B_3 Digital Hilbert Transformers for FPGA- based Phase-Locked Loops Martin Kumm and M. Shahab Sanjari

FPGA Application in High Energy Physics Session Chairs: Luciano Musa, Volker Lindenstruth

T3B_1 ATCA-based Computation Platform for Data Acquisition and Triggering in Particle Physics ExperimentsMing Liu,Tiago Perez, Johannes Lang, ShuoYang,Wolfgang Kuehn,Hao Xu,Dapeng Jin,Qiang

Wang,Lu Li, Zhen'An Liu,Zhonghai Lu andAxel Jantsch

T3B_2 An FPGA-based High-speed, Low- latency Trigger Processor for High-energy Physics Jan de Cuveland, Felix Rettig, Venelin Angelov and Volker Lindenstruth

High Performance Computing for Financial and Biological Modelling Session Chairs: Tarek El-Ghazawi, George Constantinides

T4B_1 FPGA Acceleration of Monte-Carlo Based Credit Derivative PricingAlexander Kaganov,Asif Lakhany and Paul Chow

T4B_2 FPGA Acceleration of Quasi-Monte Carlo in Finance NathanWoods and TomVanCourt

T4B_3 Acceleration of a Production RigidMolecule Docking Code Bharat Sukhwani andMartin Herbordt

ROOM 1.404 (First Floor)

Reconfigurable Processors Session Chairs: Christian Hochberger, Jürgen Becker

T1C_1 A Computation- and Communication- Infrastructure for Modular Special Instructions in a Dynamically Reconfigurable Processor Lars Bauer, Muhammad Shafique and Jörg Henkel

T1C_2 Application-Adaptive Reconfiguration of Memory Address Shuffler for FPGA- Embedded Instruction-Set Processor Young- Su Kwon and Bon-Tae Koo and Nak-Woong Eum

T1C_3 Instruction Buffer Mode for Multi- Context Dynamically Reconfigurable Processors Toru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei

Hasegawa and Hideharu Amano

Networks on Chip II Session Chairs: Klaus Danne, Thilo Streichert

T2C_1 MetaWire: Using FPGA Configuration Circuitry to Emulate a Network-on-Chip Matthew Shelburne, Cameron Patterson, Peter

Athanas, Mark Jones, Brian Martin and Ryan Fong

T2C_2 GICS: Generic Interconnection System Tomáš Málek, Tomáš Martínek and Jan Kořenek

T2C_3 A Link Removal Methodology for Networks-on-Chip on Reconfigurable Systems DaihanWang, Hiroki Matsutani,Michihiro Koibuchi

and Hideharu Amano

Reconfigurable Processor Arrays Session Chairs: Mladen Berekovic, Stephan Wong

T3C_1 Shared Reconfigurable Architectures for CMPs Matthew Watkins, Mark Cianchetti and David Albonesi

T3C_2 Power Reduction Techniques for Dynamically Reconfigurable Processor Arrays Takashi Nishimura, Keiichiro Hirai,Yoshiki Saito,Takuro

Nakamura,Yohei Hasegawa,Satoshi Tsutsumi,

VasutanTunbunheng and HideharuAmano

DFG Session

Foreword DFG Session

Exhibition Floor: Fine Grain Reconfigurable Architectures,

Coarse-Grained Reconfiguration,

Application-Specific Reconfigurable Processors,

Seamless Design Flow for Reconfigurable

Systems,

Network Prosessors,

Hyperreconfigurable Architectures

HS1 Registration Keynote 3- Break Compilers for Reconfigurable Architectures Session Chairs: Andreas Koch, David Andrews

T1A_1 Loop Unrolling and Shifting for Reconfigurable Architectures Ozana Dragomir, Todor Stefanov and Koen Bertels

T1A_2 CHiMPS: A C-Level Compilation Flow for Hybrid CPU/FPGA Architectures Andrew Putnam, Dave Bennett, Eric Dellinger, Jeff Mason, Prasanna

Sundararajan and Susan Eggers

T1A_3 Combining Data Reuse Exploitation with Data-Level Parallelization for FPGA Targeted Hard- ware Compilation: A Geometric Programming Framework Qiang Liu, George Constantinides, Konstantinos Masselos and Peter Cheung

Break/Poster Session Analysis of Reconfigurability II Session Chairs: Christophe Wolinski, Josef Angermeier

T2A_1 An Analytical Model Describing The Relationships Between Logic Architecture and FPGA DensityAndrew Lam, SteveWilton, Philip Leong an