Monday, 08 September 2008 Time 08:00 08:30 08:45 09:30 10:00 10:30 11:00 11:30 12:00 12:45 14:00 14:30 15:00 15:30 16:00 16:30 17:00 17:30 17:45 18:15 HS2 Encryption Applications Session Chairs: Tom Kean, Lionel Torres M1B_1 Bitstream Encryption and Authentication with AES-GCM in Dynamically Reconfigurable Systems Yohei Hori, Akashi Satoh, Hirofumi Sakane and Kenji Toda M1B_2 Three-stage Pipeline Implementation for SHA2 using Data Forwarding Hoang Anh Tuan, Katsuhiro Yamazaki and Shigeru Oyanagi M1B_3 Chosen-Message SPA Attacks against FPGA-Based RSA Hardware Implementations Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki and Akashi Satoh Image and Video Processing Session Chairs: Martin Herbordt, Fernando Concalves M2B_1 How fast is an FPGA in image pro- cessing ? Takashi Saegusa, Tsutomu Maruyama and Yoshiki Yamaguchi M2B_2 A Scalable Computing and Memory Architecture for Variable Block Size Motion Estimation on Field-programmable Gate Arrays Theepan Moorthy and Andy Ye M2B_3 Real-Time Image Super Resolution Using an FPGA Oliver Bowen and Christos- Savvas Bouganis Search and Matching Acceleration Session Chairs: Tom VanCourt, Horacio Neto M3B_1 High-Speed Regular Expression Matching Engine using Multi-Character NFA Norio Yamagaki, Reetinder Sidhu and Satoshi Kamiya M3B_2 Scalable High-Throughput SRAM- based Architecture for IP-Lookup Using FPGA Hoang Le, Weirong Jiang and Viktor Prasanna M3B_3 Mining Association Rules with Systolic Trees Song Sun and Joseph Zambreno ROOM 1.404 (First Floor) Networks on Chip I Session Chairs: Christophe Bobda, Hideharu Amano M1C_1 Exploring FPGA Network on Chip Implementations Across Various Application and Network Loads Graham Schelle and Dirk Grunwald M1C_2 Reducing Interconnection Cost in Coarse- Grained Dynamic Computing through Multistage Network Ricardo Ferreira, Marcone Laure, Mateus Rutzig, Antonio C. Beck and Luigi Carro M1C_3 NOC Architecture Design for Multi- cluster Chips Henrique Freitas, Philippe Navaux and Tatiana Santos FPGA Architecture Session Chairs: Bernard Pottier, Marco Platzner M2C_1 SFPGA - A Scalable Switch based FPGA Architecture and Design Methodology Shakith Fernando, Xiaolei Chen and Yajun Ha M2C_2 FPGA Family Composition and Effects of Specialized Blocks Pongstorn Maidee, Nagib Hakim and Kia Bazargan M2C_3 A Variation-aware Constant-Order Optimization Scheme Utilizing Delay Detectors to Search for Fastest Paths on FPGAs Kazutoshi Kobayashi, Yohei Kume, Cam Lai Ngo, Yuuri Sugihara and Hidetoshi Onodera Reconfigurable ASIP Design Session Chairs: Koen Bertels, Enno Lübbers M3C_1 A Configurable and Programmable Motion Estimation Processor for the H.264 Video Codec Jose Luis Nunez-Yanez, Eddie Hung and Vassilios Chouliaras M3C_2 A Flexible and Reliable Embedded System for Detector Control in a High Energy Physics Experiment Tobias Krawutschke M3C_3 Area Optimization of Cryptographic Co-Processors Implemented in Dual-Rail with Precharge Positive Logic Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger and Philippe Hoogvorst HS1 Registration Opening Remarks Keynote 1- Break Modelling Session Chairs: Neil Bergmann, Thilo Pionteck M1A_1 Increasing the Level of Abstraction in FPGA-Based Designs Martin Danek, Jiri Kadlec, Roman Bartosinski and Lukas Kohout M1A_2 Modeling Recursion Data Structures for FPGA-based Implementation Spyridon Ninos and Apostolos Dollas M1A_3 A Portable Abstraction Layer for Hardware Threads Enno Lübbers and Marco Platzner Break/Poster Session Keynote 2- Lunch Analysis of Reconfigurability Session Chairs: Joao Cardoso, Felix Reimann M2A_1 Fast and Accurate Resource Estimation of RTL-based Designs Targeting FPGAs Paul Schumacher and Pradip Jha M2A_2 Fast Toggle Rate Computation for FPGA Circuits Tomasz Czajkowski and Stephen Brown M2A_3 On-the-fly Attestation of Reconfigurable Hardware Ricardo Chaves, Georgi Kuzmanov and Leonel Sousa Break/Poster Session Dynamic Reconfiguration Session Chairs: Patrick Lysaght, Gordon Brebner M3A_1 No-Break Dynamic Defragmentation of Reconfigurable Devices Sándor Fekete,Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch and Jürgen Teich M3A_2 ReCoBus-Builder - a Novel Tool and Technique to Build Statically and Dynamically Reconfigurable Systems for FPGAs Dirk Koch, Christian Beckhoff and Jürgen Teich M3A_3 An Efficient Run-time Router for Connecting Modules in FPGAs Jorge Surís, Cameron Patterson and Peter Athanas Break PhD Forum Wine Reception Tuesday, 09 September 2008 Time 08:00 08:30 09:15 09:30 10:00 10:30 11:00 11:30 12:00 12:30 13:00 14:00 14:30 15:00 15:30 16:00 16:30 17:00 17:30 18:00 19:00-22:00 HS2 Novel Applications Session Chairs: Roger Woods, Suhaib Fahmy T1B_1 FPGA Implementation of a flexible decoder for long LDPC codes Christiane Beuschel and Hans-Jörg Pfleiderer T1B_2 Towards an "Early Neural Circuit Simulator": A FPGA Implementation of Processing In the Rat Whisker System Brian Leung,Yan Pan, Chris Schroeder, Seda Memik, Gokhan Memik and Mitra Hartmann T1B_3 Decimal Multiplier on FPGA using Embedded Binary Multipliers Horácio Neto and Mário Véstias Random Number Generation & PLL Session Chairs: Eduardo Boemo, Jose Nunez- Yanez T2B_1 Sampling from the Exponential Distribution using Independent Bernoulli Variates David Barrie Thomas and Wayne Luk T2B_2 Enhancing security of ring oscillator-based TRNG implemented in FPGA Viktor Fischer, Florent Bernard, Nathalie Bochard and Michal Varchola T2B_3 Digital Hilbert Transformers for FPGA- based Phase-Locked Loops Martin Kumm and M. Shahab Sanjari FPGA Application in High Energy Physics Session Chairs: Luciano Musa, Volker Lindenstruth T3B_1 ATCA-based Computation Platform for Data Acquisition and Triggering in Particle Physics Experiments Ming Liu, Tiago Perez, Johannes Lang, Shuo Yang, Wolfgang Kuehn, Hao Xu, Dapeng Jin, Qiang Wang, Lu Li, Zhen'An Liu, Zhonghai Lu and Axel Jantsch T3B_2 An FPGA-based High-speed, Low- latency Trigger Processor for High-energy Physics Jan de Cuveland, Felix Rettig, Venelin Angelov and Volker Lindenstruth High Performance Computing for Financial and Biological Modelling Session Chairs: Tarek El-Ghazawi, George Constantinides T4B_1 FPGA Acceleration of Monte-Carlo Based Credit Derivative Pricing Alexander Kaganov, Asif Lakhany and Paul Chow T4B_2 FPGA Acceleration of Quasi-Monte Carlo in Finance Nathan Woods and Tom VanCourt T4B_3 Acceleration of a Production Rigid Molecule Docking Code Bharat Sukhwani and Martin Herbordt ROOM 1.404 (First Floor) Reconfigurable Processors Session Chairs: Christian Hochberger, Jürgen Becker T1C_1 A Computation- and Communication- Infrastructure for Modular Special Instructions in a Dynamically Reconfigurable Processor Lars Bauer, Muhammad Shafique and Jörg Henkel T1C_2 Application-Adaptive Reconfiguration of Memory Address Shuffler for FPGA- Embedded Instruction-Set Processor Young- Su Kwon and Bon-Tae Koo and Nak-Woong Eum T1C_3 Instruction Buffer Mode for Multi- Context Dynamically Reconfigurable Processors Toru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Hasegawa and Hideharu Amano Networks on Chip II Session Chairs: Klaus Danne, Thilo Streichert T2C_1 MetaWire: Using FPGA Configuration Circuitry to Emulate a Network-on-Chip Matthew Shelburne, Cameron Patterson, Peter Athanas, Mark Jones, Brian Martin and Ryan Fong T2C_2 GICS: Generic Interconnection System Tomáš Málek,Tomáš Martínek and Jan Kořenek T2C_3 A Link Removal Methodology for Networks-on-Chip on Reconfigurable Systems Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi and Hideharu Amano Reconfigurable Processor Arrays Session Chairs: Mladen Berekovic, Stephan Wong T3C_1 Shared Reconfigurable Architectures for CMPs Matthew Watkins, Mark Cianchetti and David Albonesi T3C_2 Power Reduction Techniques for Dynamically Reconfigurable Processor Arrays Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito, Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbunheng and Hideharu Amano DFG Session Foreword DFG Session Exhibition Floor: Fine Grain Reconfigurable Architectures, Coarse-Grained Reconfiguration, Application-Specific Reconfigurable Processors, Seamless Design Flow for Reconfigurable Systems, Network Prosessors, Hyperreconfigurable Architectures HS1 Registration Keynote 3- Break Compilers for Reconfigurable Architectures Session Chairs: Andreas Koch, David Andrews T1A_1 Loop Unrolling and Shifting for Reconfigurable Architectures Ozana Dragomir, Todor Stefanov and Koen Bertels T1A_2 CHiMPS: A C-Level Compilation Flow for Hybrid CPU/FPGA Architectures Andrew Putnam, Dave Bennett, Eric Dellinger, Jeff Mason, Prasanna Sundararajan and Susan Eggers T1A_3 Combining Data Reuse Exploitation with Data-Level Parallelization for FPGA Targeted Hard- ware Compilation: A Geometric Programming Framework Qiang Liu, George Constantinides, Konstantinos Masselos and Peter Cheung Break/Poster Session Analysis of Reconfigurability II Session Chairs: Christophe Wolinski, Josef Angermeier T2A_1 An Analytical Model Describing The Relationships Between Logic Architecture and FPGA Density Andrew Lam, Steve Wilton, Philip Leong and Wayne Luk T2A_2 Rapid Estimation of Power Consumption for Hybrid FPGAs Chun Hok Ho, Philip Leong, Wayne Luk and Steven Wilton T2A_3 A Technique for Minimizing Power During FPGA Placement Kristofer Vorwerk, Madhu Raman, Julien Dunoyer, Yaun-chung Hsu, Arun Kundu and Andrew Kennings Lunch Codesign Session Chairs: Gilles Sassatelli, Peter Zipf T3A_1 Mapping and Scheduling with Task Clustering for Heterogeneous Computing Systems Yuet Ming Lam,Jose Gabriel F. Coutinho, Wayne Luk and Philip Heng Wai Leong T3A_2 Low-Latency High-Bandwidth HW/SW Communication in a Virtual Memory Environment Holger Lange and Andreas Koch Tutorial Break/Poster Session Tools for FPGA Design Session Chairs: Markus Weinhardt, Heiner Giefers T4A_1 An Integrated Debugging Environment for FPGA Computing Platforms Kevin Camera and Robert Brodersen T4A_2 Secure FPGA Configuration Architecture Preventing System Downgrade Benoît Badrignans, Reouven Elbaz and Lionel Torres T4A_3 Bitstream Compression Techniques for Virtex 4 FPGAs Radu Stefan and Sorin Coţ ofană Break/Poster Session Tram/Bus to castle Gala Dinner Ivo Bolsens: FPGA: THE FUTURE PLATFORM FOR TRANSFORMING, TRANSPORTING AND COMPUTING DATA Dan Werthimer: SEARCHING FOR ET WITH FPGAS Peter Alfke: Xilinx Virtex 5 FXT Luciano Musa: FPGAS IN HIGH ENERGY PHYSICS EXPERIMENTS AT CERN Wednesday, 10 September 2008 Time 08:00 08:30 09:15 09:30 10:00 10:30 11:00 11:30 12:00 12:30 13:00 HS2 Algorithm Acceleration Session Chairs: Manfred Glesner, Donald Bailey W1B_1 Novel FPGA based Haar Classifier Face Detection Algorithm Acceleration Changjian Gao and Shih-Lien Lu W1B_2 An FPGA-Based Implementation of the MINRES Algorithm David Boland and George Constantinides W1B_3 Efficient FPGA Mapping of Gilbert`s Algorithm for SVM Training on Large-scale Classification Problems Markos Papadonikolakis and Christos-Savvas Bouganis Surveys and Trends Session Chairs: Michael Hübner, Reiner Hartenstein W2B_1 Reconfigurable Hardware: The Holy Grail of Matching Performance with Programming Productivity Claudio Brunelli, Fabio Campi, Damien Picard, Fabio Garzia and Jari Nurmi W2B_2 Fault Tolerant Methods for Reliability in FPGAs Edward Stott, Pete Sedcole and Peter Cheung W2B_3 A Non-voltile Run-time FPGA using Thermally Assisted Switching MRAMs Yoann Guillemenet, Lionel Torres, Gilles Sassatelli, Nicolas Bruchon and Ilham Hassoune ROOM 1.404 (First Floor) Industrial Presentations Session Chair: Endric Schubert, Christophe Layer W1C_1: Beyond FPGAs: Flexible Coarse-Grained Reconfigurable Multi-Cores Solving Impeding Performance, Power and Cost Constraints Paul Heysters Recore Systems W1C_2 Next Generation Algorithmic Synthesis Crossing the Gap between Algorithm and Hardware Architecture Michael Bierl Mentor Graphics W1C_3 Top-down design flow for implemen- ting hardware and software systems Prashant Rao, The MathWorks Industrial Presentations Session Chairs: Thomas Irmen, Christophe Layer W2C_1 Mixed Signal FPGA for Integrated System Management Mike Brogley W2C_2 : C to gates: different tools for different tasks Tom Van Court, Altera W2C_3: Software Defined Silicon - a revolution in electronic product design Henk Muller, XMOS Semiconductor HS1 Registration Keynote 4- Break Synthesis Session Chairs: Uli Heinkel, Dirk Koch W1A_1 Floating Point Datapath Synthesis for FPGAs Martin Langhammer W1A_2 Automatic Generation of Run-time Parameterizable Configurations Karel Bruneel and Dirk Stroobandt W1A_3 Generation of partial FPGA configura- tions at run-time Miguel L. Silva and João Canas Ferreira Break/Poster Session Optimization Session Chairs: Christian Plessl, Wayne Luk W2A_1 Area and Reconfiguration Time Minimization of the Communication Network in Regular 2D Reconfigurable Architectures Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich and Frank Hannig W2A_2 An Symbolic Decomposition of Functions with Multi-valued Inputs and Outputs for FPGA-based Implementation Stanislaw Deniziak and Mariusz Wiśniewski W2A_3 Memory Access Parallelization in High- Level Language Compilation for Reconfigurable Adaptive Computers Hagen Gädke, Florian Stock and Andreas Koch Closing remarks Conference Close Otto Wohlmuth: HIGH PERFORMANCE COMPUTING BASED ON FPGAS Workshops Wednesday, 10 September 2008 Thursday, September 11 - Friday, September 12, 2008 THE MATHWORKS:Top Down System Flow - A detailed Technical Demonstration, Room 3.401 (Third Floor) SYNPLICITY: Prototyping as a Productive Verification Methodology, Room 2.404 (Second Floor) XILINX: Introduction to PlanAhead and Partial Reconfiguration, Room 1.404 (First Floor) XILINX: Embedded Systems Design and Partial Reconfiguration, Room 1.404 (First Floor) Time 14:00 Time 09:00 Programm FPL1 Kopie1:Programm FPL1 22.08.2008 8:31 Uhr Seite 1