MM

N.PR.COLLEGE OF ENGINEERING AND TECHNOLOGY

NATHAM

NAME OF THE STAFF :T.KAVITHA

DEPARTMENT :ECE

DESIGNATION : ASSISTANT PROFESSOR

SUB.CODE :EC1301

SUB.NAME :MICROPROCESSOR AND MICROCONTROLLER

YEAR/SEM : III EEE / V SEM

ACADEMIC YEAR : 2010-2011

SYLLABUS:

EC1301 – MICROPROCESSORS AND MICROCONTROLLERS

L T P C 0 0 3

UNIT I 8085 MICROPROCESSOR 9

8085 architecture – Instruction set – Addressing modes – Timing diagrams – Assembly

language programming – Counters – Time delays – Interrupts – Memory interfacing –

Interfacing, I/O devices.

UNIT II PERIPHERALS INTERFACING OF 8085 9

Interfacing serial I/O (8251) – Parallel I/O (8255) – Keyboard and display controller

(8279) – ADC/DAC interfacing – Inter Integrated Circuits interfacing (I2C Standard) –

Bus: RS232C – RS485 – GPIB

UNIT III 8086 MICROPROCESSOR 9

8086 internal architecture – 8086 addressing modes – Instruction set – 8086 assembly

language programming – Interrupts.

UNIT IV 8051 MICROCONTROLLER 9

8051 micro controller hardware – I/O pins, ports and circuits – External memory –

Counters and timers – Serial data I/O – Interrupts – Interfacing to external memory and

8255.

UNIT V 8051 PROGRAMMING AND APPLICATIONS 9

8051 instruction set – Addressing modes – Assembly language programming – I/O port

programming – Timer and counter programming – Serial communication – Interrupt

programming – 8051 interfacing – LCD – ADC – Sensors – Stepper motors – Keyboard

and DAC.

Total: 45

TEXT BOOKS

1. Ramesh S. Gaonkar, ―Microprocessor Architecture, Programming and application

with 8085‖, 4th Edition, PHI, 2000.

2. John Uffenbeck, ―The 80x86 Families, Design, Programming and Interfacing‖,

3rd Edition, Pearson Education, 2002.

3. Mohammed Ali Mazidi and Janice Gillispie Mazidi, ―The 8051 Microcontroller

and Embedded Systems‖, Pearson Education Asia, 2003.

REFERENCES

1. Ray A.K. and Burchandi K.M., ―Intel Microprocessors Architecture

Programming and Interfacing‖, TMH, 2000

2. Kenneth J. Ayala, ―The 8051 Microcontroller Architecture Programming and

Application‖, 2nd Edition, Penram International Publishers (India), 1996.

3. Rafiquzhman M., ―Microprocessors Theory and Applications: Intel and

Motorola‖, PHI Pvt. Ltd., 2003.

UNIT I 8085 MICROPROCESSOR

8085 Architecture:

8085 architecture – Instruction set – Addressing modes – Timing diagrams – Assembly

language programming – Counters – Time delays – Interrupts – Memory interfacing –

Interfacing, I/O devices.

Internal Architecture of 8085 Microprocessor

Control Unit

Generates signals within uP to carry out the instruction, which has been decoded. In

reality causes certain connections between blocks of the uP to be opened or closed, so

that data goes where it is required, and so that ALU operations occur.

Arithmetic Logic Unit

The ALU performs the actual numerical and logic operation such as ‗add‘, ‗subtract‘,

‗AND‘, ‗OR‘, etc. Uses data from memory and from Accumulator to perform

arithmetic. Always stores result of operation in Accumulator.

Registers

The 8085/8080A-programming model includes six registers, one accumulator, and

one flag register, as shown in Figure. In addition, it has two 16-bit registers: the stack

pointer and the program counter. They are described briefly as follows.

The 8085/8080A has six general-purpose registers to store 8-bit data; these are

identified as B,C,D,E,H, and L as shown in the figure. They can be combined as

register pairs - BC, DE, and HL - to perform some 16-bit operations. The

programmer can use these registers to store or copy data into the registers by using

data copy instructions.

Accumulator

The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This

register is used to store 8-bit data and to perform arithmetic and logical operations.

The result of an operation is stored in the accumulator. The accumulator is also

identified as register A.

Flags

The ALU includes five flip-flops, which are set or reset after an operation according

to data conditions of the result in the accumulator and other registers. They are called

Zero(Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags; they are

listed in the Table and their bit positions in the flag register are shown in the Figure

below. The most commonly used flags are Zero, Carry, and Sign. The microprocessor

uses these flags to test data conditions.

For example, after an addition of two numbers, if the sum in the accumulator id larger

than eight bits,

the flip-flop uses to indicate a carry -- called the Carry flag (CY) – is set to one. When

an arithmetic

operation results in zero, the flip-flop called the

Zero(Z) flag is set to one. The first Figure shows an 8-bit register, called the flag

register, adjacent to the accumulator. However, it is not used as a register; five bit

positions out of eight are used to store the outputs of the five flip-flops. The flags are

stored in the 8-bit register so that the programmer can examine these flags (data

conditions) by accessing the register through an instruction.

These flags have critical importance in the decision-making process of the microprocessor.

The conditions (set or reset) of the flags are tested through the software

instructions. For example, the instruction JC (Jump on Carry) is implemented to

change the sequence of a program when CY flag is set. The thorough understanding

of flag is essential in writing assembly language programs.

Program Counter (PC)

This 16-bit register deals with sequencing the execution of instructions. This register

is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a

16-bit register.

The microprocessor uses this register to sequence the execution of the instructions.

The function of the program counter is to point to the memory address from which the

next byte is to be fetched. When a byte (machine code) is being fetched, the program

counter is incremented by one to point to the next memory location

Stack Pointer (SP)

The stack pointer is also a 16-bit register used as a memory pointer. It points to a

memory location in R/W memory, called the stack. The beginning of the stack is

defined by loading 16-bit address in the stack pointer. The stack concept is explained

in the chapter "Stack and Subroutines."

Instruction Register/Decoder

Temporary store for the current instruction of a program. Latest instruction sent here

from memory prior to execution. Decoder then takes instruction and ‗decodes‘ or

interprets the instruction. Decoded instruction then passed to next stage.

Memory Address Register

Holds address, received from PC, of next program instruction. Feeds the address bus

with addresses of location of the program under execution.

Control Generator

Generates signals within uP to carry out the instruction which has been decoded. In

reality causes certain connections between blocks of the uP to be opened or closed, so

that data goes where it is required, and so that ALU operations occur.

Register Selector

This block controls the use of the register stack in the example. Just a logic circuit

which switches between different registers in the set will receive instructions from

Control Unit.

General Purpose Registers

uP requires extra registers for versatility. Can be used to store additional data during a

program. More complex processors may have a variety of differently named registers.

Microprogramming

How does the μP knows what an instruction means, especially when it is only a

binary number? The microprogram in a uP/uC is written by the chip designer and tells

the uP/uC the meaning of each instruction uP/uC can then carry out operation.

2. 8085 System Bus:

Typical system uses a number of busses, collection of wires, which transmit binary

numbers, one bit per wire. A typical microprocessor communicates with memory and

other devices (input and output) using three busses: Address Bus, Data Bus and

Control Bus.

Address Bus

One wire for each bit, therefore 16 bits = 16 wires. Binary number carried alerts

memory to ‗open‘ the designated box. Data (binary) can then be put in or taken

out.The Address Bus consists of 16 wires, therefore 16 bits. Its "width" is 16 bits. A

16 bit binary number allows 216 different numbers, or 32000 different numbers, ie

0000000000000000 up to 1111111111111111. Because memory consists of boxes,

each with a unique address, the size of the address bus determines the size of memory,

which can be used. To communicate with memory the microprocessor sends an

address on the address bus, eg 0000000000000011 (3 in decimal), to the memory. The

memory the selects box number 3 for reading or writing data. Address bus is

unidirectional, ie numbers only sent from microprocessor to memory, not other way.

Question?: If you have a memory chip of size 256 kilobytes (256 x 1024 x 8 bits),

how many wires does the address bus need, in order to be able to specify an address in

this memory? Note: the memory is organized in groups of 8 bits per location,

therefore, how many locations must you be able to specify?

Data Bus

Data Bus: carries ‗data‘, in binary form, between μP and other external units, such as

memory. Typical size is 8 or 16 bits. Size determined by size of boxes in memory and

μP size helps determine performance of μP. The Data Bus typically consists of 8

wires. Therefore, 28 combinations of binary digits. Data bus used to transmit "data",

ie information, results of arithmetic, etc, between memory and the microprocessor.

Bus is bi-directional. Size of the data bus determines what arithmetic can be done. If

only 8 bits wide then largest number is 11111111 (255 in decimal). Therefore, larger

number have to be broken down into chunks of 255. This slows microprocessor. Data

Bus also carries instructions from memory to the microprocessor. Size of the bus

therefore limits the number of possible instructions to 256, each specified by a

separate number.

Control Bus

Control Bus are various lines which have specific functions for coordinating and

controlling uP operations. Eg: Read/NotWrite line, single binary digit. Control

whether memory is being ‗written to‘ (data stored in mem) or ‗read from‘ (data taken

out of mem) 1 = Read, 0 = Write. May also include clock line(s) for

timing/synchronising, ‗interrupts‘, ‗reset‘ etc. Typically μP has 10 control lines.

Cannot function correctly without these vital control signals.

The Control Bus carries control signals partly unidirectional, partly bi-directional.

Control signals are things like "read or write". This tells memory that we are either

reading from a location, specified on the address bus, or writing to a location

specified. Various other signals to control and coordinate the operation of the system.

Modern day microprocessors, like 80386, 80486 have much larger busses. Typically

16 or 32 bit busses, which allow larger number of instructions, more memory

location, and faster arithmetic. Microcontrollers organized along same lines, except:

because microcontrollers have memory etc inside the chip, the busses may all be

internal. In the microprocessor the three busses are external to the chip (except for the

internal data bus). In case of external busses, the chip connects to the busses via

buffers, which are simply an electronic connection between external bus and the

internal data bus.

3. 8085 Pin description.

Properties

Single + 5V Supply

4 Vectored Interrupts (One is Non Maskable)

Serial In/Serial Out Port

Decimal, Binary, and Double Precision Arithmetic

Direct Addressing Capability to 64K bytes of memory

The Intel 8085A is a new generation, complete 8 bit parallel central processing unit

(CPU). The 8085A uses a multiplexed data bus. The address is split between the 8bit

address bus and the 8bit data bus. Figures are at the end of the document.

Pin Description

The following describes the function of each pin:

A6 - A1s (Output 3 State)

Address Bus; The most significant 8 bits of the memory address or the 8 bits of the I/0

address,3 stated during Hold and Halt modes.

AD0 - 7 (Input/Output 3state)

Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0 address) appear on

the bus during the first clock cycle of a machine state. It then becomes the data bus during the

second and third clock cycles. 3 stated during Hold and Halt modes.

ALE (Output)

Address Latch Enable: It occurs during the first clock cycle of a machine state and

enables the address to get latched into the on chip latch of peripherals. The falling

edge of ALE is set to guarantee setup and hold times for the address information.

ALE can also be used to strobe the status information. ALE is never 3stated.

SO, S1 (Output) Data Bus Status. Encoded status of the bus cycle:

S1 S0

O O HALT

0 1 WRITE

1 0 READ

1 1 FETCH

S1 can be used as an advanced R/W status.

RD (Output 3state)

READ; indicates the selected memory or 1/0 device is to be read and that the Data

Bus is available for the data transfer.

WR (Output 3state)

WRITE; indicates the data on the Data Bus is to be written into the selected memory

. Data is set up at the trailing edge of WR. 3stated during Hold and Halt

modes.

READY (Input)

If Ready is high during a read or write cycle, it indicates that the memory or

peripheral is ready to send or receive data. If Ready is low, the CPU will wait for

Ready to go high before completing the read or write cycle.

HOLD (Input)

HOLD; indicates that another Master is requesting the use of the Address and Data

Buses. The CPU, upon receiving the Hold request. will relinquish the use of buses as

soon as the completion of the current machine cycle. Internal processing can continue.

The processor can regain the buses only after the Hold is removed. When the Hold is

Acknowledged, the Address, Data, RD, WR, and IO/M lines are 3stated.

HLDA (Output)

HOLD ACKNOWLEDGE; indicates that the CPU has received the Hold request and

that it will relinquish the buses in the next clock cycle. HLDA goes low after the Hold

request is removed. The CPU takes the buses one half clock cycle after HLDA goes

low.

INTR (Input)

INTERRUPT REQUEST; is used as a general purpose interrupt. It is sampled only

during the next to the last clock cycle of the instruction. If it is active, the Program

Counter (PC) will be inhibited from incrementing and an INTA will be issued. During

this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt

service routine. The INTR is enabled and disabled by software. It is disabled by Reset

and immediately after an interrupt is accepted.

INTA (Output)

INTERRUPT ACKNOWLEDGE; is used instead of (and has the same timing as) RD

during the Instruction cycle after an INTR is accepted. It can be used to activate the

8259 Interrupt chip or some other interrupt port.

RST 5.5

RST 6.5 - (Inputs)

RST 7.5

RESTART INTERRUPTS;

These three inputs have the same timing as I NTR except

they cause an internal RESTART to be automatically inserted.

RST 7.5 ~~ Highest Priority

RST 6.5

RST 5.5 o Lowest Priority

The priority of these interrupts is ordered as shown above. These interrupts have a

higher priority than the INTR.

TRAP (Input)

Trap interrupt is a nonmaskable restart interrupt. It is recognized at the same time as

INTR. It is unaffected by any mask or Interrupt Enable. It has the highest priority of

any interrupt.

RESET IN (Input)

Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA

flipflops. None of the other flags or registers (except the instruction register) are

affected The CPU is held in the reset condition as long as Reset is applied.

RESET OUT (Output)

Indicates CPlJ is being reset. Can be used as a system RESET. The signal is

synchronized to the processor clock.

X1, X2 (Input)

Crystal or R/C network connections to set the internal clock generator X1 can also be

an external clock input instead of a crystal. The input frequency is divided by 2 to

give the internal operating frequency.

CLK (Output)

Clock Output for use as a system clock when a crystal or R/ C network is used as an

input to the CPU. The period of CLK is twice the X1, X2 input period.

IO/M (Output)

IO/M indicates whether the Read/Write is to memory or l/O Tristated during Hold and

Halt modes.

SID (Input)

Serial input data line The data on this line is loaded into accumulator bit 7 whenever a

RIM instruction is executed.

SOD (output)

Serial output data line. The output SOD is set or reset as specified by the SIM

instruction.

Vcc

+5 volt supply.

Vss

Ground Reference.

4. 8085 Functional Description

The 8085A is a complete 8 bit parallel central processor. It requires a single +5 volt

supply. Its basic clock speed is 3 MHz thus improving on the present 8080's

performance with higher system speed. Also it is designed to fit into a minimum

system of three IC's: The CPU, a RAM/ IO, and a ROM or PROM/IO chip.

The 8085A uses a multiplexed Data Bus. The address is split between the higher 8bit

Address Bus and the lower 8bit Address/Data Bus. During the first cycle the address

is sent out. The lower 8bits are latched into the peripherals by the Address Latch

Enable (ALE). During the rest of the machine cycle the Data Bus is used for memory

or l/O data.

The 8085A provides RD, WR, and lO/Memory signals for bus control. An Interrupt

Acknowledge signal (INTA) is also provided. Hold, Ready, and all Interrupts are

synchronized. The 8085A also provides serial input data (SID) and serial output data

(SOD) lines for simple serial interface.

In addition to these features, the 8085A has three maskable, restart interrupts and one

non-maskable trap interrupt. The 8085A provides RD, WR and IO/M signals for Bus

control.

Status Information

Status information is directly available from the 8085A. ALE serves as a status strobe.

The status is partially encoded, and provides the user with advanced timing of the

type of bus transfer being done. IO/M cycle status signal is provided directly also.

Decoded So, S1 Carries the following status information:

HALT, WRITE, READ, FETCH

S1 can be interpreted as R/W in all bus transfers. In the 8085A the 8 LSB of address

are multiplexed with the data instead of status. The ALE line is used as a strobe to

enter the lower half of the address into the memory or peripheral address latch. This

also frees extra pins for expanded interrupt capability.

Interrupt and Serial l/O:

The8085A has5 interrupt inputs: INTR, RST5.5, RST6.5, RST 7.5, and TRAP. INTR

is identical in function to the 8080 INT. Each of the three RESTART inputs, 5.5, 6.5.

7.5, has a programmable mask. TRAP is also a RESTART interrupt except it is nonmaskable.

The three RESTART interrupts cause the internal execution of RST (saving the program

counter in the stack and branching to the RESTART address) if the interrupts are enabled and if

the interrupt mask is not set. The non-maskable TRAP causes the internal execution of a RST

independent of the state of the interrupt enable or masks. The interrupts are arranged in a fixed

priority that determines which interrupt is to be recognized if more than one is pending as

follows: TRAP highest priority, RST 7.5,

RST 6.5, RST 5.5, INTR lowest priority This priority scheme does not take into

account the priority of a routine that was started by a higher priority interrupt. RST

5.5 can interrupt a RST 7.5 routine if the interrupts were re-enabled before the end of

the RST 7.5 routine. The TRAP interrupt is useful for catastrophic errors such as

power failure or bus error. The TRAP input is recognized just as any other interrupt

but has the highest priority. It is not affected by any flag or mask. The TRAP input is

both edge and level sensitive.

Basic System Timing

The 8085A has a multiplexed Data Bus. ALE is used as a strobe to sample the lower

8bits of address on the Data Bus. Figure 2 shows an instruction fetch, memory read

and l/ O write cycle (OUT). Note that during the l/O write and read cycle that the l/O

port address is copied on both the upper and lower half of the address. As in the 8080,

the READY line is used to extend the read and write pulse lengths so that the 8085A

can be used with slow memory. Hold causes the CPU to relingkuish the bus when it is

through with it by floating the Address and Data Buses.

System Interface

8085A family includes memory components, which are directly compatible to the

8085A CPU. For example, a system consisting of the three chips, 8085A, 8156, and

8355 will have the following features:

· 2K Bytes ROM

· 256 Bytes RAM

· 1 Timer/Counter

· 4 8bit l/O Ports

· 1 6bit l/O Port

· 4 Interrupt Levels

· Serial In/Serial Out Ports

In addition to standard l/O, the memory mapped I/O offers an efficient l/O addressing

technique. With this technique, an area of memory address space is assigned for l/O

address, thereby, using the memory address for I/O manipulation. The 8085A CPU

can also interface with the standard memory that does not have the multiplexed

address/data bus.

5. The 8085 Programming Model

In the previous tutorial we described the 8085 microprocessor registers in reference to

the internal data operations. The same information is repeated here briefly to provide

the continuity and the context to the instruction set and to enable the readers who

prefer to focus initially on the programming aspect of the microprocessor.

The 8085 programming model includes six registers, one accumulator, and one flag

register, as shown in Figure. In addition, it has two 16-bit registers: the stack pointer

and the program counter. They are described briefly as follows.

Registers

The 8085 has six general-purpose registers to store 8-bit data; these are identified as

B,C,D,E,H, and L as shown in the figure. They can be combined as register pairs -

BC, DE, and HL - to perform some 16-bit operations. The programmer can use these

registers to store or copy data into the registers by using data copy instructions.

Accumulator

The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This

register is used to store 8-bit data and to perform arithmetic and logical operations.

The result of an operation is stored in the accumulator. The accumulator is also

identified as register A.

ACCUMULATOR A (8) FLAG REGISTER

B (8)

D (8)

H (8)

Stack Pointer (SP) (16)

Program Counter (PC) (16)

C (8)

E (8)

L (8)

Data Bus Address Bus

8 Lines Bidirectional 16 Lines unidirectional

Flags

The ALU includes five flip-flops, which are set or reset after an operation according

to data conditions of the result in the accumulator and other registers. They are called

Zero(Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags; their bit

positions in the flag register are shown in the Figure below. The most commonly used

flags are Zero, Carry, and Sign. The microprocessor uses these flags to test data

conditions.

For example, after an addition of two numbers, if the sum in the accumulator id larger

than eight bits, the flip-flop uses to indicate a carry -- called the Carry flag (CY) – is set to one.

When an arithmetic operation results in zero, the flip-flop called the

Zero(Z) flag is set to one. The first Figure shows an 8-bit register, called the flag

register, adjacent to the accumulator. However, it is not used as a register; five bit

positions out of eight are used to store the outputs of the five flip-flops. The flags are

stored in the 8-bit register so that the programmer can examine these flags (data

conditions) by accessing the register through an instruction.

These flags have critical importance in the decision-making process of the

microprocessor. The conditions (set or reset) of the flags are tested through the software

instructions. For example, the instruction JC (Jump on Carry) is implemented to

change the sequence of a program when CY flag is set. The thorough understanding

of flag is essential in writing assembly language programs.

Program Counter (PC)

This 16-bit register deals with sequencing the execution of instructions. This register

is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a

16-bit register.

The microprocessor uses this register to sequence the execution of the instructions.

The function of the program counter is to point to the memory address from which the

next byte is to be fetched. When a byte (machine code) is being fetched, the program

counter is incremented by one to point to the next memory location

Stack Pointer (SP)

The stack pointer is also a 16-bit register used as a memory pointer. It points to a

memory location in R/W memory, called the stack. The beginning of the stack is

defined by loading 16-bit address in the stack pointer.

This programming model will be used in subsequent tutorials to examine how these

registers are affected after the execution of an instruction.

D7 D6 D5 D4 D3 D2 D1 D0

6. The 8085 Addressing Modes

Addressing Modes of 8085

To perform any operation, we have to give the corresponding instructions to the

microprocessor.

In each instruction, programmer has to specify 3 things:

Operation to be performed.

Address of source of data.

Address of destination of result.

The method by which the address of source of data or the address of destination of result is

given in the instruction is called Addressing Modes. The term addressing mode refers to the

way in which the operand of the instruction is specified.

Types of Addressing Modes

Intel 8085 uses the following addressing modes:

1. Direct Addressing Mode

2. Register Addressing Mode

3. Register Indirect Addressing Mode

4. Immediate Addressing Mode

5. Implicit Addressing Mode

Direct Addressing Mode

In this mode, the address of the operand is given in the instruction itself.

LDA 4500H- Load the contents of memory location 4500H in accumulatorDA2500

tor.

LDA is the operation.

4500 H is the address of source.

Accumulator is the destination.

Register Addressing Mode

In this mode, the operand is in general purpose register.

MOV A,B – Move the contents of register B to A

MOV is the operation.

B is the source of data.

A is the destination.

Register Indirect Addressing Mode

In this mode, the address of operand is specified by a register pair.

MOVA,M- Move data from memory location specified by HL pair to accumulator

MOV is the operation.

M is the memory location specified by H-L register pair.

A is the destination

Immediate Addressing Mode

In this mode, the operand is specified within the instruction itself.

MVI A,05 H- Move 05 H in accumulator

MVI is the operation.

05 H is the immediate data (source).

A is the destination

Implicit Addressing Mode

If address of source of data as well as address of destination of result is fixed,

then there is no need to give any operand along with the instruction.

CMA- Complement Accumulator

CMA is the operation.

A is the source.

A is the destination.

The instructions MOV B, A or MVI A, 82H are to copy data from a source into a

destination. In these instructions the source can be a register, an input port, or an 8-bit

number (00H to FFH). Similarly, a destination can be a register or an output port. The

sources and destination are operands. The various formats for specifying operands are

called the ADDRESSING MODES. For 8085, they are:

1. Immediate addressing.

2. Register addressing.

3. Direct addressing.

4. Indirect addressing.

Immediate addressing

Data is present in the instruction. Load the immediate data to the destination provided.

Example: MVI R,data

Register addressing

Data is provided through the registers.

Example: MOV Rd, Rs

Direct addressing

Used to accept data from outside devices to store in the accumulator or send the data

stored in the accumulator to the outside device. Accept the data from the port 00H and

store them into the accumulator or Send the data from the accumulator to the port 01H.

Example: IN 00H or OUT 01H

Indirect Addressing

This means that the Effective Address is calculated by the processor. And the

contents of the address (and the one following) is used to form a second address. The

second address is where the data is stored. Note that this requires several memory

accesses; two accesses to retrieve the 16-bit address and a further access (or accesses)

to retrieve the data which is to be loaded into the register.

7. Instruction Set Classification

An instruction is a binary pattern designed inside a microprocessor to perform a

specific function. The entire group of instructions, called the instruction set,

determines what functions the microprocessor can perform. These instructions can be

classified into the following five functional categories: data transfer (copy)

operations, arithmetic operations, logical operations, branching operations, and

machine-control operations.

Data Transfer (Copy) Operations

This group of instructions copy data from a location called a source to another

location called a destination, without modifying the contents of the source. In

technical manuals, the term data transfer is used for this copying function. However,

the term transfer is misleading; it creates the impression that the contents of the

source are destroyed when, in fact, the contents are retained without any modification.

The various types of data transfer (copy) are listed below together with examples of

each type:

Types

Examples

1. Between Registers.

Copy the contents of the register B into register D.

2. Specific data byte to a register or a memory location.

Load register B with the data byte 32H.

3. Between a memory location and a register.

From a memory location 2000H to register B.

4. Between an I/O device and the accumulator.

From an input keyboard to the accumulator.

Arithmetic Operations

These instructions perform arithmetic operations such as addition, subtraction,

increment, and decrement.

Addition - Any 8-bit number, or the contents of a register or the contents of a

memory location can be added to the contents of the accumulator and the sum is

stored in the accumulator. No two other 8-bit registers can be added directly (e.g., the

contents of register B cannot be added directly to the contents of the register C). The

instruction DAD is an exception; it adds 16-bit data directly in register pairs.

Subtraction - Any 8-bit number, or the contents of a register, or the contents of a

memory location can be subtracted from the contents of the accumulator and the

results stored in the accumulator. The subtraction is performed in 2's compliment, and

the results if negative, are expressed in 2's complement. No two other registers can be

subtracted directly.

Increment/Decrement - The 8-bit contents of a register or a memory location can be

incremented or decrement by 1. Similarly, the 16-bit contents of a register pair (such

as BC) can be incremented or decrement by 1. These increment and decrement

operations differ from addition and subtraction in an important way; i.e., they can be

performed in any one of the registers or in a memory location.

Logical Operations

These instructions perform various logical operations with the contents of the

accumulator.

AND, OR Exclusive-OR - Any 8-bit number, or the contents of a register, or of

a memory location can be logically ANDed, Ored, or Exclusive-ORed with the

contents of the accumulator. The results are stored in the accumulator.

Rotate- Each bit in the accumulator can be shifted either left or right to the next

position.

Compare- Any 8-bit number, or the contents of a register, or a memory location can

be compared for equality, greater than, or less than, with the contents of the

accumulator.

Complement - The contents of the accumulator can be complemented. All 0s are

replaced by 1s and all 1s are replaced by 0s.

Branching Operations

This group of instructions alters the sequence of program execution either

conditionally or unconditionally.

Jump - Conditional jumps are an important aspect of the decision-making process in

the programming. These instructions test for a certain conditions (e.g., Zero or Carry

flag) and alter the program sequence when the condition is met. In addition, the

instruction set includes an instruction called unconditional jump.

Call, Return, and Restart - These instructions change the sequence of a program

either by calling a subroutine or returning from a subroutine. The conditional Call and

Return instructions also can test condition flags.

Machine Control Operations

These instructions control machine functions such as Halt, Interrupt, or do nothing.

The microprocessor operations related to data manipulation can be summarized in

four functions:

1. copying data

2. performing arithmetic operations

3. performing logical operations

4. testing for a given condition and alerting the program sequence

Some important aspects of the instruction set are noted below:

1. In data transfer, the contents of the source are not destroyed; only the contents of

the destination are changed. The data copy instructions do not affect the flags.

2. Arithmetic and Logical operations are performed with the contents of the

accumulator, and the results are stored in the accumulator (with some

expectations). The flags are affected according to the results.

3. Any register including the memory can be used for increment and decrement.

4. A program sequence can be changed either conditionally or by testing for a given

data condition.

8. Instruction Format

An instruction is a command to the microprocessor to perform a given task on a

specified data. Each instruction has two parts: one is task to be performed, called the

operation code (opcode), and the second is the data to be operated on, called the

operand. The operand (or data) can be specified in various ways. It may include 8-bit

(or 16-bit ) data, an internal register, a memory location, or 8-bit (or 16-bit) address.

In some instructions, the operand is implicit.

Instruction word size

The 8085 instruction set is classified into the following three groups according to

word size:

1. One-word or 1-byte instructions

2. Two-word or 2-byte instructions

3. Three-word or 3-byte instructions

In the 8085, "byte" and "word" are synonymous because it is an 8-bit microprocessor.

However, instructions are commonly referred to in terms of bytes rather than words.

One-Byte Instructions

A 1-byte instruction includes the opcode and operand in the same byte. Operand(s)

are internal register and are coded into the instruction.

For example:

Task Opcode Operand Binary Code Hex Code

Copy the contents of the accumulator in the register C.

MOV C,A 0100 1111 4FH

Add the contents of register B to the contents of the accumulator.

ADD B 1000 0000 80H

Invert (compliment) each bit in the accumulator.

CMA 0010 1111 2FH

These instructions are 1-byte instructions performing three different tasks. In the first

instruction, both operand registers are specified. In the second instruction, the operand

B is specified and the accumulator is assumed. Similarly, in the third instruction, the

accumulator is assumed to be the implicit operand. These instructions are stored in 8-

bit binary format in memory; each requires one memory location.

MOV rd, rs

rd <-- rs copies contents of rs into rd.

Coded as 01 ddd sss where ddd is a code for one of the 7 general registers which is

the destination of the data, sss is the code of the source register.

Example: MOV A,B

Coded as 01111000 = 78H = 170 octal (octal was used extensively in instruction

design of such processors).

ADD r

A <-- A + r

Two-Byte Instructions

In a two-byte instruction, the first byte specifies the operation code and the second

byte specifies the operand. Source operand is a data byte immediately following the

opcode. For example:

Task Opcode Operand Binary Code Hex Code

Load an 8-bit data byte in the accumulator.

MVI A, Data 3E

Data

First Byte

Second Byte

Assume that the data byte is 32H. The assembly language instruction is written as

Mnemonics Hex code

MVI A, 32H 3E 32H

The instruction would require two memory locations to store in memory.

MVI r,data

r <-- data

Example: MVI A,30H coded as 3EH 30H as two contiguous bytes. This is an

example of immediate addressing.

ADI data

A <-- A + data

OUT port

0011 1110

DATA

where port is an 8-bit device address. (Port) <-- A. Since the byte is not the data but

points directly to where it is located this is called direct addressing.

Three-Byte Instructions

In a three-byte instruction, the first byte specifies the opcode, and the following two

bytes specify the 16-bit address. Note that the second byte is the low-order address

and the third byte is the high-order address.

opcode + data byte + data byte

For example:

Task Opcode Operand Binary code Hex Code

Transfer the program sequence to the memory location 2085H.

JMP 2085H C3

85

20

First byte

Second Byte

Third Byte

This instruction would require three memory locations to store in memory.

Three byte instructions - opcode + data byte + data byte

LXI rp, data16

rp is one of the pairs of registers BC, DE, HL used as 16-bit registers. The two data

bytes are 16-bit data in L H order of significance.

rp <-- data16

Example:

LXI H,0520H coded as 21H 20H 50H in three bytes. This is also immediate

addressing.

LDA addr

A <-- (addr) Addr is a 16-bit address in L H order. Example: LDA 2134H coded as

3AH 34H 21H. This is also an example of direct addressing.

9. Sample Programs

Write an assembly program to add two numbers

Program

MVI D, 8BH

MVI C, 6FH

MOV A, C

1100 0011

1000 0101

0010 0000

ADD D

OUT PORT1

HLT

Write an assembly program to multiply a number by 8

Program

MVI A, 30H

RRC

RRC

RRC

OUT PORT1

HLT

Write an assembly program to find greatest between two numbers

Program

MVI B, 30H

MVI C, 40H

MOV A, B

CMP C

JZ EQU

JC GRT

OUT PORT1

HLT

EQU: MVI A, 01H

OUT PORT1

HLT

GRT: MOV A, C

OUT PORT1

HLT

Differences between Intel 8080 and 8085 processors

Features

8080 8085

1. Processorspeed (MHz)

2

- 3.1 3 - 6

2. Power supply

+5V,-

5Vand +12V

+5V

3. On-chip peripherals

Clock oscillator (similar to 8224)

system controller (similar to 8228)

Serial I/O lines

4. Address/Data bus

Separate

address and

data busses

Multiplexed address and

data

5. Pins/signals

Reset Out pin

RD bus signal

WR bus signal

IO/MM bus signal

ALE pin provides encoded

bus

status information

6. Interrupts

Three maskable interrupts and one

non- maskable

7. Instruction set

RIM - read interrupt mask

SIM - Set interrupt mask

8085 microprocessor questions

1. What are the various registers in 8085? - Accumulator register, Temporary register,

Instruction register, Stack Pointer, Program Counter are the various registers in 8085 .

2. In 8085 name the 16 bit registers? - Stack pointer and Program counter all have 16 bits.

3. What are the various flags used in 8085? - Sign flag, Zero flag, Auxillary flag, Parity flag,

Carry flag.

4. What is Stack Pointer? - Stack pointer is a special purpose 16-bit register in the

Microprocessor, which holds the address of the top of the stack.

5. What is Program counter? - Program counter holds the address of either the first byte of the

next instruction to be fetched for execution or the address of the next byte of a multi byte

instruction, which has not been completely fetched. In both the cases it gets incremented

automatically one by one as the instruction bytes get fetched. Also Program register keeps the

address of the next instruction.

6. Which Stack is used in 8085? - LIFO (Last In First Out) stack is used in 8085.In this type of

Stack the last stored information can be retrieved first.

7. What happens when HLT instruction is executed in processor? - The Micro Processor enters

into Halt-State and the buses are tri-stated.

8. What is meant by a bus? - A bus is a group of conducting lines that carriers data, address, &

control signals.

9. What is Tri-state logic? - Three Logic Levels are used and they are High, Low, High

impedance state. The high and low are normal logic levels & high impedance state is electrical

open circuit conditions. Tri-state logic has a third line called enable line.

10. Give an example of one address microprocessor? - 8085 is a one address microprocessor.

11. In what way interrupts are classified in 8085? - In 8085 the interrupts are classified as

Hardware and Software interrupts.

12. What are Hardware interrupts? - TRAP, RST7.5, RST6.5, RST5.5, INTR.

13. What are Software interrupts? - RST0, RST1, RST2, RST3, RST4, RST5, RST6, RST7.

14. Which interrupt has the highest priority? - TRAP has the highest priority.

15. Name 5 different addressing modes? - Immediate, Direct, Register, Register indirect, Implied

addressing modes.

16. How many interrupts are there in 8085? - There are 12 interrupts in 8085.

17. What is clock frequency for 8085? - 3 MHz is the maximum clock frequency for 8085.

18. What is the RST for the TRAP? - RST 4.5 is called as TRAP.

19. In 8085 which is called as High order / Low order Register? - Flag is called as Low order

register & Accumulator is called as High order Register.

20. What are input & output devices? - Keyboards, Floppy disk are the examples of input devices.

Printer, LED / LCD display, CRT Monitor are the examples of output devices.

21. Can an RC circuit be used as clock source for 8085? - Yes, it can be used, if an accurate clock

frequency is not required. Also, the component cost is low compared to LC or Crystal.

22. Why crystal is a preferred clock source? - Because of high stability, large Q (Quality Factor)

& the frequency that doesn‘t drift with aging. Crystal is used as a clock source most of the

times.

23. Which interrupt is not level-sensitive in 8085? - RST 7.5 is a raising edge-triggering interrupt.

24. What does Quality factor mean? - The Quality factor is also defined, as Q. So it is a number,

which reflects the lossness of a circuit. Higher the Q, the lower are the losses.

25. What are level-triggering interrupt? - RST 6.5 & RST 5.5 are level-triggering interrupts.

TWO MARK QUESTIONS - 8085 Microprocessor

1.What is Microprocessor? Give the power supply & clock frequency of

8085?

Ans:A microprocessor is a multipurpose, programmable logic device that reads binary

instructions from a storage device called memory accepts binary data as input and processes

data according to those instructions and provides result as output. The power supply of 8085 is

+5V and clock frequency in 3MHz.

2. List few applications of microprocessor-based system.

Ans: It is used:

i. For measurements, display and control of current, voltage, temperature, pressure, etc.

ii. For traffic control and industrial tool control.

iii. For speed control of machines.

3. What are the functions of an accumulator?

Ans:The accumulator is the register associated with the ALU operations and sometimes

I/O operations. It is an integral part of ALU. It holds one of data to be processed by ALU. It

also temporarily stores the result of the operation performed by the ALU.

4. List the 16 – bit registers of 8085 microprocessor.

Ans:Stack pointer (SP) and Program counter (PC).

5. List the allowed register pairs of 8085.

Ans: B-C register pair

D-E register pair

H-L register pair

6. Mention the purpose of SID and SOD lines

Ans:SID (Serial input data line): It is an input line through which the microprocessor accepts

serial data.

SOD (Serial output data line): It is an output line through which the microprocessor

sends output serial data.

7. What is an Opcode?

Ans: The part of the instruction that specifies the operation to be performed is

called the operation code or opcode.

8. What is the function of IO/M signal in the 8085?

Ans: It is a status signal. It is used to differentiate between memory locations

and I/O operations. When this signal is low (IO/M = 0) it denotes the memory

related operations. When this signal is high (IO/M = 1) it denotes an I/O

operation.

9. What is an Operand?

Ans: The data on which the operation is to be performed is called as an Operand.

10. How many operations are there in the instruction set of 8085 microprocessor?

Ans: There are 74 operations in the 8085 microprocessor.

11. List out the five categories of the 8085 instructions. Give examples of

the instructions for each group.

Ans:

• Data transfer group – MOV, MVI, LXI.

• Arithmetic group – ADD, SUB, INR.

• Logical group –ANA, XRA, CMP.

• Branch group – JMP, JNZ, CALL.

• Stack I/O and Machine control group – PUSH, POP, IN, HLT.

12. Explain the difference between a JMP instruction and CALL instruction.

Ans: A JMP instruction permanently changes the program counter. A CALL

instruction leaves information on the stack so that the original program

execution sequence can be resumed.

13. Explain the purpose of the I/O instructions IN and OUT.

Ans: The IN instruction is used to move data from an I/O port into the accumulator. The OUT

instruction is used to move data from the accumulator to an I/O port. The IN & OUT

instructions are used only on microprocessor, which use a separate address space for

interfacing.

14. What is the difference between the shift and rotate instructions?

Ans: A rotate instruction is a closed loop instruction. That is, the data moved

out at one end is put back in at the other end. The shift instruction loses the data

that is moved out of the last bit locations.

15. How many address lines in a 4096 x 8 EPROM CHIP?

Ans: 12 address lines.

16. What are the Control signals used for DMA operation?

Ans:-HOLD & HLDA.

17. What is meant by Wait State?

Ans:-This state is used by slow peripheral devices. The peripheral devices can transfer the data

to or from the microprocessor by using READY input line. The microprocessor remains in wait

state as long as READY line is low. During the wait state, the contents of the address,

address/data and control buses are held constant.

18. List the four instructions which control the interrupt structure of the 8085 microprocessor.

Ans:-

DI ( Disable Interrupts )

EI ( Enable Interrupts )

RIM ( Read Interrupt Masks )

SIM ( Set Interrupt Masks )

19. What is meant by polling?

Ans:-Polling or device polling is a process which identifies the device that has

interrupted the microprocessor.

20. What is meant by interrupt?

Ans:-Interrupt is an external signal that causes a microprocessor to jump to a

specific subroutine.

21. Explain priority interrupts of 8085.

Ans:-The 8085 microprocessor has five interrupt inputs. They are TRAP, RST 7.5, RST 6.5,

RST 5.5, and INTR. These interrupts have a fixed priority of interrupt service. If two or more

interrupts go high at the same time, the 8085 will service them on priority basis. The TRAP has

the highest priority followed by RST 7.5, RST 6.5, RST 5.5. The priority of interrupts in 8085

is shown in the table.

TRAP 1

RST 7.5 2

RST 6.5 3

RST 5.5 4

INTR 5

22. What is a microcomputer?

Ans:-A computer that is designed using a microprocessor as its CPU is called

Microcomputer

23. What is the signal classification of 8085

Ans:-All the signals of 8085 can be classified into 6 groups

Address bus

Data bus

Control and status signals

Power supply and frequency signals

Externally initiated signals

Serial I/O ports

24. What are operations performed on data in 8085

Ans:- The various operations performed are Store 8-bit data Perform arithmetic and logical

operationsTest for conditions Sequence the execution of instructions Store data temporarily

during execution in the defined R/W memory locations called the stack

25. Steps involved to fetch a byte in 8085

Ans:-

i. The PC places the 16-bit memory address on the address bus

ii. The control unit sends the control signal RD to enable the memory chip

iii. The byte from the memory location is placed on the data bus

iv. The byte is placed in the instruction decoder of the microprocessor and the task is carried

out according to the instruction

26. How many interrupts does 8085 have, mention them

Ans:-The 8085 has 5 interrupt signals; they are INTR, RST7.5, RST6.5, RST5.5

and TRAP

27. Basic concepts in memory interfacing

Ans:-The primary function of memory interfacing is that the microprocessor should be able to

read from and write into a given register of a memory chip. To perform these operations the

microprocessor should Be able to select the chipIdentify the register .Enable the appropriate

buffer

28. Define instruction cycle, machine cycle and T-state

Ans:-Instruction cycle is defined, as the time required completing the execution of an

instruction. Machine cycle is defined as the time required completing one operation of

accessing memory, I/O or acknowledging an external request. Tcycle is defined as one

subdivision of the operation performed in one clock period

29. What is an instruction?

Ans:-An instruction is a binary pattern entered through an input device to

command the microprocessor to perform that specific function

30. What is the use of ALE

Ans:-The ALE is used to latch the lower order address so that it can be available in T2 and T3

and used for identifying the memory address. During T1 the ALE goes high, the latch is

transparent ie, the output changes according to the input data, so the output of the latch is the

lower order address. When ALE goes low the lower order address is latched until the next ALE.

31. How many machine cycles does 8085 have, mention them

Ans:The 8085 have seven machine cycles. They are

Opcode fetch

Memory read

Memory write

I/O read

I/O write

Interrupt acknowledge

Bus idle

32. Explain the signals HOLD, READY and SID

Ans:HOLD indicates that a peripheral such as DMA controller is requesting the use of address

bus, data bus and control bus. READY is used to delay the microprocessor read or write cycles

until a slow responding peripheral is ready to send or accept data.SID is used to accept serial

data bit by bit

33. Mention the categories of instruction and give two examples for each category.

Ans:The instructions of 8085 can be categorized into the following five

categories

Data transfer Instructions -MOV Rd,Rs STA 16-bit

Arithmetic Instructions -ADD R DCR M

Logical Instructions -XRI 8-bit RAR

Branching Instructions -JNZ CALL 16-bit

Machine control Instructions -HLT NOP

34. Explain LDA, STA and DAA instructions

Ans:LDA copies the data byte into accumulator from the memory location specified by the 16-

bit address. STA copies the data byte from the accumulator in the memory location specified by

16-bit address. DAA changes the contents of the accumulator from binary to 4-bit BCD digits.

35. Explain the different instruction formats with examples

Ans:The instruction set is grouped into the following formats

One byte instruction -MOV C,A

Two byte instruction -MVI A,39H

Three byte instruction -JMP 2345H

36. What is the use of addressing modes, mention the different types

Ans:The various formats of specifying the operands are called addressing modes, it is used to

access the operands or data. The different types are as follows

Immediate addressing

Register addressing

Direct addressing

Indirect addressing

Implicit addressing

37. What is the use of bi-directional buffers?

Ans:It is used to increase the driving capacity of the data bus. The data bus of a

microcomputer system is bi-directional, so it requires a buffer that allows the data to flow in

both directions.

38. Give the register organization of 8085

Ans:

W(8) Temp. Reg

Z(8) Temp. Reg

B(8) Register

C(8) Register

D(8) Register

E(8) Register

H(8) Register

L(8) Register

Stack Pointer (16)

Program Counter (16)

39. Define stack and explain stack related instructions

Ans:The stack is a group of memory locations in the R/W memory that is used for the

temporary storage of binary information during the execution of the program. The stack related

instructions are PUSH & POP

40. Why do we use XRA A instruction

Ans:The XRA A instruction is used to clear the contents of the Accumulator and store the value

00H.

41. Compare CALL and PUSH instructions

Ans:

CALL PUSH

1.When CALL is executed the microprocessor automatically stores the 16-bit address of the

instruction next to CALL on the stack.

2.When CALL is executed the stack pointer is decremented by two

1.PUSH The programmer uses the instruction to save the contents of the register pair on the

stack

2. When PUSH is executed the stack pointer is decremented by two

42. What is Microcontroller and Microcomputer

Ans:Microcontroller is a device that includes microprocessor; memory and I/O

signal lines on a single chip, fabricated using VLSI technology. Microcomputer

is a computer that is designed using microprocessor as its CPU. It includes

microprocessor, memory and I/O.

43. Define Flags

Ans:The flags are used to reflect the data conditions in the accumulator. The 8085 flags are S-

Sign flag, Z-Zero flag, AC-Auxiliary carry flag, P-Parity flag, CYCarry flag, D7 D6 D5 D4 D3

D2 D1 D0

44. How does the microprocessor differentiate between data and instruction?

Ans:When the first m/c code of an instruction is fetched and decoded in the instruction register,

the microprocessor recognizes the number of bytes required to fetch the entire instruction. For

example MVI A, Data, the second byte is always considered as data. If the data byte is omitted

by mistake whatever is in that memory location will be considered as data & the byte after the

―data‖ will be treated as the next instruction.

45. Compare RET and POP

Ans:

RET POP

1.RET transfers the contents of the top two locations of the stack to the PC

2.When RET is executed the SP is incremented by two

3.Has 8 conditional RETURN instructions

1.POP transfers the contents of the top two locations of the stack to the specified register pair

2. When POP is executed the SP is incremented by two

3.No conditional POP instructions

46.What is interrupt service routine?

Ans:Interrupt means to break the sequence of operation. While the CPU is executing a

program an interrupt breaks the normal sequence of execution of instructions & diverts its

execution to some other program. This program to which the control is transferred is called the

interrupt service routine.

SIXTEEN MARK QUESTIONS:

1. Draw the functional block diagram of 8085, and explain in brief. (16)

2. What are the different addressing modes used in 8085. Explain with an example. (16)

3. Discuss the interrupt system in 8085. (16)

4. What are the memories mapped I/O, I/O mapped & I/O explain. (16)

5. Draw the timing diagram for IN & OUT instructions of 8085. (16)

7. a. Draw the block diagram of 8085 mp and explain? (12)

b. Write an assembly language program to add two 2-digits BCD Number? (4)

8. a. Explain the instruction set of 8085? (10)

b. Write notes on status flag? (6)

9. a. Explain the architecture of Intel 8085 with the help of a block diagram? (12)

b. Explain the similarities diff b/w subtract and compare instructions in 8085? (4) 10

10. a. Describe the sequence of event that may occur during the different T state in the opcode

Fetch machine cycle of 8085? (8)

b. Write an assembly language program to convert on array of ASCII code to corresponding

Binary (hex) value. The ASCII array is stored starting from 4200H.The first element of the

number of elements in the array. (8)

11. a. With neat block diagram explain the architecture of 8085? (10)

b. List out the maskable and non maskable interrupts available in 8085? (6)

12. a. How do the instructions of 8085 is classified based on their function and word length? Give

an example? (8)

b. Write an ALP to Add two 8bit numbers? (8)

13.(a)Specify the contents of the registers and the flag status as the following instructions are

executed.(8)

i. MVI A, 00H

ii. MVI B, F8H

iii. MOV C, A

iv. MOV D, B

v. HLT

(b)Write instructions to load the hexadecimal number 65H in register C and 92H in

accumulator A. Display the number 65H at PORT0 and 92H at PORT1.(8)

14. (a)Why the lower order address bus is multiplexed with data bus? How they will be de-

multiplexed? (8)

(b) Differentiate between maskable and non-maskable interrupts.(8)

15. a)Write an 8085 assembly language program using minimum number of instructions to

add the 16 bit no. in BC, DE & HL. Store the 16 bit result in DE pair. (8)

b) Explain the similarities diff b/w subtract and compare instructions in 8085? (8)

16. (a)Explain in detail the following instructions:- (i) ADC (ii) LHLD (iii) RLC (iv) DI

(b) Define & explain the term addressing modes.

UNIT II

SERIAL COMMUNICATION INTERFACE (8251):

UART Functionality

The UART is a universal asynchronous receiver/transmitter, which is modeled on the real-

world. Intel® 8251 peripheral interface adapter component. In the model we are considering,

the UART consists of three main blocks.

• a serial transmit block

• a serial receive block and

• a CPU Interface (I/F) block.

The serial transmit block has two buffers (FIFO) into which data is written by the CPU

I/F block. After the data is written into the buffers it is transmitted serially onto TXD. As long

as the FIFO is not full the serial transmit block sets the signal TX_RDY high.

The serial receive block has four buffers (FIFO). The block checks for the parity and the

validity of the data frame on the RXD input and then writes correct data into its buffers. It also

sets the signal RX_RDY low if its FIFO is empty.

The CPU I/F block is responsible for reading the status register, data register and

writing data into interrupt enable register and data register. It receives control signals from the

CPU for

performing certain tasks. The different functions for the set of control signals is given in a

tabular form below.

D_XS R/W CPU I/F Function

0 R Read status register

0 W Write interrupt enable

register

1 R Receive data from

receive block into data

register.

1 W Write data register &

transmit data into

transmit FIFO.

The XINT is asserted when there is an interrupt factor, i.e. atleast one of status register

bits is asserted, and is also not masked by a corresponding bit in the interrupt enable register.

Bits 0, 1, 2 of the interrupt enable register mask the bits 0, 1,2 of the status register. The block

diagram for the UART with its I/O ports and three main blocks is given below in Figure1

The timing chart for the reading and writing operations, and the serial data format, are

given below in Figure 2 (2.1 through 2.3).

2. System partitioning and Component Description

The UART can be divided into several sub-components, according to different

functionality. The description of each of these components is given next section. The block

diagram depicting the more detailed component partitioning is shown in Figures 3 and 4.

The block diagram shows the different components. The D_XS, XCS, DATA, XWR,

XRD inputs are synchronized with the clock by their respective synchronizing blocks each of

which register the signals twice.

The CPU I/F registers the status register, interrupt enable register, and data register are

modeled separately. Each of these components have DXS1, X_WR/X_RD as control signals.

The transmit and receive FIFO‘s are separated from their corresponding control blocks the

transmit and receive blocks. The RXD is passed through an IFF and the TXD goes through an

OFF before being output. The data goes through an OFF before being written onto DATA

output.

2.1. The Components

DATASynch: This component registers the DATA signal twice so as to synchronize it with the

system clock CLK16M. The synchronized signal is data_bus1.

DXSSynch: This component registers the D_XS signal twice so as to synchronize it with the

system clock CLK16M. The synchronized output is DXS1.

XCSSynch: This component registers the XCS signal twice so as to synchronize it with the

system clock CLK16M. The synchronized output is XCS1.

XWRSynch: This component registers the XWR signal twice so as to synchronize it with the

system clock CLK16M. The synchronized output is X_WR.

XRDSynch: This component registers the XRD signal twice so as to synchronize it with the

system clock CLK16M. The synchronized output is X_RD.

RXDIFF: The RXD input is synchronized with the clock before being read by the receive

block.

The synchronized output is r_xd.

DATAOFF: The data from the data register/status register is registered once before being

written onto DATA output.

Data Tristate Buffer: This component drives the data bus output. It sets it to data_bus2 when

the XRD is asserted and to high impedance otherwise.

XINTOFF: The interrupt factor signal xintd is registered once before being output as XINT.

TXDOFF: The transmit data signal from the serial transmit block txd is synchronized with the

clock before being output onto TXD output.

Status Register: This component represents the status of the UART. The register has TX_RDY,

RX_RDY, PERR as its contents corresponding to bits 0, 1, 2 respectively. Its data is used to

generate the interrupt factor xintd.

Interrupt Enable Register: The contents of this register are used to mask the interrupts the CPU

does not want to process. Data on the data_bus1 bus (bits 2 downto 0) is written into this

register

when both DXS1 and X_WR are low. The XINT generator uses this register contents to mask

the unwanted interrupts.

XINT Generator: This component generates the interrupt from the status register data and the

interrupt enable register data. The equation for the interrupt signal xintd generation is as given

below.

Transmit FIFO: The FIFO is 8-bit by 2-word. It receives control signals from the serial transmit

block. The data on signal data_bus1 is written into its buffer when WRP is asserted. At the

same

time the write pointer is incremented. The data is read onto the stb_fifo_data signal when the

stb_fifo_read is asserted. The stb_fifo_read_inc asserted at the same time as stb_fifo_read,

increments the read pointer by one. The read pointer is reset when the read pointer has reached

its maximum. The write pointer is cleared when the write pointer has reached its maximum.

The

TX_RDY is set low when the FIFO is full.

Receive FIFO: The FIFO is 8-bit by 4-word. It receives control signals from the serial receive

block. The data received from the receive block, rec_data is written into its buffer when

srb_fifo_write is asserted. The srb_fifo_write_inc asserted at the same time as srb_fifo_write,

increments the write pointer by one.

The data is read onto the data_bus2 signal when the XRD is asserted. The srb_fifo_read_inc

asserted at the same time as srb_fifo_read increments the read pointer by one. The read pointer

is

reset when the read pointer has reached its maximum value. The write pointer is cleared when

the write pointer reaches its maximum limit before further increment. The RX_RDY is asserted

low when the FIFO is empty.

Serial Transmit Block: This component is responsible for serial transmission of data onto TXD.

It generates the requisite control signals for reading and writing the transmit FIFO. This

component can be divided into sub-components to make modeling easier. The block diagram

for

this is given below in Figure 3.

All the sub-components have XCS1 as chip enable and XRST as reset signals. The transmit

clock counter counts the CLK16M clock cycles and sets the stb_clk16 high after every 16 clock

cycles. This signal is used as a enable by the transmit data counter, and the transmit block. The

transmit data counter keeps count of the number of data bits transmitted onto tx_d. The data

count is incremented when stb_dci is asserted and cleared when stb_dcc is asserted. These

signals are provided by the transmit control block. The parity counter counts the number of bits

that were high in the eight bits of data being transmitted. The parity count is incremented on

assertion of stb_pci and cleared on assertion of stb_pcc. These two signals are provided by the

transmit block.

The transmit control block controls the whole process of transmission. It is modeled in

the form of a state machine. The state machine has three states namely: IDLE, FIFO_READ,

DATA_TRANSMIT. Initially the machine is in the IDLE state. When DXS1 is high and XWR

is

low it jumps to FIFO_READ state. In the FIFO_READ state the data in the FIFO is read onto

its

output stb_fifo_data by setting stb_fifo_read and stb_fifo_read_inc high. It then jumps to

DATA_TRANSMIT state. In DATA_TRANSMIT state the transmit and the stb_dci signals are

asserted. The machine waits in this state until the signal transmitted is asserted by the transmit

block and upon which it asserts stb_dcc and goes back to IDLE state. When XRST is asserted it

resets all its output signals.

The transmit block has stb_clk_16 as clock and XRST as asynchronous reset. It is

enabled when transmit signal is asserted. It then transmits data serially onto the tx_d depending

upon the value of the stb_data _count. It sends the start bit when the count is less than 1. It then

transmits the data bit by bit on every stb_clk16 high until the count reaches 9. After this it sends

the parity bit corresponding to the parity count stb_par_count. When the count becomes greater

than 10 it transmits stop bit and asserts transmitted signal.

Serial Receive Block: This component is responsible for serial receiving of data on RXD. It

generates the requisite control signals for reading and writing the receive FIFO. This

component

can be further divided into sub-components to make modeling easier. The block diagram for

this

is given below in Figure 4.

All the sub-components have XCS1 as chip enable and XRST as reset signals. The receive

clock

counter counts the CLK16M clock cycles. It at first counts upto 8 clock cycles when the start

bit

is received. It then starts counting and sets the srb_clk16 high after every 16 clock cycles. This

signal is used as a clock by the transmit data counter, transmit parity counter, and the transmit

block. The transmit data counter keeps count of the number of data bits received from rx_d.

The

data count is incremented when srb_dci is asserted and cleared when srb_dcc is asserted. These

signals are provided by the receive control block. The parity counter counts the number of bits

that were high in the eight bits of data being recieved. The parity count is incremented on

assertion of srb_pci and cleared on assertion of srb_pcc. These two signals are provided by the

receive block.

The receive control block controls the whole receiving process. It is modeled in the form of a

state machine. The state machine has four states namely: IDLE, FIFO_WRITE, FIFO_READ,

DATA_RECEIVE. Initially the machine is in the IDLE state. In this state when the start bit is

received on rx_d it jumps to DATA_RECEIVE state. In the DATA_RECEIVE state, receive

and

the srb_dci signals are asserted. The machine waits in this state until the signal received is

asserted by the receive block. When received is asserted it checks for PERR and x_fre before it

asserts srb_dcc and jumps to FIFO_WRITE state. If PERR is high or x_fre is low it jumps to

IDLE state instead. In the FIFO_WRITE state it asserts the srb_fifo_write and

srb_fifo_write_inc

signals and then jumps to IDLE state so that it remains in the FIFO_WRITE state for only one

clock cycle. This ensures that the data is written in only one of the buffers, as the FIFO read and

write processes are clock sensitive.

The receive block has srb_clk_16 as clock and XRST as asynchronous reset. It is enabled when

receive signal is asserted. It then receives data serially from rx_d depending upon the value of

the srb_data _count. It receives data bit by bit into rec_data on every srb_clk16 high until the

data count reaches 8. After this it receives the parity bit. When the count becomes greater than 8

it checks for the stop bit.

PARALLEL I/O 8255:

The Intel 8255 (or i8255) Programmable Peripheral Interface chip is a peripheral chip originally

developed for the Intel 8085 microprocessor, and as such is a member of a large array of such

chips, known as the MCS-85 Family. This chip was later also used with the Intel 8086 and its

descendants. It was later made (cloned) by many other manufacturers. It is made in DIP 40 and

PLCC 44 pins encapsulated versions.

This chip is used to give the CPU access to programmable parallel I/O, and is similar to other

such chips like the Motorola 6520 PIA (Peripheral Interface Adapter) the MOS Technology

6522 (Versatile Interface Adapter) and the MOS Technology CIA (Complex Interface Adapter)

all developed for the 6502 family. Other such chips are the 2655 Programmable Peripheral

Interface from the Signetics 2650 family of microprocessors, the 6820 PIO (Peripheral

Input/Output) from the Motorola 6800 family, the Western Design Center WDC 65C21, an

enhanced 6520, and many others.

The 8255 is widely used not only in many microcomputer/microcontroller systems especially

Z-80 based, home computers such as SV-328 and all MSX, but also in the system board of the

best known original IBM-PC, PC/XT, PC/jr, etc. and clones.

However, most often the functionality the 8255 offered is now not implemented with the 8255

chip itself anymore, but is embedded in a larger VLSI chip as a sub function. The 8255 chip

itself is still made, and is sometimes used together with a micro controller to expand its I/O

capabilities.

Functional Block of 8255

The 8255 has 24 input/output pins in all. These are divided into three 8-bit ports. Port A and

port B can be used as 8-bit input/output ports. Port C can be used as an 8-bit input/output port

or as two 4-bit input/ouput ports or to produce handshake signals for ports A and B.

The three ports are further grouped as follows:

1) Group A consisting of port A and upper part of port C.

2) Group B consisting of port B and lower part of port C.

Eight data lines (D0 - D7) are available (with an 8-bit data buffer) to read/write data into the

ports or control register under the status of the "RD" (pin 5) and WR" (pin 36), which are active

low signals for read and write operations respectively. The address lines A1 and A0 allow to

successively access any one of the ports or the control register as listed below:

A1 A0 Function

0 0 port A

0 1 port B

1 0 port C

1 1 control register

The control signal "'CS" (pin 6) is used to enable the 8255 chip. It is an active low signal, ie,

when CS = '0, the 8255 is enabled. The RESET input (pin 35) is connected to a system (like

8085, 8086, etc. ) reset line so that when the system is reset, all the ports are initialised as input

lines. This is done to prevent 8255 and/or any peripheral connected to it, from being destroyed

due to mismatch of ports. This is explained as follows. Suppose an input device is connected to

8255 at port A. If from the previous operation, port A is initialised as an output port and if 8255

is not reset before using the current configuration, then there is a possibility of damage of either

the input device connected or 8255 or both since both 8255 and the device connected will be

sending out data.

The control register or the control logic or the command word register is an 8-bit register used

to select the modes of operation and input/output designation of the ports.

Operational Modes of 8255

There are two main operational modes of 8255:

1. Input/output mode 2. Bit set/reset mode

Input/Output Mode

There are three types of the input/output mode. They are as follows:

Mode 0

In this mode, the ports can be used for simple input/output operations without handshaking. If

both port A and B are initialized in mode 0, the two halves of port C can be either used together

as an additional 8-bit port, or they can be used as individual 4-bit ports. Since the two halves of

port C are independent, the may be used such that one-half is initialized as an input port while

the other half is initialized as an output port.

Mode 1

When we wish to use port A or port B for handshake (strobed) input or output operation, we

initialise that port in mode 1 (port A and port B can be initilalised to operate in different

modes,ie, for eg, port A can operate in mode 0 and port B in mode 1). Some of the pins of port

C function as handshake lines.

For port B in this mode (irrespective of whether is acting as an input port or output port), PC0,

PC1 and PC2 pins function as handshake lines.

If port A is initialised as mode 1 input port, then, PC3, PC4 and PC5 function as handshake

signals. Pins PC6 and PC7 are available for use as input/output lines.

If port A is initialised as mode 1 output port, then pins PC3, PC6 and PC7 function as

handshake signals. PC4 and PC5 are available as input/output lines.

Mode 2

Only group A can be initialised in this mode. Port A can be used for bidirectional handshake

data transfer. This means that data can be input or output on the same eight lines (PA0 - PA7).

Pins PC3 - PC7 are used as hanshake lines for port A. The remaining pins of port C (PC0 -

PC2) can be used as input/output lines if group B is initialised in mode 0. In this mode, the

8255 may be used to extend the system bus to a slave microprocessor or to transfer data bytes

to and from a floppy disk controller.

Bit Set/Reset (BSR) mode

In this mode only port C can be used (as an output port). Each line of port C (PC0 - PC7) can be

set/reset by suitably loading the command word register.no effect occurs in input-output mode.

Control Word Format

Input/output mode format

Control Word format in input/output mode

The figure shows the control word format in the input/output mode. This mode is selected by

making D7 = '1' .

D0, D1, D3, D4 are for lower port C, port B, upper port C and port A respectively. When D0

or D1 or D3 or D4 are "SET", the corresponding ports act as input ports. For eg, if D0 = D4 =

'1', then lower port C and port A act as input ports. If these bits are "RESET", then the

corresponding ports act as output ports. For eg, if D1 = D3 = '0', then port B and upper port C

act as output ports.

D2 is used for mode selection for group B (Port B and Lower Port C). When D2 = '0', mode 0

is selected and when D2 = '1', mode 1 is selected.

D5, D6 are used for mode selection for group A (Upper Port C and Port A). The format is as

follows:

D6 D5 mode

0 0 0

0 1 1

1 x 2

Example: If port B and upper port C have to be initialised as input ports and lower port C and

port A as ouput ports (all in mode 0), what is the control word?

o 1. Since it is an input/ouput mode, D7 = '1'.

o 2. Mode selection bits, D2, D5, D6 are all '0' for mode 0 operation.

o 3. Port B should operate as input port, hence, D1 = '1'.

o 4. Upper port C should also be an input port, hence, D3 = '1'.

o 5. Port A has to operate output port, hence, D4 = '0'.

o 6. Lower port C should also operate as output port, hence, D0 = '0'.

Applying the corresponding values to the format in input/output mode, we get the control word

as "8A (hex)"

BSR mode format

Control Word format in BSR mode

The figure shows the control word format in BSR mode. This mode is selected by making

D7='0'.

D0 is used for bit set/reset. When D0= '1', the port C bit selected (selection of a port C bit is

shown in the next point) is SET, when D0 = '0', the port C bit is RESET.

D1, D2, D3 are used to select a particular port C bit whose value may be altered using D0 bit

as mentioned above. The selection of the port C bits are done as follows:

D3 D2 D1 bit/pin of port C selected

0 0 0 PC0

0 0 1 PC1

0 1 0 PC2

0 1 1 PC3

1 0 0 PC4

1 0 1 PC5

1 1 0 PC6

1 1 1 PC7

D4, D5, D6 are not used.

Example: If the 5th bit (PC5) of port C has to be "SET", then what is the control word?

o 1. Since it is BSR mode, D7 = '0'.

o 2. Since D4, D5, D6 are not used, assume them to be '0'.

o 3. PC5 has to be selected, hence, D3 = '1', D2 = '0', D1 = '1'.

o 4. PC5 has to be set, hence, D0 = '1'.

Applying the above values to the format for BSR mode, we get the control word as "0B (hex)".

KEYBOARD/DISPLAY CONTROLLER - INTEL 8279

The INTEL 8279 is specially developed for interfacing keyboard and display devices to

8085/8086/8088 microprocessor based system. The important features of 8279 are,

o Simultaneous keyboard and display operations.

o Scanned keyboard mode.

o Scanned sensor mode.

o 8-character keyboard FIFO.

o 1 6-character display.

o Right or left entry 1 6-byte display RAM.

o Programmable scan timing.

Block diagram of 8279:

The functional block diagram of 8279 is shown.

Keyboard section:

The keyboard section consists of eight return lines RL0 - RL7 that can be used to form the

columns of a keyboard matrix.

It has two additional input : shift and control/strobe. The keys are automatically debounced.

The two operating modes of keyboard section are 2-key lockout and N-key rollover.

In the 2-key lockout mode, if two keys are pressed simultaneously, only the first key is

recognized.

In the N-key rollover mode simultaneous keys are recognized and their codes are stored in

FIFO.

The keyboard section also have an 8 x 8 FIFO (First In First Out) RAM.

The FIFO can store eight key codes in the scan keyboard mode. The status of the shift key and

control key are also stored along with key code. The 8279 generate an interrupt signal when

there is an entry in FIFO. The format of key code entry in FIFO for scan keyboard mode is,

In sensor matrix mode the condition (i.e., open/close status) of 64 switches is stored in FIFO

RAM. If the condition of any of the switches changes then the 8279 asserts IRQ as high to

interrupt the processor.

Display section:

The display section has eight output lines divided into two groups A0-A3 and B0-B3.

The output lines can be used either as a single group of eight lines or as two groups of four

lines, in conjunction with the scan lines for a multiplexed display.

The output lines are connected to the anodes through driver transistor in case of common

cathode 7-segment LEDs.

The cathodes are connected to scan lines through driver transistors.

The display can be blanked by BD (low) line.

The display section consists of 16 x 8 display RAM. The CPU can read from or write into any

location of the display RAM.

Scan section:

The scan section has a scan counter and four scan lines, SL0 to SL3.

In decoded scan mode, the output of scan lines will be similar to a 2-to-4 decoder.

In encoded scan mode, the output of scan lines will be binary count, and so an external

decoder should be used to convert the binary count to decoded output.

The scan lines are common for keyboard and display.

The scan lines are used to form the rows of a matrix keyboard and also connected to digit

drivers of a multiplexed display, to turn ON/OFF.

CPU interface section:

The CPU interface section takes care of data transfer between 8279 and the processor.

This section has eight bidirectional data lines DB0 to DB7 for data transfer between 8279 and

CPU.

It requires two internal address A =0 for selecting data buffer and A = 1 for selecting control

register of8279.

The control signals WR (low), RD (low), CS (low) and A0 are used for read/write to 8279.

It has an interrupt request line IRQ, for interrupt driven data transfer with processor.

The 8279 require an internal clock frequency of 100 kHz. This can be obtained by dividing

the input clock by an internal prescaler.

The RESET signal sets the 8279 in 16-character display with two -key lockout keyboard

modes.

Programming the 8279:

The 8279 can be programmed to perform various functions through eight command words.

DIGITAL TO ANALOG CONVERTOR:

To convert the digital signal to analog signal a Digital-to-Analog Converter (DAC) has to be

employed.The DAC will accept a digital (binary) input and convert to analog voltage or

current. Every DAC will have "n" input lines and an analog output. The DAC require a

reference analog voltage (Vref) or current (Iref) source. The smallest possible analog value that

can be represented by the n-bit binary code is called resolution. The resolution of DAC with n-

bit binary input is 1/2nof reference analog value. Every analog output will be a multiple of the

resolution. For example, consider an 8-bit DAC with reference analog voltage of 5 volts. The

analog values for all possible digital input are as shown.

PIN DIGRAM & BLOCK DIAGRAM OF DAC0800

The DAC0800 is an 8-bit, high speed, current output DAC with a typical settling time

(conversion time) of 100 ns. It produces complementary current output, which can be converted

to voltage by using simple resistor load.The DAC0800 require a positive and a negative supply

voltage in the range of ± 5V to ±18V. It can be directly interfaced with TTL, CMOS, PMOS

and other logic families.For TTL input, the threshold pin should be tied to ground (VLC = 0V).

The reference voltage and the digital input will decide the analog output current, which can be

converted to a voltage by simply connecting a resistor to output terminal or by using an op-amp

I to V converter.The DAC0800 is available as a 16-pin IC in DIP.

The pin configuration of DAC0800 is

The internal block diagram of DACO800 is,

ANALOG TO DIGITAL CONVERTOR

The ADC0809 is an 8-bit successive approximation type ADC with inbuilt 8-channel

multiplexer.The ADC0809 is suitable for interface with 8086 microprocessor. The ADC0809 is

available as a 28 pin IC in DIP (Dual Inline Package). The ADC0809 has a total unadjusted

error of ±1 LSD (Least Significant Digit). The ADC0808 is also same as ADC0809 except the

error. The total unadjusted error in ADC0808 is ± 1/2 LSD. The pin configuration of

ADC0809/ADC0808 is

PIN DESCRIPTION OF ADC0809

The internal block diagram of ADC0809/ADC0808 is

The various functional blocks of ADC are 8-channel multiplexer, comparator, 256R resistor

ladder, switch tree, successive approximation register, output buffer, address latch and decoder.

The 8-channel multiplexer can accept eight analog inputs in the range of 0 to 5V and allow

one by one for conversion depending on the 3-bit address input. The channel selection logic is,

The successive approximation register (SAR) performs eight iterations to determine the digital

code for input value. The SAR is reset on the positive edge of START pulse and start the

conversion process on the falling edge of START pulse.

A conversion process will be interrupted on receipt of new START pulse. The End-Of-

Conversion (EOC) will go low between 0 and 8 clock pulses after the positive edge of START

pulse. The ADC can be used in continuous conversion mode by tying the EOC output to

START input. In this mode an external START pulse should be applied whenever power is

switched ON.

The 256'R resistor network and the switch tree is shown in fig.

The 256R ladder network has been provided instead of conventional R/2R ladder because of

its inherent monotonic, which guarantees no missing digital codes. Also the 256R resistor

network does not cause load variations on the reference voltage.The comparator in

ADC0809/ADC0808 is a chopper- stabilized comparator. It converts the DC input signal into

an AC signal, and amplifies the AC sign using high gain AC amplifier. Then it converts AC

signal to DC signal. This technique limits the drift component of the amplifier, because the drift

is a DC component and it is not amplified/passed by the AC amp1ifier. This makes the ADC

extremely insensitive to temperature, long term drift and input offset errors.In ADC conversion

process the input analog value is quantized and each quantized analog value will have a

unique binary equivalent.

The quantization step in ADC0809/ADC0808 is given by,

Inter Integrated Circuits interfacing (I2C Standard)

I²C (Inter-Integrated Circuit) is a multi-master serial computer bus invented by Philips that is

used to attach low-speed peripherals to a motherboard, embedded system, or cellphone. SM

Bus is a subset of I²C that defines stricter electrical and protocol conventions. One purpose of

SM Bus is to promote robustness and interoperability. Accordingly, modern I²C systems

incorporate policies and rules from SM Bus, and the line between these two standards is often

blurred in practice.

Design

A sample schematic with one master (a microcontroller) and three slave nodes (an ADC, a

DAC, and another microcontroller) with pull up resistors Rp

I²C uses only two bidirectional open-drain lines, Serial Data (SDA) and Serial Clock (SCL),

pulled up with resistors. Typical voltages used are +5 V or +3.3 V although systems with other,

higher or lower, voltages are permitted.

The I²C reference design has a 7-bit address space with 16 reserved addresses, so a maximum

of 112 nodes can communicate on the same bus. The most common I²C bus modes are the 100

kbit/s standard mode and the 10 kbit/s low-speed mode, but clock frequencies down to DC are

also allowed. Recent revisions of I²C can host more nodes and run faster (400 kbit/s Fast mode,

1 Mbit/s Fast mode plus or Fm+, and 3.4 Mbit/s High Speed mode), and also support other

extended features, such as 10-bit addressing.

The maximum number of nodes is obviously limited by the address space, and also by the total

bus capacitance of 400 pF, because it restricts practical communication distances to a few

meters.

Reference design

The reference design, as mentioned above, is a bus with a clock (SCL) and data (SDA) lines

with 7-bit addressing. The bus has two roles for nodes: master and slave:

Master node — node that issues the clock and addresses slaves

Slave node — node that receives the clock line and address.

The bus is a multi-master bus which means any number of master nodes can be present.

Additionally, master and slave roles may be changed between messages (after a STOP is sent).

There are four potential modes of operation for a given bus device, although most devices only

use a single role and its two modes:

master transmit — master node is sending data to a slave

master receive — master node is receiving data from a slave

slave transmit — slave node is sending data to a master

slave receive — slave node is receiving data from the master

The master is initially in master transmit mode by sending a start bit followed by the 7-bit

address of the slave it wishes to communicate with, which is finally followed by a single bit

representing whether it wishes to write(0) to or read(1) from the slave.

If the slave exists on the bus then it will respond with an ACK bit (acknowledge) for that

address. The master then continues in either transmit or receive mode (according to the

read/write bit it sent), and the slave continues in its complementary mode (receive or transmit,

respectively).

The address and the data bytes are sent most significant bit first. The start bit is indicated by a

high->low transition of SDA with SCL high; the stop bit is indicated by a low->high transition

of SDA with SCL high.

If the master wishes to write to the slave then it repeatedly sends a byte with the slave sending

an ACK bit. (In this situation, the master is in master transmit mode and the slave is in slave

receive mode.)

If the master wishes to read from the slave then it repeatedly receives a byte from the slave, the

master sending an ACK bit after every byte but the last one. (In this situation, the master is in

master receive mode and the slave is in slave transmit mode.)

The master then ends transmission with a stop bit, or it may send another START bit if it

wishes to retain control of the bus for another transfer (a "combined message").

Message Protocols

I²C defines three basic types of message, each of which begins with a START and ends with a

STOP:

Single message where a master writes data to a slave;

Single message where a master reads data from a slave;

"Combined" messages, where a master issues at least two reads and/or writes to one or more

slaves.

In a combined message, each read or write begins with a START and the slave address. After

the first START, these are also called "repeated START" bits; repeated START bits are not

preceded by STOP bits, which is how slaves know the next transfer is part of the same message.

Any given slave will only respond to particular messages, as defined by its product

documentation.

Pure I²C systems support arbitrary message structures. SMBus is restricted to nine of those

structures, such as "read word N" and "write word N", involving a single slave.

With only a few exceptions, neither I²C nor SMBus define message semantics, such as the

meaning of data bytes in messages. Message semantics are otherwise product-specific. Those

exceptions include messages addressed to the I²C "general call" address (0x00) or to the SMBus

"Alert Response Address"; and messages involved in the SMBus "Address Resolution

Protocol" (ARP) for dynamic address allocation and management.

In practice most slaves adopt request/response control models, where one or more bytes

following a write command are treated as a command or address. Those bytes determine how

subsequent written bytes are treated and/or how the slave responds on subsequent reads. Most

SMBus operations involve single byte commands.

Messaging Example: 24c32 EEPROM

One specific example is the 24c32 type EEPROM, which uses two request bytes that are called

Address High and Address Low. (Accordingly, these EEPROMs aren't usable by pure SMBus

hosts, which only support single byte commands.) These bytes are used to address bytes within

the 32 kbit (4 kB) supported by that EEPROM; the same two byte addressing is also used by

larger EEPROMs, such as 24c512 ones storing 512 kbits (64 kB).

To write to the EEPROM, a single message is used. After the START, the master sends the

chip's bus address with the direction bit clear ("write"), then sends the two byte address of data

within the EEPROM and then sends data bytes to be written starting at that address, followed

by a STOP. When writing multiple bytes, all the bytes must be in the same 32 byte page. While

it's busy saving those bytes to memory, the EEPROM won't respond to further I2C requests.

(That's another incompatibility with SMBus: SMBus devices must always respond to their bus

addresses.)

To read starting at a particular address in the EEPROM, a combined message is used. After a

START, the master first writes that chip's bus address with the direction bit clear ("write") and

then the two bytes of EEPROM data address. It then sends a (repeated) START and the

EEPROM's bus address with the direction bit set ("read"). The EEPROM will then respond

with the data bytes beginning at the specified EEPROM data address -- a combined message,

first a write then a read. The master issues a STOP after the first data byte it NAKs rather than

ACks (when it's read all it wants). The EEPROM increments the address after each data byte

transferred; multi-byte reads can retrieve the entire contents of the EEPROM using one

combined message.

Applications

I²C is appropriate for peripherals where simplicity and low manufacturing cost are more

important than speed. Common applications of the I²C bus are:

Reading configuration data from SPD EEPROMs on SDRAM, DDR SDRAM, DDR2

SDRAM memory sticks (DIMM) and other stacked PC boards

Supporting systems management for PCI cards, through an SMBus 2.0 connection.

Accessing NVRAM chips that keep user settings.

Accessing low speed DACs.

Accessing low speed ADCs.

Changing contrast, hue, and color balance settings in monitors (Display Data Channel).

Changing sound volume in intelligent speakers.

Controlling OLED/LCD displays, like in a cellphone.

Reading hardware monitors and diagnostic sensors, like a CPU thermostat and fan speed.

Reading real time clocks.

Turning on and turning off the power supply of system components.

A particular strength of I²C is that a microcontroller can control a network of device chips with

just two general-purpose I/O pins and software.

Peripherals can also be added to or removed from the I²C bus while the system is running,

which makes it ideal for applications that require hot swapping of components.

Buses like I²C became popular when computer engineers realized that much of the

manufacturing cost of an integrated circuit design results from its package size and pin count. A

smaller package also usually weighs less and consumes less power, which is especially

important in cellphones and portable computing.

Limitations

The assignment of slave addresses is one weakness of I²C. Seven bits is too few to prevent

address collisions between the many thousands of available devices, and manufacturers rarely

dedicate enough pins to configure the full slave address used on a given board. While some

devices can set multiple address bits per pin, e.g. by using a spare internal ADC channel to

sense one of eight ranges set by an external voltage divider, usually each pin controls one

address bit. Manufacturers may provide pins to configure a few low order bits of the address

and arbitrarily set the higher order bits to some value based on the model. This limits the

number of devices of that model which may be present on the same bus to some low number,

typically between two and eight. That partially addresses the issue of address collisisons

between different vendors. The addition of ten-bit addresses to I²C hasn't really caught on yet.

Neither has the complex SMBus "ARP" scheme for dynamically assigning addresses (other

than for PCI cards with SMBus presence, for which it is required).

Automatic bus configuration is a related issue. A given address may be used by a number of

different protocol-incompatible devices in various systems, and hardly any device types can be

detected at runtime. For example 0x51 may be used by a 24LC02 or 24C32 EEPROM, with

incompatible addressing; or by a PCF8563 RTC, which can't reliably be distinguished from

either (without changing device state, which might not be allowed). The only reliable

configuration mechanisms available to hosts involve out-of-band mechanisms such as tables

provided by system firmware which list the available devices. Again, this issue can partially be

addressed by ARP in SMBus systems, especially when vendor and product identifiers are used;

but that hasn't really caught on. The rev 03 version of the I²C specification adds a device ID

mechanism, which at this writing has not had time to catch on either.

I²C supports a limited range of speeds. Hosts supporting the multi-megabit speeds are rare.

Support for the Fm+ one-megabit speed is more widespread, since its electronics are simple

variants of what is used at lower speeds. Many devices don't support the 400 kbit/s speed (in

part because SMBus doesn't yet support it). I²C nodes implemented in software (instead of

dedicated hardware) may not even support the 100 kbit/s speed; so the whole range defined in

the specification is rarely usable. All devices must at least partially support the highest speed

used or they may spuriously detect their device address. Devices are allowed to stretch clock

cycles to suit their particular needs, which can starve bandwidth needed by faster devices and

increase latencies when talking to other device addresses. Bus capacitance also places a limit on

the transfer speed, especially when current sources aren't used to increase signal rise times.

Because of those limits (address management, bus configuration, speed), few I²C bus segments

have even a dozen devices. It's common for systems to have several such segments. One might

be dedicated to use with high speed devices, for low latency power management. Another

might be used to control a few devices where latency and throughput aren't important issues;

yet another segment might be used only to read EEPROM chips describing add-on cards (such

as the SPD standard used with DRAM sticks).

IEEE-488

IEEE-488 is a short-range, digital communications bus specification that has been in use for

over 30 years. Originally created for use with automated test equipment, the standard is still in

wide use for that purpose. IEEE-488 is also commonly known as HP-IB (Hewlett-Packard

Instrument Bus) and GPIB (General Purpose Interface Bus).

IEEE-488 allows up to 15 devices to share a single 8-bit parallel electrical bus by daisy

chaining connections. The slowest device participates in control and data transfer handshakes to

determine the speed of the transaction. The maximum data rate is about one Mbyte/s in the

original standard, and about 8 Mbyte/s with later extensions.

The IEEE-488 bus employs 16 signal lines — eight bi-directional used for data transfer, three

for handshake, and five for bus management — plus eight ground return lines.

IEEE-488 / HP-IB / GPIB

IEEE-488 stacking connectors

Type General purpose data bus

Production history

Designer Hewlett-Packard

Designed late 1960s standardized in 1975

Manufacturer Hewlett-Packard

Produced 1960s to present

Specifications

External yes

Data signal Parallel data bus with

handshaking

Width 8 bits

Bandwidth 1 Mbyte/s

(later

extended to

8 Mbyte/s)

Max

devices

15

Protocol Parallel

Cable 20 meters max

Pins 24 (8 data, 5 bus management, 3

handshake, 8 ground)

Connector 24-pin Amphenol-designed

micro ribbon

Pin out

A female IEEE-488 connector

Pin 1 DIO1 Data

input/output

bit.

Pin 2 DIO2 Data

input/output

bit.

Pin 3 DIO3 Data

input/output

bit.

Pin 4 DIO4 Data

input/output

bit.

Pin 5 EOI End-or-

identify.

Pin 6 DAV Data valid.

Pin 7 NRFD Not ready

for data.

Pin 8 NDAC Not data

accepted.

Pin 9 IFC Interface

clear.

Pin 10 SRQ Service

request.

Pin 11 ATN Attention.

Pin 12 SHIELD

Pin 13 DIO5 Data

input/output

bit.

Pin 14 DIO6 Data

input/output

bit.

Pin 15 DIO7 Data

input/output

bit.

Pin 16 DIO8 Data

input/output

bit.

Pin 17 REN Remote

enable.

Pin 18 GND (wire

twisted

with DAV)

Pin 19 GND (wire

twisted

with

NRFD)

Pin 20 GND (wire

twisted

with

NDAC)

Pin 21 GND (wire

twisted

with IFC)

Pin 22 GND (wire

twisted

with SRQ)

Pin 23 GND (wire

twisted

with ATN)

Pin 24 Logic

ground

GPIB Description [IEEE488]

GPIB System

The IEEE-488 interface bus, also known as the General Purpose Interface Bus "GPIB" is an 8

bit wide byte serial, bit parallel interface system which incorporates:

5 control lines

3 handshake lines

8 bi-directional data lines.

The entire bus consists of 24 lines, with the remaining lines occupied by ground wires.

Additional features include: TTL logic levels (negative true logic), the ability to communicate

in a number of different language formats, and no minimum operational transfer limit. The

maximum data transfer rate is determined by a number of factors, but is assumed to be 1Mb/s.

Devices exist on the bus in any one of 3 general forms:

1. Controller

2. Talker

3. Listener

A single device may incorporate all three options, although only one option may be active at a

time. The Controller makes the determination as to which device becomes active on the bus.

The GPIB can handle only 1 ‗active‘ controller on the bus, although it may pass operation to

another controller. Any number of active listeners can exist on the bus with an active talker as

long as no more then 15 devices are connected to the bus.The controller determines which

devices become active by sending interface messages over the bus to a particular instrument.

Each individual device is associated with a 5 bit BCD code which is unique to that device. By

using this code, the controller can coordinate the activities on the bus and the individual devices

can be made to talk, listen (un-talk, un-listen) as determined by the controller. A controller can

only select a particular function of a device, if that function is incorporated within the device;

for example a ‗listen‘ only device can not be made to talk to the controller.The Talker sends

data to other devices.The Listener receives the information from the Talker. In addition to the 3

basic functions of the controller, talker, and listener the system also incorporates a number of

operational features, such as; serial poll, parallel poll, secondary talk and listen addresses,

remote/local capability, and a device clear (trigger).

Device dependent messages are moved over the GPIB in conjunction with the data byte

transfer control lines. These three lines (DAV, NRFD, and NDAC) are used to form a three

wire ‗interlocking‘ handshake which controls the passage of data. The active talker would

control the ‗DAV‘ line (Data Valid) and the listener(s) would control the ‗NRFD‘ (Not Ready

For Data), and the ‗NDAC‘ (Not Data Accepted) line.In the steady state mode the talker will

hold ‗DAV‘ high (no data available) while the listener would hold ‗NRFD‘ high (ready for

data) and ‗NDAC‘ low (no data accepted. After the talker placed data on the bus it would then

take ‗DAV‘ low (data valid). The listener(s) would then send ‗NRFD‘ low and send ‗NDAC‘

high (data accepted). Before the talker lifts thedata off the bus, ‗DAV‘ will be taken high

signifying that data is no longer valid. If the ‗ATN‘ line (attention) is high while this process

occurs the information is considered data ( a device dependent message), but with the "ATN‘

line low the information is regarded as an interface message; such as listen, talk, un-listen or

un-talk. The other five lines on the bus (‗ATN‘ included) are the bus management lines. These

lines enable the controller and other devices on the bus to enable, interrupt, flag, and halt the

operation of the bus. All lines in the GPIB are tri-state except for ‗SQR‘, ‗NRFD‘, and ‗NDAC‘

which are open-collector. The standard bus termination is a 3K resistor connected to 5 volts in

series with a 6.2K resistor to ground - all values having a 5% tolerance. The standard also

allows for identification of the devices on the bus. Each device should have a string of 1 or 2

letters placed some where on the body of the device (near or on the GPIB connector). These

letters signify the capabilities of the device on the GPIB bus.

C Controller

T Talker

L Listener

AH Acceptor Handshake

SH Source Handshake

DC Device Clear

DT Device Trigger

RL Remote Local

PP Parallel Poll

TE Talker Extended

LE Listener Extended

Devices are connected together on the bus in a daisy chained fashion. Normally the GPIB

connector (after being connected to the device with the male side) has an female interface so

that another connector may be attached to it. This allows the devices to be daisy chained.

Devices are connected together in either a Linear or Star fashion. Most devices operate either

via front panel control or HPIB control (REMOTE). While using the front Panel the device is in

the Local state, when receiving commands via the HPIB, the device is in the Remote state. The

device is placed in the Remote state when ever the System Controller is reset or powered on,;

also, when the system controller sends out an Abort message. In addition, if the device is

addressed, it then enters the Remote state.

IEEE488 Data Bus Transfer Timing

GPIB Bus Handshake Timing

The IEEE488 bus operates at the speed of the slowest device, all devices have to be ready

before operation begins. Signals are active low. Data is transferred asynchronous, using the

Handshake lines instead of a clock. Only Parallel Polling does not use the Handshake, all other

transfers use Hand-shaking.

HS488 High-Speed GPIB Handshake Protocol Hand shake protocol [not shown above],

increases bus transfers to 8MBytes/s with other HS488 devices. NDAC is not required to

Handshake, The Talker outputs data with DAV, waits then outputs new data with DAV without

NDAC occurring.

What is RS232?

RS232 is a popular communications protocol for connecting modems and data acquisition

devices to computers. RS232 devices can be plugged straight into the computer's serial port

(also known as the COM or Comms port). Examples of data acquisition devices include GPS

receivers, electronic balances, data loggers, temperature interfaces and other measurement

instruments.

RS232 Software

To obtain data from your RS232 instruments and display it on your PC you need some

software. Version 4.3 of the Windmill RS232 software is now free from their web site. They

also offer free serial trouble-shooting software.

The RS232 Standard

RS stands for recommended standard. In the 60's a standards committee now known as the

Electronic Industries Association developed an interface to connect computer terminals to

modems. Over the years this has been updated: the most commonly used version of the

standard is RS232C (sometimes known as EIA232); the most recent is RS232E. The standard

defines the electrical and mechanical characteristics of the connection - including the function

of the signals and handshake pins, the voltage levels and maximum bit rate.

If RS232 is a standard why can't I just use a standard lead to connect together two RS232 ports

and expect them to talk to one another? That's a good question. The answer is that the RS232

standard was created for just one specific situation and the difficulties come when it is used for

something else. The standard was defined to connect computers to modems. Any other use is

outside of the standard. The authors of the standard had in mind the situation below:

The standard defines how computers ( it calls them Data Terminal Equipment or DTEs)

connect to modems ( it calls them Data Communication Equipment or DCEs). The standard

says that computers should be fitted with a 25 way plug whilst modems should have a 25 way

D socket. The interconnecting lead between a computer and a modem should be simply pin1—

pin1, pin2—pin2, etc. The main signals and their direction of flow are described below. It is

important to note that a signal which is an output from a computer is an input to a modem and

vice versa. This means that you can never tell from the signal name alone whether it is an input

or an output from a particular piece of equipment. Also, instead of being a DCE device, a data

acquisition device might be configured as DTE. In this case you need an adaptor or the RS232

cable wired differently to normal. When the PC is connected to a DTE instrument, some of the

cable wires must cross over.

TXD Transmitted Data, Pin 2 of 25 way D

This is the serial encoded data sent from a computer to a modem to be transmitted over the

telephone line.

RXD Received Data, Pin 3 of 25 way D

This is the serial encoded data received by a computer from a modem which has in turn

received it over the telephone line.

DSR Data Set Ready, Pin 6 of 25 way D

This should be set true by a modem whenever it is powered on. It can be read by the computer

to determine that the modem is on line.

DTR Data Terminal Ready, Pin 20 of 25 way D

This should be set true by a computer whenever it is powered on. It can be read by the modem

to determine that the computer is on line.

RTS Request to Send, Pin 4 of 25 way D

This is set true by a computer when it wishes to transmit data.

CTS Clear To Send, Pin 5 of 25 Way D

This is set true by a modem to allow the computer to transmit data. The standard envisaged that

when a computer wished to transmit data it would set its RTS. The local modem would then

arbitrate with the distant modem for use of the telephone line. If it succeeded it would set CTS

and the computer would transmit data. The distant modem would use its CTS to prevent any

transmission by the distant computer.

DCD Data Carrier Detect, Pin 8 of 25 Way D

This is set true by a modem when it detects the data carrier signal on the telephone line..

PC Serial Ports

A nine pin D plug has become the standard fitting for the serial ports of PCs, although it's

nothing to do with the RS232 standard. The pin connections used are:

Pin Direction Signal

1 Input DCD Data Carrier Detect

2 Input RXD Received Data

3 Output TXD Transmitted Data

4 Output DTR Data Terminal Ready

5 Signal Ground

6 Input DSR Data Set Ready

7 Output RTS Request To Send

8 Input CTS Clear To Send

9 Input RI Ring Indicator

How Fast Can Instruments send data over RS232?

The speed of RS232 communications is expressed in Baud. The unit is named after Jean

Maurice-Emile Baudot (1845-1903), a French telegraph engineer and the inventor of the first

teleprinter. It was proposed at the International Telegraph Conference of 1927. The maximum

speed, according to the standard, is 20000 Baud. However, modern equipment can operate

much faster than this. No matter how fast (or slow) your connection - the maximum number of

readings per second you can take from your instrument depends on the software. For example,

with Windmill software, speeds of up to 35 readings per second are achievable whilst with

Streamer software this rises to 700 readings per second.

The length of the cable also plays a part in maximum speed. The longer the cable, the greater

the cable's capacitance and the slower the speed at which you can obtain accurate results. A

large capacitance means voltage changes on one signal wire may be transmitted to an adjacent

signal wire. Fifty feet is commonly quoted as the maximum distance, but this is not specified in

the standard. We generally recommend a maximum distance of 50 metres, but this depends on

the type of hardware you are connecting and characteristics of the cable.

Introduction to RS485

RS232, RS422, RS423 and RS485 are serial communication methods for computers and

devices. RS232 is without doubt the best known interface, because this serial interface is

implemented on almost all computers available today. But some of the other interfaces are

certainly interesting because they can be used in situations where RS232 is not appropriate. We

will concentrate on the RS485 interface here.

RS232 is an interface to connect one DTE, data terminal equipment to one DCE, data

communication equipment at a maximum speed of 20 kbps with a maximum cable length of 50

feet. This was sufficient in the old days where almost all computer equipment were connected

using modems, but soon after people started to look for interfaces capable of one or more of the

following:

Connect DTE's directly without the need of modems

Connect several DTE's in a network structure

Ability to communicate over longer distances

Ability to communicate at faster communication rates

RS485 is the most versatile communication standard in the standard series defined by the EIA,

as it performs well on all four points. That is why RS485 is currently a widely used

communication interface in data acquisition and control applications where multiple nodes

communicate with each other.

Differential signals with RS485:

Longer distances and higher bit rates

One of the main problems with RS232 is the lack of immunity for noise on the signal lines. The

transmitter and receiver compare the voltages of the data- and handshake lines with one

common zero line. Shifts in the ground level can have disastrous effects. Therefore the trigger

level of the RS232 interface is set relatively high at ±3 Volt. Noise is easily picked up and

limits both the maximum distance and communication speed. With RS485 on the contrary there

is no such thing as a common zero as a signal reference. Several volts difference in the ground

level of the RS485 transmitter and receiver does not cause any problems. The RS485 signals

are floating and each signal is transmitted over a Sig+ line and a Sig- line. The RS485 receiver

compares the voltage difference between both lines, instead of the absolute voltage level on a

signal line. This works well and prevents the existence of ground loops, a common source of

communication problems. The best results are achieved if the Sig+ and Sig- lines are twisted.

The image below explains why.

Noise in straight and twisted pair cables

In the picture above, noise is generated by magnetic fields from the environment. The picture

shows the magnetic field lines and the noise current in the RS485 data lines that is the result of

that magnetic field. In the straight cable, all noise current is flowing in the same direction,

practically generating a looping current just like in an ordinary transformer. When the cable is

twisted, we see that in some parts of the signal lines the direction of the noise current is the

oposite from the current in other parts of the cable. Because of this, the resulting noise current

is many factors lower than with an ordinary straight cable. Shielding—which is a common

method to prevent noise in RS232 lines—tries to keep hostile magnetic fields away from the

signal lines. Twisted pairs in RS485 communication however adds immunity which is a much

better way to fight noise. The magnetic fields are allowed to pass, but do no harm. If high noise

immunity is needed, often a combination of twisting and shielding is used as for example in

STP, shielded twisted pair and FTP, foiled twisted pair networking cables. Differential signals

and twisting allows RS485 to communicate over much longer communication distances than

achievable with RS232. With RS485 communication distances of 1200 m are possible.

Differential signal lines also allow higher bit rates than possible with non-differential

connections. Therefore RS485 can overcome the practical communication speed limit of

RS232. Currently RS485 drivers are produced that can achieve a bit rate of 35 mbps.

Characteristics of RS485 compared to RS232, RS422 and RS423

Characteristics of RS232, RS422, RS423 and RS485

RS232 RS423 RS422 RS485

Differential no no yes yes

Max number of

drivers

Max number of

receivers

1

1

1

10

1

10

32

32

Modes of

operation

half

duplex

full

duplex

half

duplex

half

duplex

half

duplex

Network

topology

point-

to-point multidrop multidrop multipoint

Max distance

(acc. standard) 15 m 1200 m 1200 m 1200 m

Max speed at

12 m

Max speed at

1200 m

20 kbs

(1 kbs)

100 kbs

1 kbs

10 Mbs

100 kbs

35 Mbs

100 kbs

Max slew rate 30 V/μs adjustable n/a n/a

Receiver input

resistance 3..7 kΩ ≧ 4 kΩ ≧ 4 kΩ ≧ 12 kΩ

Driver load

impedance 3..7 kΩ ≧ 450 Ω 100 Ω 54 Ω

Receiver input

sensitivity ±3 V ±200 mV ±200 mV ±200 mV

Receiver input

range ±15 V ±12 V ±10 V –7..12 V

Max driver

output voltage ±25 V ±6 V ±6 V –7..12 V

Min driver

output voltage

(with load) ±5 V ±3.6 V ±2.0 V ±1.5 V

What does all the information in this table tell us? First of all we see that the speed of the

differential interfaces RS422 and RS485 is far superior to the single ended versions RS232 and

RS423. We also see that there is a maximum slew rate defined for both RS232 and RS423. This

has been done to avoid reflections of signals. The maximum slew rate also limits the maximum

communication speed on the line. For both other interfaces—RS422 and RS485—the slew rate

is indefinite. To avoid reflections on longer cables it is necessary to use appropriate termination

resitors.

We also see that the maximum allowed voltage levels for all interfaces are in the same range,

but that the signal level is lower for the faster interfaces. Because of this RS485 and the others

can be used in situations with a severe ground level shift of several volts, where at the same

time high bit rates are possible because the transition between logical 0 and logical 1 is only a

few hundred millivolts.

Interesting is, that RS232 is the only interface capable of full duplex communication. This is,

because on the other interfaces the communication channel is shared by multiple receivers

and—in the case of RS485—by multiple senders. RS232 has a separate communication line for

transmitting and receiving which—with a well written protocol—allows higher effective data

rates at the same bit rate than the other interfaces. The request and acknowledge data needed in

most protocols does not consume bandwidth on the primary data channel of RS232.

Network topology with RS485

Network topology is probably the reason why RS485 is now the favorite of the four mentioned

interfaces in data acquisition and control applications. RS485 is the only of the interfaces

capable of internetworking multiple transmitters and receivers in the same network. When

using the default RS485 receivers with an input resistance of 12 kΩ it is possible to connect 32

devices to the network. Currently available high-resistance RS485 inputs allow this number to

be expanded to 256. RS485 repeaters are also available which make it possible to increase the

number of nodes to several thousands, spanning multiple kilometers. And that with an interface

which does not require intelligent network hardware: the implementation on the software side is

not much more difficult than with RS232. It is the reason why RS485 is so popular with

computers, PLCs, micro controllers and intelligent sensors in scientific and technical

applications.

RS485 network topology

In the picture above, the general network topology of RS485 is shown. N nodes are connected

in a multipoint RS485 network. For higher speeds and longer lines, the termination resistances

are necessary on both ends of the line to eliminate reflections. Use 100 Ω resistors on both

ends. The RS485 network must be designed as one line with multiple drops, not as a star.

Although total cable length maybe shorter in a star configuration, adequate termination is not

possible anymore and signal quality may degrade significantly.

RS485 functionality

And now the most important question, how does RS485 function in practice? Default, all the

senders on the RS485 bus are in tri-state with high impedance. In most higher level protocols,

one of the nodes is defined as a master which sends queries or commands over the RS485 bus.

All other nodes receive these data. Depending of the information in the sent data, zero or more

nodes on the line respond to the master. In this situation, bandwidth can be used for almost

100%. There are other implementations of RS485 networks where every node can start a data

session on its own. This is comparable with the way ethernet networks function. Because there

is a chance of data collosion with this implementation, theory tells us that in this case only 37%

of the bandwidth will be effectively used. With such an implementation of a RS485 network it

is necessary that there is error detection implemented in the higher level protocol to detect the

data corruption and resend the information at a later time.

There is no need for the senders to explicity turn the RS485 driver on or off. RS485 drivers

automatically return to their high impedance tri-state within a few microseconds after the data

has been sent. Therefore it is not needed to have delays between the data packets on the RS485

bus.

RS485 is used as the electrical layer for many well known interface standards, including

Profibus and Modbus. Therefore RS485 will be in use for many years in the future.

Two mark Questions:

1.What are the various programmed data transfer methods?

Ans:i) Synchronous data transfer

ii) Asynchronous data transfer

iii) Interrupt driven data transfer

2. What is synchronous data transfer?

Ans:It is a data method which is used when the I/O device and the microprocessor

match in speed. To transfer a data to or from the device, the user program issues a suitable

instruction addressing the device. The data transfer is completed at the end of the execution of

this instruction.

3. What is asynchronous data transfer?

Ans:It is a data transfer method which is used when the speed of an I/O device

does not match with the speed of the microprocessor. Asynchronous data

transfer is also called as Handshaking.

4. What are the basic modes of operation of 8255?

Ans: There are two basic modes of operation of 8255, They are:

1. I/O mode.

2. BSR mode.

In I/O mode, the 8255 ports work as programmable I/O ports, while In BSR mode only

port C (PC0-PC7) can be used to set or reset its individual port bits. Under the IO mode of

operation, further there are three modes of operation of 8255, So as to support different types of

applications, viz. mode 0, mode 1 and mode 2.

• Mode 0 - Basic I/O mode

• Mode 1 - Strobed I/O mode

• Mode 2 - Strobed bi-directional I/O.

5. Write the features of mode 0 in 8255?

Ans:1. Two 8-bit ports (port A and port B) and two 4-bit ports (port C upper

and lower) are available. The two 4-bit ports can be combined used as a third 8-

bit port.

2. Any port can be used as an input or output port.

3.Output ports are latched. Input ports are not latched.

4. A maximum of four ports are available so that overall 16 I/O configurations

are possible.

6. What are the features used mode 1 in 8255?

Ans:Two groups – group A and group B are available for strobed data transfer.

1. Each group contains one 8-bit data I/O port and one 4-bit control/data port.

2. The 8-bit data port can be either used as input or output port. The inputs and

outputs both are latched.

3. Out of 8-bit port C, PC0-PC2 is used to generate control signals for port B and PC3=PC5 are

used to generate control signals for port A. The lines PC6, PC7 may be used as independent

data lines.

7. What are the signals used in input control signal & output control signal?

Ans: Input control signal

• STB (Strobe input)

• IBF (Input buffer full)

• INTR(Interrupt request)

Output control signal

• OBF (Output buffer full)

• ACK (Acknowledge input)

• INTR(Interrupt request)

8. What are the features used mode 2 in 8255?

Ans:The single 8-bit port in-group A is available.

1. The 8-bit port is bi-directional and additionally a 5-bit control port is available.

2. Three I/O lines are available at port C, viz PC2-PC0.

3. Inputs and outputs are both latched.

4. The 5-bit control port C (PC3=PC7) is used for generating/accepting handshake signals for

the 8-bit data transfer on port A.

9. What are the modes of operations used in 8253?

Ans:Each of the three counters of 8253 can be operated in one of the following

six modes of operation.

1. Mode 0 (Interrupt on terminal count)

2. Mode 1 (Programmable monoshot)

3. Mode 2 (Rate generator)

4. Mode 3 (Square wave generator)

5. Mode 4 (Software triggered strobe)

6. Mode 5 (Hardware triggered strobe)

10.Give the different types of command words used in 8259a?

Ans:The command words of 8259A are classified in two groups

1. Initialization command words (ICWs)

2. Operation command words (OCWs)

11. Give the operating modes of 8259a?

Ans:

(a) Fully Nested Mode

(b) End of Interrupt (EOI)

(c) Automatic Rotation

(d) Automatic EOI Mode

(e) Specific Rotation

(f) Special Mask Mode

(g) Edge and level Triggered Mode

(h) Reading 8259 Status

(i) Poll command

(j) Special Fully Nested Mode

(k) Buffered mode

(l) Cascade mode

12. Define scan counter?

Ans:The scan counter has two modes to scan the key matrix and refresh the display. In the

encoded mode, the counter provides binary count that is to be externally decoded to provide the

scan lines for keyboard and display. In the decoded scan mode, the counter internally decodes

the least significant 2 bits and provides a decoded 1 out of 4 scan on SL0-SL3.The keyboard

and display both are in the same mode at a time.

13. What is the output modes used in 8279?

Ans:8279 provides two output modes for selecting the display options.

1.Display Scan

In this mode, 8279 provides 8 or 16 character-multiplexed displays those can be

organized as dual 4-bit or single 8-bit display units.

2.Display Entry

8279 allows options for data entry on the displays. The display data is entered

for display from the right side or from the left side.

14. What are the modes used in keyboard modes?

Ans:1. Scanned Keyboard mode with 2 Key Lockout.

2. Scanned Keyboard with N-key Rollover.

3. Scanned Keyboard special Error Mode.

4. Sensor Matrix Mode.

15. What are the modes used in display modes?

Ans:1. Left Entry mode

In the left entry mode, the data is entered from the left side of the display unit.

2. Right Entry Mode.

In the right entry mode, the first entry to be displayed is entered on the

rightmost display.

16. What is the use of modem control unit in 8251?

Ans:The modem control unit handles the modem handshake signals to

coordinate the communication between the modem and the USART

17. What is interfacing?

Ans:An interface is a shared boundary between the devices which involves

sharing information. Interfacing is the process of making two different systems

communicate with each other.

18. List the operation modes of 8255

Ans:a) I.O Mode

i. Mode 0-Simple Input/Output.

ii. Mode 1-Strobed Input/Output (Handshake mode)

iii. Mode 2-Strobed bidirectional mode

b) Bit Set/Reset Mode.

19. What is a control word?

Ans:It is a word stored in a register (control register) used to control the

operation of a program digital device.

20. What is the purpose of control word written to control register in 8255?

Ans:The control words written to control register specify an I/O function for

each I.O port. The bit D7 of the control word determines either the I/O function

of the BSR function.

21.What is the size of ports in 8255?

Ans:

• Port-A : 8-bits

• Port-B : 8-bits

• Port-CU : 4-bits

• Port-CL : 4-bits

22. Distinguish between the memories mapped I/O peripheral I/O?

Ans:

Memory Mapped I/O Peripheral MappedI/O

16-bit device address 8-bit device address

Data transfer between

any general-purpose

register and I/O port

Data is transfer only

between

accumulator and I.O por

The memory map (64K)

is shared between I/O device

and system memory.

The I/O map is

independent of the

memory map; 256 input

device and 256 output

device can be connected

More hardware is required to

decode 16- bit address

Less hardware is required

to decode 8-bit address

Arithmetic or logic operation

can be directly performed

with I/O data

Arithmetic or logical

operation cannot be

directly performed with

I/O data

23.What is memory mapping?

Ans: The assignment of memory addresses to various registers in a

memory chip is called as memory mapping.

24. What is I/O mapping?

Ans:The assignment of addresses to various I/O devices in the memory

chip is called as I/O mapping.

25.What is an USART?

Ans:USART stands for universal synchronous/Asynchronous Receiver/Transmitter. It is a

programmable communication interface that can communicate by using either synchronous or

asynchronous serial data.

26.What is the use of 8251 chip?

8251 chip is mainly used as the asynchronous serial interface between the

processor and the external equipment.

27. What is 8279?

Ans:The 8279 is a programmable Keyboard/Display interface.

28. List the major components of the keyboard/Display interface.

a. Keyboard section

b. Scan section

c. Display section

d. CPU interface section

29. What is Key bouncing?

Ans: Mechanical switches are used as keys in most of the keyboards. When a key is pressed the

contact bounce back and forth and settle down only after a small time delay (about 20ms). Even

though a key is actuated once, it will appear to have been actuated several times. This problem

is called Key Bouncing.

16 mark questions:

1.. Sketch and explain the interface of PPI 8255 to the 8085 microprocessor .

2.Interface4 7 segment LEDs to display as a BCD counter.

3.Sketch and explain the interface of 8279 to the 8085 microprocessor Interface 8x8 key pad

4 Draw the block diagram of 8255 and explain its working. What is Control Word? Determine the

control word for the following configuration of 8255:- 4 Port A – Output Mode of port A – Mode 1

Port B – Output Mode of port B – Mode 0 Port C lower (pins PC0 – PC2) – Output

5.Explain major components of 8259 with the aid of suitable diagram. .

6. Explain the command words/control words of 8251in details.16/10/8 marks

UNIT III

8086 ARCHITECTURE

Memory

Program, data and stack memories occupy the same memory space. The total addressable

memory size is 1MB KB. As the most of the processor instructions use 16-bit pointers the

processor can effectively address only 64 KB of memory. To access memory outside of 64 KB

the CPU uses special segment registers to specify where the code, stack and data 64 KB

segments are positioned within 1 MB of memory (see the "Registers" section below).

16-bit pointers and data are stored as:

address: low-order byte

address+1: high-order byte

32-bit addresses are stored in "segment:offset" format as:

address: low-order byte of segment

address+1: high-order byte of segment

address+2: low-order byte of offset

address+3: high-order byte of offset

Physical memory address pointed by segment:offset pair is calculated as:

address = (<segment> * 16) + <offset>

Program memory - program can be located anywhere in memory. Jump and call instructions

can be used for short jumps within currently selected 64 KB code segment, as well as for far

jumps anywhere within 1 MB of memory. All conditional jump instructions can be used to

jump within approximately +127 - -127 bytes from current instruction.

Data memory - the processor can access data in any one out of 4 available segments, which

limits the size of accessible memory to 256 KB (if all four segments point to different 64 KB

blocks). Accessing data from the Data, Code, Stack or Extra segments can be usually done by

prefixing instructions with the DS:, CS:, SS: or ES: (some registers and instructions by default

may use the ES or SS segments instead of DS segment).

Word data can be located at odd or even byte boundaries. The processor uses two memory

accesses to read 16-bit word located at odd byte boundaries. Reading word data from even byte

boundaries requires only one memory access.

Stack memory can be placed anywhere in memory. The stack can be located at odd memory

addresses, but it is not recommended for performance reasons (see "Data Memory" above).

Reserved locations:

0000h - 03FFh are reserved for interrupt vectors. Each interrupt vector is a 32-bit pointer in

format segment:offset.

FFFF0h - FFFFFh - after RESET the processor always starts program execution at the

FFFF0h address.

Interrupts

The processor has the following interrupts:

INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using STI/CLI

instructions or using more complicated method of updating the FLAGS register with the help of

the POPF instruction. When an interrupt occurs, the processor stores FLAGS register into stack,

disables further interrupts, fetches from the bus one byte representing interrupt type, and jumps

to interrupt processing routine address of which is stored in location 4 * <interrupt type>.

Interrupt processing routine should return with the IRET instruction.

NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR interrupt.

Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is stored in

location 0008h. This interrupt has higher priority then the maskable interrupt.

Software interrupts can be caused by:

INT instruction - breakpoint interrupt. This is a type 3 interrupt.

INT <interrupt number> instruction - any one interrupt from available 256 interrupts.

INTO instruction - interrupt on overflow

Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When the CPU

processes this interrupt it clears TF flag before calling the interrupt processing routine.

Processor exceptions: divide error (type 0), unused opcode (type 6) and escape opcode (type

7).

Software interrupt processing is the same as for the hardware interrupts.

I/O ports

65536 8-bit I/O ports. These ports can be also addressed as 32768 16-bit I/O ports.

Registers

Most of the registers contain data/instruction offsets within 64 KB memory segment. There are

four different 64 KB segments for instructions, stack, data and extra data. To specify where in 1

MB of processor memory these 4 segments are located the processor uses four segment

registers:

Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor

instructions. The processor uses CS segment for all accesses to instructions referenced by

instruction pointer (IP) register. CS register cannot be changed directly. The CS register is

automatically updated during far jump, far call and far return instructions.

Stack segment (SS) is a 16-bit register containing address of 64KB segment with program

stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and

base pointer (BP) registers is located in the stack segment. SS register can be changed directly

using POP instruction.

Data segment (DS) is a 16-bit register containing address of 64KB segment with program data.

By default, the processor assumes that all data referenced by general registers (AX, BX, CX,

DX) and index register (SI, DI) is located in the data segment. DS register can be changed

directly using POP and LDS instructions.

Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with

program data. By default, the processor assumes that the DI register references the ES segment

in string manipulation instructions. ES register can be changed directly using POP and LES

instructions.

It is possible to change default segments used by general and index registers by prefixing

instructions with a CS, SS, DS or ES prefix.

All general registers of the 8086 microprocessor can be used for arithmetic and logic

operations. The general registers are:

Accumulator register consists of 2 8-bit registers AL and AH, which can be combined together

and used as a 16-bit register AX. AL in this case contains the low-order byte of the word, and

AH contains the high-order byte. Accumulator can be used for I/O operations and string

manipulation.

Base register consists of 2 8-bit registers BL and BH, which can be combined together and used

as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH

contains the high-order byte. BX register usually contains a data pointer used for based, based

indexed or register indirect addressing.

Count register consists of 2 8-bit registers CL and CH, which can be combined together and

used as a 16-bit register CX. When combined, CL register contains the low-order byte of the

word, and CH contains the high-order byte. Count register can be used as a counter in string

manipulation and shift/rotate instructions.

Data register consists of 2 8-bit registers DL and DH, which can be combined together and used

as a 16-bit register DX. When combined, DL register contains the low-order byte of the word,

and DH contains the high-order byte. Data register can be used as a port number in I/O

operations. In integer 32-bit multiply and divide instruction the DX register contains high-order

word of the initial or resulting number.

The following registers are both general and index registers:

Stack Pointer (SP) is a 16-bit register pointing to program stack.

Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually

used for based, based indexed or register indirect addressing.

Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect

addressing, as well as a source data address in string manipulation instructions.

Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register

indirect addressing, as well as a destination data address in string manipulation instructions.

Other registers:

Instruction Pointer (IP) is a 16-bit register.

Flags is a 16-bit register containing 9 1-bit flags:

Overflow Flag (OF) - set if the result is too large positive number, or is too small negative

number to fit into destination operand.

Direction Flag (DF) - if set then string manipulation instructions will auto-decrement index

registers. If cleared then the index registers will be auto-incremented.

Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.

Single-step Flag (TF) - if set then single-step interrupt will occur after the next instruction.

Sign Flag (SF) - set if the most significant bit of the result is set.

Zero Flag (ZF) - set if the result is zero.

Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the AL

register.

Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the result is

even.

Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit during last

result calculation.

Instruction Set

8086 instruction set consists of the following instructions:

Data moving instructions.

Arithmetic - add, subtract, increment, decrement, convert byte/word and compare.

Logic - AND, OR, exclusive OR, shift/rotate and test.

String manipulation - load, store, move, compare and scan for byte/word.

Control transfer - conditional, unconditional, call subroutine and return from subroutine.

Input/Output instructions.

Other - setting/clearing flag bits, stack operations, software interrupts, etc.

Addressing modes

Implied - the data value/data address is implicitly associated with the instruction.

Register - references the data in a register or in a register pair.

Immediate - the data is provided in the instruction.

Direct - the instruction operand specifies the memory address where data is located.

Register indirect - instruction specifies a register containing an address, where data is located.

This addressing mode works with SI, DI, BX and BP registers.

Based - 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or

BP), the resulting value is a pointer to location where data resides.

Indexed - 8-bit or 16-bit instruction operand is added to the contents of an index register (SI or

DI), the resulting value is a pointer to location where data resides.

Based Indexed - the contents of a base register (BX or BP) is added to the contents of an index

register (SI or DI), the resulting value is a pointer to location where data resides.

Based Indexed with displacement - 8-bit or 16-bit instruction operand is added to the contents

of a base register (BX or BP) and index register (SI or DI), the resulting value is a pointer to

location where data resides.

• Memory Organization

– Each byte in memory has a 20 bit address starting with 0 to 220

-1 or 1 meg of

addressable memory

– Addresses are expressed as 5 hex digits from 00000 - FFFFF

– Problem: But 20 bit addresses are TOO BIG to fit in 16 bit registers!

– Solution: Memory Segment

• Block of 64K (65,536) consecutive memory bytes

• A segment number is a 16 bit number

• Segment numbers range from 0000 to FFFF

• Within a segment, a particular memory location is specified with an offset

• An offset also ranges from 0000 to FFFF

Segmented Memory

Segmented memory addressing: absolute (linear) address is a combination of a 16-bit segment

value added to a 16-bit offset

Memory Address Generation

• The BIU has a dedicated adder for determining physical memory addresses

6 are status flags

3 are control flag

Flag Register

• Conditional flags:

– They are set according to some results of arithmetic operation. You do not need to

alter the value yourself.

• Control flags:

Used to control some operations of the MPU. These flags are to be set by you in order to

achieve some specific purposes.

Flag Register

• CF (carry) Contains carry from leftmost bit following arithmetic, also contains last bit from a

shift or rotate operation.

• OF (overflow) Indicates overflow of the leftmost bit during arithmetic.

• DF (direction) Indicates left or right for moving or comparing string data.

• IF (interrupt) Indicates whether external interrupts are being processed or ignored.

• TF (trap) Permits operation of the processor in single step mode.

• SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)

• ZF (zero) Indicates when the result of arithmetic or a comparison is zero. (1=yes)

• AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized arithmetic.

• PF (parity) Indicates the number of 1 bits that result from an operation.

Instruction Set

8086 instruction set consists of the following instructions:

Data moving instructions.

Arithmetic - add, subtract, increment, decrement, convert byte/word and compare.

Logic - AND, OR, exclusive OR, shift/rotate and test.

String manipulation - load, store, move, compare and scan for byte/word.

Control transfer - conditional, unconditional, call subroutine and return from subroutine.

Input/Output instructions.

Other - setting/clearing flag bits, stack operations, software interrupts, etc.

Addressing modes

Implied - the data value/data address is implicitly associated with the instruction.

Register - references the data in a register or in a register pair.

Immediate - the data is provided in the instruction.

Direct - the instruction operand specifies the memory address where data is located.

Register indirect - instruction specifies a register containing an address, where data is located.

This addressing mode works with SI, DI, BX and BP registers.

Based - 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or

BP), the resulting value is a pointer to location where data resides.

Indexed - 8-bit or 16-bit instruction operand is added to the contents of an index register (SI or

DI), the resulting value is a pointer to location where data resides.

Based Indexed - the contents of a base register (BX or BP) is added to the contents of an index

register (SI or DI), the resulting value is a pointer to location where data resides.

Based Indexed with displacement - 8-bit or 16-bit instruction operand is added to the contents

of a base register (BX or BP) and index register (SI or DI), the resulting value is a pointer to

location where data resides.

Memory Address Decoding

The processor can usually address a memory space that is much larger than

the memory space covered by an individual memory chip.

In order to splice a memory device into the address space of the processor,

decoding is necessary.

For example, the 8088 issues 20-bit addresses for a total of 1MB of memory

address space.

However, the BIOS on a 2716 EPROM has only 2KB of memory and 11

address pins.

A decoder can be used to decode the additional 9 address pins and allow the

EPROM to be placed in any 2KB section of the 1MB address space.

Two Mark Questions:

1.Define pipelining?

Ans: In 8086, to speedup the execution of program, the instructions fetching and

execution of instructions are overlapped each other. This technique is known as pipelining. In

pipelining, when the n th instruction is executed, the n+1 th instruction is fetched and thus the

processing speed is increased.

2. Discuss the function of instruction queue in 8086?

Ans: In 8086, a 6-byte instruction queue is presented at the Bus Interface Unit (BIU). It

is used to prefetch and store at the maximum of 6 bytes of instruction code from the memory.

Due to this, overlapping instruction fetch with instruction execution increases the processing

speed.

3. What is the maximum memory size that can be addressed by 8086?

Ans: In 8086, an memory location is addressed by 20 bit address and the address bus is

20 bit address and the address bus is 20 bits. So it can address up to one mega byte (2^20) of

memory space.

4. What is the function of the signal in 8086?

Ans: BHE signal means Bus High Enable signal. The BHE signal is made low when

there is some read or write operation is carried out. ie . When ever the data bus of the system is

busy i.e. whenever there is some data transfer then the BHE signal is made low.

5.What are the predefined interrupts in 8086?

Ans: The various predefined interrupts are,

DIVISION BY ZERO --(type 0) Interrupt.

SINGLE STEP -- (type 1) Interrupt.

NONMASKABLE -- (type2) Interrupt.

BREAK POINT -- (type 3) Interrupt.

OVER FLOW -- (type 4) Interrupt.

6. What are the different flag available in status register of 8086?

Ans: There are 6 one bit flags are present. They are,

AF - Auxiliary Carry Flag

CF - Carry Flag

OF - Overflow Flag

SF - Sign Flag

PF - Parity Flag

ZF - Zero Flag

7. List the various addressing modes present in 8086?

Ans: There are 12 addressing modes present in 8086. They are,

(a) Register and immediate addressing modes

Register addressing modes

Immediate addressing mode

(b) Memory addressing modes.

Direct addressing modes

Register indirect addressing modes

Based addressing modes

Indexed addressing modes

Based Indexed addressing modes

String addressing modes

(c) I/O addressing modes

Direct addressing mode

Indirect addressing mode

(d)Relative addressing mode

(e) Implied addressing mode

8. How single stepping can be done in 8086?

Ans: By setting the Trace Flag (TF) the 8086 goes to single-step mode. In this mode,

after the execution of each instruction s 8086 generates an internal interrupt and by writing

some interrupt service routine we can display the content of desired registers and memory

locations. So it is useful for debugging the program.

9. State the significance of LOCK signal in 8086?

Ans: If 8086 is working at maximum mode, there are multiprocessors are present. If the

system bus is given to a processor then the LOCK signal is made low. That means the system

bus is busy and it cannot be given of any other processors. After the use of the system bus again

the LOCK signal is made high. That means it is ready to give the system bus to any processor.

10. What are the functions of bus interface unit (BIU) in 8086?

Ans:

(a) Fetch instructions from memory.

(b) Fetch data from memory and I/O ports.

(c) Write data to memory and I/O ports.

(d) To communicate with outside world.

(e) Provide external bus operations and bus control signals.

11. What is the clock frequency of 8086?

Ans:

Microprocessor 8086 8086-2 8086-4

Internal clock

Frequency 5 MHz 8MHz 4MHz

External Clock

Frequency 15MHZ 24MHZ 12MHZ

12. What are the two modes of operations present in 8086?

Ans:

i. Minimum mode (or) Uniprocessor system

ii. Maximum mode (or) Multiprocessor system

13. Explain the process control instructions

Ans:

STC – It sets the carry flag & does not affect any other flag

CLC – it resets the carry flag to zero &does not affect any other flag

CMC – It complements the carry flag & does not affect any other flag

STD – It sets the direction flag to 1 so that SI and/or DI can be decremented automatically after

execution of string instruction & does not affect other flags

CLD – It resets the direction flag to 0 so that SI and/or DI can be incremented automatically

after

execution of string instruction & does not affect other flags

STI – Sets the interrupt flag to 1. Enables INTR of 8086.

CLI – Resets the interrupt flagto0. 8086 will not respond to INTR.

14. Explain REPEAT-UNTIL statements

Ans: REPEAT-UNTIL statements allow executing a series of instructions repeatedly

until some condition occurs. The REPEAT defines the start of the loop & UNTIL the end of the

loop. UNTIL has a condition when the condition is true the loop is terminated.

15. What is the purpose of segment registers in 8086?

Ans:There are 4 segment registers present in 8086. They are

1. Code Segment (CS ) register - The code segment register gives the address of the current

code segment. ie. It will points out where the instructions, to be executed, are stored in the

memory.

2. Data Segment (DS ) register - The data segment register points out where the operands are

stored in the memory.

3. Stack Segment (SS ) register - The stack segment registers points out the address of the

current stack, which is used to store the temporary results.

4. Extra Segment (ES ) register - If the amount of data used is more the Extra segment register

points out where the large amount of data is stored in the memory.

16. What is assembler?

Ans: The assembler translates the assembly language program text which is given as input to

the assembler to their binary equivalents known as object code. The time required to translate

the assembly code to object code is called access time. The assembler checks for syntax errors

& displays them before giving the object code.

17. What is loader?

Ans:The loader copies the program into the computer‘s main memory at load time and begins

the program execution at execution time.

18. What is linker?

A linker is a program used to join together several object files into one large object file. For

large programs it is more efficient to divide the large program modules into smaller modules.

Each module is individually written, tested & debugged. When all the modules work they are

linked together to form a large functioning program.

19. Explain ALIGN & ASSUME:

Ans: The ALIGN directive forces the assembler to align the next segment at an address

divisible by specified divisor. The format is ALIGN number where number can be 2, 4, 8 or 16.

Example ALIGN 8.

The ASSUME directive assigns a logical segment to a physical segment at any given time. It

tells the assembler what address will be in the segment registers at execution time. Example

ASSUME CS: code, DS: data, SS: stack

20. Explain PTR & GROUP

Ans: A program may contain several segments of the same type. The GROUP directive collects

them under a single name so they can reside in a single segment, usually a data segment. The

format is Name GROUP Seg-name,…..Seg-name PTR is used to assign a specific type to a

variable or a label. It is also used to override the declared type of a variable.

21. What are the three classifications of 8086 interrupts?

Ans:

(1) Predefined interrupts

(2) User defined Hardware interrupts

(3) User defined software interrupts.

22. What are the functions of status pins in 8086?

Ans:

S2 S1 S0 Functions

0 0 0 Interrupt

acknowledge

0 0 1 Read I/O

0 1 0 Write I/O

0 1 1 Halt

1 0 0 Code access

1 0 1 Read

memory

1 1 0 Write

memory

1 1 1 inactive

S4 S3 Functions

0 0

I/O from

extra

segment

0 1

I/O from

Stack

Segment

1 0

I/O from

Code

segment

1 0

I/O from

Data

segment

S5 --Status of interrupt enable flag

S6 --Hold acknowledge for system bus

S7 --Address transfer.

23. What are the schemes for establishing priority in order to resolve bus arbitration

problem?

Ans: There are three basic bus access control and arbitration schemes

1. Daisy Chaining

2. Independent Request

3. Polling

24.What are the different types of methods used for data transmission?

Ans: The data transmission between two points involves unidirectional or bi-directional

transmission of meaningful digital data through a medium. There are basically there modes of

data transmission.

(a) Simplex

(b) Duplex

(c) Half Duplex

In simplex mode, data is transmitted only in one direction over a single communication

channel.For example, a computer (CPU) may transmit data for a CRT display unit in this mode.

In duplex mode, data may be transferred between two transreceivers in both directions

simultaneously.

In half duplex mode, on the other hand, data transmission may take pace in either direction, but

at a time data may be transmitted only in one direction. For example, a computer may

communicate with a terminal in this mode. When the terminal sends data (i.e. terminal is

sender). The message is received by the computer (i.e the computer is receiver). However, it is

not possible to transmit data from the computer to terminal and from terminal to the computer

simultaneously.

25.What are the various programmed data transfer methods?

Ans:

i) Synchronous data transfer

ii) Asynchronous data transfer

iii) Interrupt driven data transfer

26. What is synchronous data transfer?

Ans: It is a data method which is used when the I/O device and the microprocessor match in

speed. To transfer a data to or from the device, the user program issues a suitable instruction

addressing the device. The data transfer is completed at the end of the execution of this

instruction.

27. What is asynchronous data transfer?

Ans: It is a data transfer method which is used when the speed of an I/O device does not match

with the speed of the microprocessor. Asynchronous data transfer is also called as

Handshaking.

28.What are the different inter connection topologies?

Ans:

Shared bus

Multiport Memory

Linked Input/Output

Bus window

Crossbar Switching.

29. What are the configurations used for physical interconnections?

Ans:

Star Configuration

Loop configuration

Complete interconnection

Regular topologies

Irregular topologies

SIXTEEN MARK QUESTIONS:

1. Draw the architectural block diagram of 8086. (16)

2. Explain with examples addressing modes of 8086 processor. (16)

3. Explain the interrupt structure of 8086 processor. (16)

4. Draw & explain the modes of operation of 8086. (16)

5. Explain the instruction set of 8086 with examples.(16)

1. a. Explain the addressing modes of 8086 with the help of examples? (12)

b. Write short notes on macro? (4)

2. a. Explain the instruction set 8086? (10)

b. Write an ALP in 8086 to find sum of numbers in array? (6)

3. a. Explain the addressing modes of 8086 with the help of example? (12)

b. Describe the action taken by 8086 when NMI pin is activated? (4)

4. a. Explain memory organization in 8086? (8)

b. Explain the following assembler directives (8)

i. ASSUME ii. EQU iii. DD IV. DW

5. a. With the neat sketch explain the architecture of 8086 processor? (12)

b. Give the significance of ‗O‘ flag, ‘T‘ flag, ‘I‘ flag &‘D‘flag of 8086? (4)

6.a)Discuss the interrupt system of Intel 8086. What is interrupt pointer? What is 'type' of

an interrupt? (8)

b)Discuss the various addressing modes of 8086. What are displacement, base and index?

What is an effective address or offset? (8)

7. a)What is the difference between minimum and maximum modes of 8086? How are

these modes selected? (6)

b)Draw and explain the architecture of 8086.(10)

8 a)Write an 8086 program to add two 16-bit numbers in CX and DX and store the result in

location 0500H addressed by DI.(6)

b)Draw the maximum mode module of 8086 clearly showing address latches, transreceivers,

clock generator. neatly label the diagram. terminate unused pins properly.(10)

9.Draw the interfacing diagram for 8086 based system(minimum mode)with the following

specification. -16 KB RAM -8 KB EPROM -8255 PPI in I/O address space also show the

required latches, buffers and decoder .draw the memory map for the above interface. (16)

10.a)Explain the following 8086 signals:(8) -INTR -DT/(R bar) -RESET -TEST (bar )

b)How does 8086 convert a logical address to physical address? explain with an example.(8)

11.a).Explain with the suitable diagram how 8086 access a byte or word from EVEN and ODD

memory banks.

b).State the differences between I/O mapped I/O and Memory mapped I/O.

UNIT IV MICROCONTROLLER

What are microcontrollers and what are they used for?

Like all good things, this powerful component is basically very simple. It is made by mixing

tested and high- quality "ingredients" (components) as per following receipt:

1. The simplest computer processor is used as the "brain" of the future system.

2. Depending on the taste of the manufacturer, a bit of memory, a few A/D converters, timers,

input/output lines etc. are added

3. All that is placed in some of the standard packages.

4. A simple software able to control it all and which everyone can easily learn about has been

developed.

On the basis of these rules, numerous types of microcontrollers were designed and they quickly

became man's invisible companion. Their incredible simplicity and flexibility conquered us a

long time ago and if you try to invent something about them, you should know that you are

probably late, someone before you has either done it or at least has tried to do it.

The following things have had a crucial influence on development and success of the

microcontrollers:

Powerful and carefully chosen electronics embedded in the microcontrollers can independetly

or via input/output devices (switches, push buttons, sensors, LCD displays, relays etc.), control

various processes and devices such as industrial automation, electric current, temperature,

engine performance etc.

Very low prices enable them to be embedded in such devices in which, until recent time it was

not worthwhile to embed anything. Thanks to that, the world is overwhelmed today with cheap

automatic devices and various ―smart‖ appliences.

Prior knowledge is hardly needed for programming. It is sufficient to have a PC (software in

use is not demanding at all and is easy to learn) and a simple device (called the programmer)

used for ―loading‖ raedy-to-use programs into the microcontroller.

So, if you are infected with a virus called electronics, there is nothing left for you to do but to

learn how to use and control its power.

How does the microcontroller operate?

Even though there is a large number of different types of microcontrollers and even more

programs created for their use only, all of them have many things in common. Thus, if you

learn to handle one of them you will be able to handle them all. A typical scenario on the basis

of which it all functions is as follows:

1. Power supply is turned off and everything is still…the program is loaded into the

microcontroller, nothing indicates what is about to come…

2. Power supply is turned on and everything starts to happen at high speed! The control logic

unit keeps everything under control. It disables all other circuits except quartz crystal to

operate. While the preparations are in progress, the first milliseconds go by.

3. Power supply voltage reaches its maximum and oscillator frequency becomes stable. SFRs are

being filled with bits reflecting the state of all circuits within the microcontroller. All pins are

configured as inputs. The overall electronis starts operation in rhythm with pulse sequence.

From now on the time is measured in micro and nanoseconds.

4. Program Counter is set to zero. Instruction from that address is sent to instruction decoder

which recognizes it, after which it is executed with immediate effect.

5. The value of the Program Counter is incremented by 1 and the whole process is

repeated...several million times per second.

What is what in the microcontroller?

As you can see, all the operations within the microcontroller are performed at high speed and

quite simply, but the microcontroller itself would not be so useful if there are not special

circuits which make it complete. In continuation, we are going to call your attention to them.

Read Only Memory (ROM)

Read Only Memory (ROM) is a type of memory used to permanently save the program being

executed. The size of the program that can be written depends on the size of this memory. ROM

can be built in the microcontroller or added as an external chip, which depends on the type of

the microcontroller. Both options have some disadvantages. If ROM is added as an external

chip, the microcontroller is cheaper and the program can be considerably longer. At the same

time, a number of available pins is reduced as the microcontroller uses its own input/output

ports for connection to the chip. The internal ROM is usually smaller and more expensive, but

leaves more pins available for connecting to peripheral environment. The size of ROM ranges

from 512B to 64KB.

Random Access Memory (RAM)

Random Access Memory (RAM) is a type of memory used for temporary storing data and

intermediate results created and used during the operation of the microcontrollers. The content

of this memory is cleared once the power supply is off. For example, if the program performes

an addition, it is necessary to have a register standing for what in everyday life is called the

―sum‖ . For that purpose, one of the registers in RAM is called the "sum" and used for storing

results of addition. The size of RAM goes up to a few KBs.

Electrically Erasable Programmable ROM (EEPROM)

The EEPROM is a special type of memory not contained in all microcontrollers. Its contents

may be changed during program execution (similar to RAM ), but remains permanently saved

even after the loss of power (similar to ROM). It is often used to store values, created and used

during operation (such as calibration values, codes, values to count up to etc.), which must be

saved after turning the power supply off. A disadvantage of this memory is that the process of

programming is relatively slow. It is measured in miliseconds.

Special Function Registers (SFR)

Special function registers are part of RAM memory. Their purpose is predefined by the

manufacturer and cannot be changed therefore. Since their bits are physically connected to

particular circuits within the microcontroller, such as A/D converter, serial communication

module etc., any change of their state directly affects the operation of the microcontroller or

some of the circuits. For example, writing zero or one to the SFR controlling an input/output

port causes the appropriate port pin to be configured as input or output. In other words, each bit

of this register controls the function of one single pin.

Program Counter

Program Counter is an engine running the program and points to the memory address

containing the next instruction to execute. After each instruction execution, the value of the

counter is incremented by 1. For this reason, the program executes only one instruction at a

time just as it is written. However…the value of the program counter can be changed at any

moment, which causes a ―jump‖ to a new memory location. This is how subroutines and branch

instructions are executed. After jumping, the counter resumes even and monotonous automatic

counting +1, +1, +1…

Central Processor Unit (CPU)

As its name suggests, this is a unit which monitors and controls all processes within the

microcontroller and the user cannot affect its work. It consists of several smaller subunits, of

which the most important are:

Instruction decoder is a part of the electronics which recognizes program instructions and

runs other circuits on the basis of that. The abilities of this circuit are expressed in the

"instruction set" which is different for each microcontroller family.

Arithmetical Logical Unit (ALU) performs all mathematical and logical operations upon data.

Accumulator is an SFR closely related to the operation of ALU. It is a kind of working desk

used for storing all data upon which some operations should be executed (addition, shift etc.). It

also stores the results ready for use in further processing. One of the SFRs, called the Status

Register, is closely related to the accumulator, showing at any given time the "status" of a

number stored in the accumulator (the number is greater or less than zero etc.).

Input/output ports (I/O Ports)

In order to make the microcontroller useful, it is necessary to connect it to peripheral devices.

Each microcontroller has one or more registers (called a port) connected to the microcontroller

pins

Why do we call them input/output ports? Because it is possible to change a pin function according to the

user's needs. These registers are the only registers in the microcontroller the state of which can be

checked by voltmeter

Oscillator

Even pulses generated by the oscillator enable harmonic and synchronous operation of all circuits within

the microcontroller. It is usually configured as to use quartz-crystal or ceramics resonator for frequency

stabilization. It can also operate without elements for frequency stabilization (like RC oscillator). It is

important to say that program instructions are not executed at the rate imposed by the oscillator itself,

but several times slower. It happens because each instruction is executed in several steps. For some

microcontrollers, the same number of cycles is needed to execute any instruction, while it's different for

other microcontrollers. Accordingly, if the system uses quartz crystal with a frequency of 20MHz, the

execution time of an instruction is not expected 50nS, but 200, 400 or even 800 nS, depending on the

type of the microcontroller!

Timers/Counters

Most programs use these miniature electronic "stopwatches" in their operation. These are

commonly 8- or 16-bit SFRs the contents of which is automatically incremented by each

coming pulse. Once the register is completely loaded, an interrupt is generated!

If these registers use an internal quartz oscillator as a clock source, then it is possible to

measure the time between two events (if the register value is T1 at the moment measurement

has started, and T2 at the moment it has finished, then the elapsed time is equal to the result of

subtraction T2-T1 ). If the registers use pulses coming from external source, then such a timer

is turned into a counter.

What is 8051 Standard?

Microcontroller manufacturers have been competing for a long time for attracting choosy

customers and every couple of days a new chip with a higher operating frequency, more

memory and upgraded A/D converters appeared on the market.

However, most of them had the same or at least very similar architecture known in the world of

microcontrollers as ―8051 compatible‖. What is all this about?

The whole story has its beginnings in the far 80s when Intel launched the first series of

microcontrollers called the MCS 051. Even though these microcontrollers had quite modest

features in comparison to the new ones, they conquered the world very soon and became a

standard for what nowadays is called the microcontroller.

The main reason for their great success and popularity is a skillfully chosen configuration

which satisfies different needs of a large number of users allowing at the same time constant

expansions (refers to the new types of microcontrollers). Besides, the software has been

developed in great extend in the meantime, and it simply was not profitable to change anything

in the microcontroller‘s basic core. This is the reason for having a great number of various

microcontrollers which basically are solely upgraded versions of the 8051 family. What makes

this microcontroller so special and universal so that almost all manufacturers all over the world

manufacture it today under different name?

As seen in figure above, the 8051 microcontroller has nothing impressive in appearance:

4 Kb of ROM is not much at all.

128b of RAM (including SFRs) satisfies the user's basic needs.

4 ports having in total of 32 input/output lines are in most cases sufficient to make all necessary

connections to peripheral environment.

The whole configuration is obviously thought of as to satisfy the needs of most programmers

working on development of automation devices. One of its advantages is that nothing is missing

and nothing is too much. In other words, it is created exactly in accordance to the average

user‗s taste and needs. Another advantages are RAM organization, the operation of Central

Processor Unit (CPU) and ports which completely use all recourses and enable further upgrade.

2.2 Pin out Description

Pins 1-8: Port 1 Each of these pins can be configured as an input or an output.

Pin 9: RS A logic one on this pin disables the microcontroller and clears the contents of most

registers. In other words, the positive voltage on this pin resets the microcontroller. By applying

logic zero to this pin, the program starts execution from the beginning.

Pins10-17: Port 3 Similar to port 1, each of these pins can serve as general input or output.

Besides, all of them have alternative functions:

Pin 10: RXD Serial asynchronous communication input or Serial synchronous communication

output.

Pin 11: TXD Serial asynchronous communication output or Serial synchronous communication

clock output.

Pin 12: INT0 Interrupt 0 input.

Pin 13: INT1 Interrupt 1 input.

Pin 14: T0 Counter 0 clock input.

Pin 15: T1 Counter 1 clock input.

Pin 16: WR Write to external (additional) RAM.

Pin 17: RD Read from external RAM.

Pin 18, 19: X2, X1 Internal oscillator input and output. A quartz crystal which specifies

operating frequency is usually connected to these pins. Instead of it, miniature ceramics

resonators can also be used for frequency stability. Later versions of microcontrollers operate at

a frequency of 0 Hz up to over 50 Hz.

Pin 20: GND Ground.

Pin 21-28: Port 2 If there is no intention to use external memory then these port pins are

configured as general inputs/outputs. In case external memory is used, the higher address byte,

i.e. addresses A8-A15 will appear on this port. Even though memory with capacity of 64Kb is

not used, which means that not all eight port bits are used for its addressing, the rest of them are

not available as inputs/outputs.

Pin 29: PSEN If external ROM is used for storing program then a logic zero (0) appears on it

every time the microcontroller reads a byte from memory.

Pin 30: ALE Prior to reading from external memory, the microcontroller puts the lower address

byte (A0-A7) on P0 and activates the ALE output. After receiving signal from the ALE pin, the

external register (usually 74HCT373 or 74HCT375 add-on chip) memorizes the state of P0 and

uses it as a memory chip address. Immediately after that, the ALU pin is returned its previous

logic state and P0 is now used as a Data Bus. As seen, port data multiplexing is performed by

means of only one additional (and cheap) integrated circuit. In other words, this port is used for

both data and address transmission.

Pin 31: EA By applying logic zero to this pin, P2 and P3 are used for data and address

transmission with no regard to whether there is internal memory or not. It means that even there

is a program written to the microcontroller, it will not be executed. Instead, the program written

to external ROM will be executed. By applying logic one to the EA pin, the microcontroller

will use both memories, first internal then external (if exists).

Pin 32-39: Port 0 Similar to P2, if external memory is not used, these pins can be used as

general inputs/outputs. Otherwise, P0 is configured as address output (A0-A7) when the ALE

pin is driven high (1) or as data output (Data Bus) when the ALE pin is driven low (0).

Pin 40: VCC +5V power supply.

2.3 Input/Output Ports (I/O Ports)

All 8051 microcontrollers have 4 I/O ports each comprising 8 bits which can be configured as

inputs or outputs. Accordingly, in total of 32 input/output pins enabling the microcontroller to

be connected to peripheral devices are available for use.

Pin configuration, i.e. whether it is to be configured as an input (1) or an output (0), depends on

its logic state. In order to configure a microcontroller pin as an input, it is necessary to apply a

logic zero (0) to appropriate I/O port bit. In this case, voltage level on appropriate pin will be 0.

Similarly, in order to configure a microcontroller pin as an input, it is necessary to apply a logic

one (1) to appropriate port. In this case, voltage level on appropriate pin will be 5V (as is the

case with any TTL input). This may seem confusing but don't loose your patience. It all

becomes clear after studying simple electronic circuits connected to an I/O pin.

Input/Output (I/O) pin

Figure above illustrates a simplified schematic of all circuits within the microcontroler connected to one

of its pins. It refers to all the pins except those of the P0 port which do not have pull-up resistors built-in

Input pin

A logic one (1) is applied to a bit of the P register. The output FE transistor is turned off and the

appropriate pin remains connected to the power supply voltage over a pull-up resistor of high resistance.

Output pin

A logic zero (0) is applied to a bit of the P register. The output FE transistor is turned on, thus

connecting the appropriate pin to ground.

Port 0

The P0 port is characterized by two functions. If external memory is used then the lower

address byte (addresses A0-A7) is applied on it. Otherwise, all bits of this port are configured

as inputs/outputs.

The other function is expressed when it is configured as an output. Unlike other ports consisting

of pins with built-in pull-up resistor connected by its end to 5 V power supply, pins of this port

have this resistor left out. This apparently small difference has its consequences:

Port 1

P1 is a true I/O port, because it doesn't have any alternative functions as is the case with P0, but

can be cofigured as general I/O only. It has a pull-up resistor built-in and is completely

compatible with TTL circuits.

Port 2

P2 acts similarly to P0 when external memory is used. Pins of this port occupy addresses

intended for external memory chip. This time it is about the higher address byte with addresses

A8-A15. When no memory is added, this port can be used as a general input/output port

showing features similar to P1.

Port 3

All port pins can be used as general I/O, but they also have an alternative function. In order to

use these alternative functions, a logic one (1) must be applied to appropriate bit of the P3

register. In tems of hardware, this port is similar to P0, with the difference that its pins have a

pull-up resistor built-in.

Pin's Current limitations

When configured as outputs (logic zero (0)), single port pins can receive a current of 10mA. If

all 8 bits of a port are active, a total current must be limited to 15mA (port P0: 26mA). If all

ports (32 bits) are active, total maximum current must be limited to 71mA. When these pins are

configured as inputs (logic 1), built-in pull-up resistors provide very weak current, but strong

enough to activate up to 4 TTL inputs of LS series.

Memory Organization

The 8051 has two types of memory and these are Program Memory and Data Memory.

Program Memory (ROM) is used to permanently save the program being executed, while Data

Memory (RAM) is used for temporarily storing data and intermediate results created and used

during the operation of the microcontroller. Depending on the model in use (we are still talking

about the 8051 microcontroller family in general) at most a few Kb of ROM and 128 or 256

bytes of RAM is used. However…

All 8051 microcontrollers have a 16-bit addressing bus and are capable of addressing 64 kb

memory. It is neither a mistake nor a big ambition of engineers who were working on basic

core development. It is a matter of smart memory organization which makes these

microcontrollers a real ―programmers‘ goody―.

Program Memory

The first models of the 8051 microcontroller family did not have internal program memory. It

was added as an external separate chip. These models are recognizable by their label beginning

with 803 (for example 8031 or 8032). All later models have a few Kbyte ROM embedded.

Even though such an amount of memory is sufficient for writing most of the programs, there

are situations when it is necessary to use additional memory as well. A typical example are so

called lookup tables. They are used in cases when equations describing some processes are too

complicated or when there is no time for solving them. In such cases all necessary estimates

and approximates are executed in advance and the final results are put in the tables (similar to

logarithmic tables).

EA=0 In this case, the microcontroller completely ignores internal program memory and

executes only the program stored in external memory.

EA=1 In this case, the microcontroller executes first the program from built-in ROM, then the

program stored in external memory.

In both cases, P0 and P2 are not available for use since being used for data and address

transmission. Besides, the ALE and PSEN pins are also used.

Data Memory

As already mentioned, Data Memory is used for temporarily storing data and intermediate

results created and used during the operation of the microcontroller. Besides, RAM memory

built in the 8051 family includes many registers such as hardware counters and timers,

input/output ports, serial data buffers etc. The previous models had 256 RAM locations, while

for the later models this number was incremented by additional 128 registers. However, the first

256 memory locations (addresses 0-FFh) are the heart of memory common to all the models

belonging to the 8051 family. Locations available to the user occupy memory space with

addresses 0-7Fh, i.e. first 128 registers. This part of RAM is divided in several blocks.

The first block consists of 4 banks each including 8 registers denoted by R0-R7. Prior to

accessing any of these registers, it is necessary to select the bank containing it. The next

memory block (address 20h-2Fh) is bit- addressable, which means that each bit has its own

address (0-7Fh). Since there are 16 such registers, this block contains in total of 128 bits with

separate addresses (address of bit 0 of the 20h byte is 0, while address of bit 7 of the 2Fh byte is

7Fh). The third group of registers occupy addresses 2Fh-7Fh, i.e. 80 locations, and does not

have any special functions or features.

Additional RAM

In order to satisfy the programmers‘ constant hunger for Data Memory, the manufacturers

decided to embed an additional memory block of 128 locations into the latest versions of the

8051 microcontrollers. However, it‘s not as simple as it seems to be… The problem is that

electronics performing addressing has 1 byte (8 bits) on disposal and is capable of reaching

only the first 256 locations, therefore. In order to keep already existing 8-bit architecture and

compatibility with other existing models a small trick was done.

What does it mean? It means that additional memory block shares the same addresses with

locations intended for the SFRs (80h- FFh). In order to differentiate between these two

physically separated memory spaces, different ways of addressing are used. The SFRs memory

locations are accessed by direct addressing, while additional RAM memory locations are

accessed by indirect addressing.

Memory expansion

In case memory (RAM or ROM) built in the microcontroller is not sufficient, it is possible to

add two external memory chips with capacity of 64Kb each. P2 and P3 I/O ports are used for

their addressing and data transmission.

From the user‘s point of view, everything works quite simply when properly connected because

most operations are performed by the microcontroller itself. The 8051 microcontroller has two

pins for data read RD#(P3.7) and PSEN#. The first one is used for reading data from external

data memory (RAM), while the other is used for reading data from external program memory

(ROM). Both pins are active low. A typical example of memory expansion by adding RAM and

ROM chips (Hardward architecture), is shown in figure above.

Even though additional memory is rarely used with the latest versions of the microcontrollers,

we will describe in short what happens when memory chips are connected according to the

previous schematic. The whole process described below is performed automatically.

When the program during execution encounters an instruction which resides in external

memory (ROM), the microcontroller will activate its control output ALE and set the first 8 bits

of address (A0-A7) on P0. IC circuit 74HCT573 passes the first 8 bits to memory address pins.

A signal on the ALE pin latches the IC circuit 74HCT573 and immediately afterwards 8

higher bits of address (A8-A15) appear on the port. In this way, a desired location of additional

program memory is addressed. It is left over to read its content.

Port P0 pins are configured as inputs, the PSEN pin is activated and the microcontroller reads

from memory chip.

Similar occurs when it is necessary to read location from external RAM. Addressing is

performed in the same way, while read and write are performed via signals appearing on the

control outputs RD (is short for read) or WR (is short for write).

Counters and Timers

As you already know, the microcontroller oscillator uses quartz crystal for its operation. As the

frequency of this oscillator is precisely defined and very stable, pulses it generates are always

of the same width, which makes them ideal for time measurement. Such crystals are also used

in quartz watches. In order to measure time between two events it is sufficient to count up

pulses coming from this oscillator. That is exactly what the timer does. If the timer is properly

programmed, the value stored in its register will be incremented (or decremented) with each

coming pulse, i.e. once per each machine cycle. A single machine-cycle instruction lasts for 12

quartz oscillator periods, which means that by embedding quartz with oscillator frequency of

12MHz, a number stored in the timer register will be changed million times per second, i.e.

each microsecond.

The 8051 microcontroller has 2 timers/counters called T0 and T1. As their names suggest, their

main purpose is to measure time and count external events. Besides, they can be used for

generating clock pulses to be used in serial communication, so called Baud Rate.

Timer T0

As seen in figure below, the timer T0 consists of two registers – TH0 and TL0 representing a

low and a high byte of one 16-digit binary number.

Accordingly, if the content of the timer T0 is equal to 0 (T0=0) then both registers it consists of

will contain 0. If the timer contains for example number 1000 (decimal), then the TH0 register

(high byte) will contain the number 3, while the TL0 register (low byte) will contain decimal

number 232.

Formula used to calculate values in these two registers is very simple:

TH0 × 256 + TL0 = T

Matching the previous example it would be as follows:

3 × 256 + 232 = 1000

Since the timer T0 is virtually 16-bit register, the largest value it can store is 65 535. In case of

exceeding this value, the timer will be automatically cleared and counting starts from 0. This

condition is called an overflow. Two registers TMOD and TCON are closely connected to this

timer and control its operation.

TMOD Register (Timer Mode)

The TMOD register selects the operational mode of the timers T0 and T1. As seen in figure

below, the low 4 bits (bit0 - bit3) refer to the timer 0, while the high 4 bits (bit4 - bit7) refer to

the timer 1. There are 4 operational modes and each of them is described herein.

Bits of this register have the following function:

GATE1 enables and disables Timer 1 by means of a signal brought to the INT1 pin (P3.3):

o 1 - Timer 1 operates only if the INT1 bit is set.

o 0 - Timer 1 operates regardless of the logic state of the INT1 bit.

C/T1 selects pulses to be counted up by the timer/counter 1:

o 1 - Timer counts pulses brought to the T1 pin (P3.5).

o 0 - Timer counts pulses from internal oscillator.

T1M1,T1M0 These two bits select the operational mode of the Timer 1.

T1M1 T1M0 Mode Description

0 0 0 13-bit timer

0 1 1 16-bit timer

1 0 2 8-bit auto-reload

1 1 3 Split mode

GATE0 enables and disables Timer 1 using a signal brought to the INT0 pin (P3.2):

o 1 - Timer 0 operates only if the INT0 bit is set.

o 0 - Timer 0 operates regardless of the logic state of the INT0 bit.

C/T0 selects pulses to be counted up by the timer/counter 0:

o 1 - Timer counts pulses brought to the T0 pin (P3.4).

o 0 - Timer counts pulses from internal oscillator.

T0M1,T0M0 These two bits select the oprtaional mode of the Timer 0.

T0M1 T0M0 Mode Description

0 0 0 13-bit timer

0 1 1 16-bit timer

1 0 2 8-bit auto-reload

1 1 3 Split mode

Timer 0 in mode 0 (13-bit timer)

This is one of the rarities being kept only for the purpose of compatibility with the previuos

versions of microcontrollers. This mode configures timer 0 as a 13-bit timer which consists of

all 8 bits of TH0 and the lower 5 bits of TL0. As a result, the Timer 0 uses only 13 of 16 bits.

How does it operate? Each coming pulse causes the lower register bits to change their states.

After receiving 32 pulses, this register is loaded and automatically cleared, while the higher

byte (TH0) is incremented by 1. This process is repeated until registers count up 8192 pulses.

After that, both registers are cleared and counting starts from 0

Timer 0 in mode 1 (16-bit timer)

Mode 1 configures timer 0 as a 16-bit timer comprising all the bits of both registers TH0 and

TL0. That's why this is one of the most commonly used modes. Timer operates in the same way

as in mode 0, with difference that the registers count up to 65 536 as allowable by the 16 bits.

Timer 0 in mode 2 (Auto-Reload Timer)

Mode 2 configures timer 0 as an 8-bit timer. Actually, timer 0 uses only one 8-bit register for

counting and never counts from 0, but from an arbitrary value (0-255) stored in another (TH0)

register.

The following example shows the advantages of this mode. Suppose it is necessary to

constantly count up 55 pulses generated by the clock.

If mode 1 or mode 0 is used, It is necessary to write the number 200 to the timer registers and

constantly check whether an overflow has occured, i.e. whether they reached the value 255.

When it happens, it is necessary to rewrite the number 200 and repeat the whole procedure. The

same procedure is automatically performed by the microcontroller if set in mode 2. In fact, only

the TL0 register operates as a timer, while another (TH0) register stores the value from which

the counting starts. When the TL0 register is loaded, instead of being cleared, the contents of

TH0 will be reloaded to it. Referring to the previous example, in order to register each 55th

pulse, the best solution is to write the number 200 to the TH0 register and configure the timer to

operate in mode 2.

Timer 0 in Mode 3 (Split Timer)

Mode 3 configures timer 0 so that registers TL0 and TH0 operate as separate 8-bit timers. In

other words, the 16-bit timer consisting of two registers TH0 and TL0 is split into two

independent 8-bit timers. This mode is provided for applications requiring an additional 8-bit

timer or counter. The TL0 timer turns into timer 0, while the TH0 timer turns into timer 1. In

addition, all the control bits of 16-bit Timer 1 (consisting of the TH1 and TL1 register), now

control the 8-bit Timer 1. Even though the 16-bit Timer 1 can still be configured to operate in

any of modes (mode 1, 2 or 3), it is no longer possible to disable it as there is no control bit to

do it. Thus, its operation is restricted when timer 0 is in mode 3.

The only application of this mode is when two timers are used and the 16-bit Timer 1 the

operation of which is out of control is used as a baud rate generator.

Timer Control (TCON) Register

TCON register is also one of the registers whose bits are directly in control of timer operation.

Only 4 bits of this register are used for this purpose, while rest of them is used for interrupt

control to be discussed later.

TF1 bit is automatically set on the Timer 1 overflow.

TR1 bit enables the Timer 1.

o 1 - Timer 1 is enabled.

o 0 - Timer 1 is disabled.

TF0 bit is automatically set on the Timer 0 overflow.

TR0 bit enables the timer 0.

o 1 - Timer 0 is enabled.

o 0 - Timer 0 is disabled.

How to use the Timer 0 ?

In order to use timer 0, it is first necessary to select it and configure the mode of its operation.

Bits of the TMOD register are in control of it:

Referring to figure above, the timer 0 operates in mode 1 and counts pulses generated by

internal clock the frequency of which is equal to 1/12 the quartz frequency.

Turn on the timer:

The TR0 bit is set and the timer starts operation. If the quartz crystal with frequency of 12MHz

is embedded then its contents will be incremented every microsecond. After 65.536

microseconds, the both registers the timer consists of will be loaded. The microcontroller

automatically clears them and the timer keeps on repeating procedure from the beginning until

the TR0 bit value is logic zero (0).

How to 'read' a timer?

Depending on application, it is necessary either to read a number stored in the timer registers or

to register the moment they have been cleared.

- It is extremely simple to read a timer by using only one register configured in mode 2 or 3. It

is sufficient to read its state at any moment. That's all!

- It is somehow complicated to read a timer configured to operate in mode 2. Suppose the lower

byte is read first (TL0), then the higher byte (TH0). The result is:

TH0 = 15 TL0 = 255

Everything seems to be ok, but the current state of the register at the moment of reading was:

TH0 = 14 TL0 = 255

In case of negligence, such an error in counting (255 pulses) may occur for not so obvious but

quite logical reason. The lower byte is correctly read (255), but at the moment the program

counter was about to read the higher byte TH0, an overflow occurred and the contents of both

registers have been changed (TH0: 14→15, TL0: 255→0). This problem has a simple solution.

The higher byte should be read first, then the lower byte and once again the higher byte. If the

number stored in the higher byte is different then this sequence should be repeated. It's about a

short loop consisting of only 3 instructions in the program.

There is another solution as well. It is sufficient to simply turn the timer off while reading is

going on (the TR0 bit of the TCON register should be cleared), and turn it on again after

reading is finished.

Timer 0 Overflow Detection

Usually, there is no need to constantly read timer registers. It is sufficient to register the

moment they are cleared, i.e. when counting starts from 0. This condition is called an overflow.

When it occurrs, the TF0 bit of the TCON register will be automatically set. The state of this bit

can be constantly checked from within the program or by enabling an interrupt which will stop

the main program execution when this bit is set. Suppose it is necessary to provide a program

delay of 0.05 seconds (50 000 machine cycles), i.e. time when the program seems to be

stopped:

First a number to be written to the timer registers should be calculated:

Then it should be written to the timer registers TH0 and TL0:

When enabled, the timer will resume counting from this number. The state of the TF0 bit, i.e.

whether it is set, is checked from within the program. It happens at the moment of overflow, i.e.

after exactly 50.000 machine cycles or 0.05 seconds.

UART (Universal Asynchronous Receiver and Transmitter)

One of the microcontroller features making it so powerful is an integrated UART, better known

as a serial port. It is a full-duplex port, thus being able to transmit and receive data

simultaneously and at different baud rates. Without it, serial data send and receive would be an

enormously complicated part of the program in which the pin state is constantly changed and

checked at regular intervals. When using UART, all the programmer has to do is to simply

select serial port mode and baud rate. When it's done, serial data transmit is nothing but writing

to the SBUF register, while data receive represents reading the same register. The

microcontroller takes care of not making any error during data transmission.

Serial port must be configured prior to being used. In other words, it is necessary to determine

how many bits is contained in one serial ―word‖, baud rate and synchronization clock source.

The whole process is in control of the bits of the SCON register (Serial Control).

Serial Port Control (SCON) Register

SM0 - Serial port mode bit 0 is used for serial port mode selection.

SM1 - Serial port mode bit 1.

SM2 - Serial port mode 2 bit, also known as multiprocessor communication enable bit. When

set, it enables multiprocessor communication in mode 2 and 3, and eventually mode 1. It should

be cleared in mode 0.

REN - Reception Enable bit enables serial reception when set. When cleared, serial reception

is disabled.

TB8 - Transmitter bit 8. Since all registers are 8-bit wide, this bit solves the problem of

transmiting the 9th bit in modes 2 and 3. It is set to transmit a logic 1 in the 9th bit.

RB8 - Receiver bit 8 or the 9th bit received in modes 2 and 3. Cleared by hardware if 9th bit

received is a logic 0. Set by hardware if 9th bit received is a logic 1.

TI - Transmit Interrupt flag is automatically set at the moment the last bit of one byte is sent.

It's a signal to the processor that the line is available for a new byte transmite. It must be cleared

from within the software.

RI - Receive Interrupt flag is automatically set upon one byte receive. It signals that byte is

received and should be read quickly prior to being replaced by a new data. This bit is also

cleared from within the software.

As seen, serial port mode is selected by combining the SM0 and SM2 bits:

SM0 SM1 Mode Description Baud Rate

0 0 0 8-bit Shift

Register 1/12 the quartz frequency

0 1 1 8-bit UART Determined by the timer 1

1 0 2 9-bit UART 1/32 the quartz frequency (1/64 the

quartz frequency)

1 1 3 9-bit UART Determined by the timer 1

In mode 0, serial data are transmitted and received through the RXD pin, while the TXD pin

output clocks. The bout rate is fixed at 1/12 the oscillator frequency. On transmit, the least

significant bit (LSB bit) is sent/received first.

TRANSMIT - Data transmit is initiated by writing data to the SBUF register. In fact, this

process starts after any instruction being performed upon this register. When all 8 bits have

been sent, the TI bit of the SCON register is automatically set.

RECEIVE - Data receive through the RXD pin starts upon the two following conditions are

met: bit REN=1 and RI=0 (both of them are stored in the SCON register). When all 8 bits have

been received, the RI bit of the SCON register is automatically set indicating that one byte

receive is complete.

Since there are no START and STOP bits or any other bit except data sent from the SBUF

register in the pulse sequence, this mode is mainly used when the distance between devices is

short, noise is minimized and operating speed is of importance. A typical example is I/O port

expansion by adding a cheap IC (shift registers 74HC595, 74HC597 and similar).

Mode 1

In mode 1, 10 bits are transmitted through the TXD pin or received through the RXD pin in the

following manner: a START bit (always 0), 8 data bits (LSB first) and a STOP bit (always 1).

The START bit is only used to initiate data receive, while the STOP bit is automatically written

to the RB8 bit of the SCON register.

TRANSMIT - Data transmit is initiated by writing data to the SBUF register. End of data

transmission is indicated by setting the TI bit of the SCON register.

RECEIVE - The START bit (logic zero (0)) on the RXD pin initiates data receive. The

following two conditions must be met: bit REN=1 and bit RI=0. Both of them are stored in the

SCON register. The RI bit is automatically set upon data reception is complete.

The Baud rate in this mode is determined by the timer 1 overflow.

Mode 2

In mode 2, 11 bits are transmitted through the TXD pin or received through the RXD pin: a

START bit (always 0), 8 data bits (LSB first), a programmable 9th data bit and a STOP bit

(always 1). On transmit, the 9th data bit is actually the TB8 bit of the SCON register. This bit

usually has a function of parity bit. On receive, the 9th data bit goes into the RB8 bit of the

same register (SCON).The baud rate is either 1/32 or 1/64 the oscillator frequency.

TRANSMIT - Data transmit is initiated by writing data to the SBUF register. End of data

transmission is indicated by setting the TI bit of the SCON register.

RECEIVE - The START bit (logic zero (0)) on the RXD pin initiates data receive. The

following two conditions must be met: bit REN=1 and bit RI=0. Both of them are stored in the

SCON register. The RI bit is automatically set upon data reception is complete.

Mode 3

Mode 3 is the same as Mode 2 in all respects except the baud rate. The baud rate in Mode 3 is

variable.

8051 Microcontroller Interrupts

There are five interrupt sources for the 8051, which means that they can recognize 5 different

events that can interrupt regular program execution. Each interrupt can be enabled or disabled

by setting bits of the IE register. Likewise, the whole interrupt system can be disabled by

clearing the EA bit of the same register. Refer to figure below.

Now, it is necessary to explain a few details referring to external interrupts- INT0 and INT1. If

the IT0 and IT1 bits of the TCON register are set, an interrupt will be generated on high to low

transition, i.e. on the falling pulse edge (only in that moment). If these bits are cleared, an

interrupt will be continuously executed as far as the pins are held low.

IE Register (Interrupt Enable)

EA - global interrupt enable/disable:

o 0 - disables all interrupt requests.

o 1 - enables all individual interrupt requests.

ES - enables or disables serial interrupt:

o 0 - UART system cannot generate an interrupt.

o 1 - UART system enables an interrupt.

ET1 - bit enables or disables Timer 1 interrupt:

o 0 - Timer 1 cannot generate an interrupt.

o 1 - Timer 1 enables an interrupt.

EX1 - bit enables or disables external 1 interrupt:

o 0 - change of the pin INT0 logic state cannot generate an interrupt.

o 1 - enables an external interrupt on the pin INT0 state change.

ET0 - bit enables or disables timer 0 interrupt:

o 0 - Timer 0 cannot generate an interrupt.

o 1 - enables timer 0 interrupt.

EX0 - bit enables or disables external 0 interrupt:

o 0 - change of the INT1 pin logic state cannot generate an interrupt.

o 1 - enables an external interrupt on the pin INT1 state change.

Interrupt Priorities

It is not possible to forseen when an interrupt request will arrive. If several interrupts are

enabled, it may happen that while one of them is in progress, another one is requested. In order

that the microcontroller knows whether to continue operation or meet a new interrupt request,

there is a priority list instructing it what to do.

The priority list offers 3 levels of interrupt priority:

1. Reset! The apsolute master. When a reset request arrives, everything is stopped and the

microcontroller restarts.

2. Interrupt priority 1 can be disabled by Reset only.

3. Interrupt priority 0 can be disabled by both Reset and interrupt priority 1.

The IP Register (Interrupt Priority Register) specifies which one of existing interrupt sources

have higher and which one has lower priority. Interrupt priority is usually specified at the

beginning of the program. According to that, there are several possibilities:

If an interrupt of higher priority arrives while an interrupt is in progress, it will be

immediately stopped and the higher priority interrupt will be executed first.

If two interrupt requests, at different priority levels, arrive at the same time then the higher

priority interrupt is serviced first.

If the both interrupt requests, at the same priority level, occur one after another, the one which

came later has to wait until routine being in progress ends.

If two interrupt requests of equal priority arrive at the same time then the interrupt to be

serviced is selected according to the following priority list:

1. External interrupt INT0

2. Timer 0 interrupt

3. External Interrupt INT1

4. Timer 1 interrupt

5. Serial Communication Interrupt

IP Register (Interrupt Priority)

The IP register bits specify the priority level of each interrupt (high or low priority).

PS - Serial Port Interrupt priority bit

o Priority 0

o Priority 1

PT1 - Timer 1 interrupt priority

o Priority 0

o Priority 1

PX1 - External Interrupt INT1 priority

o Priority 0

o Priority 1

PT0 - Timer 0 Interrupt Priority

o Priority 0

o Priority 1

PX0 - External Interrupt INT0 Priority

o Priority 0

o Priority 1

Handling Interrupt

When an interrupt request arrives the following occurs:

1. Instruction in progress is ended.

2. The address of the next instruction to execute is pushed on the stack.

3. Depending on which interrupt is requested, one of 5 vectors (addresses) is written to the

program counter in accordance to the table below:

4.

Interrupt Source Vector (address)

IE0 3 h

TF0 B h

TF1 1B h

RI, TI 23 h

All addresses are in hexadecimal format

5. These addresses store appropriate subroutines processing interrupts. Instead of them, there are

usually jump instructions specifying locations on which these subroutines reside.

6. When an interrupt routine is executed, the address of the next instruction to execute is poped

from the stack to the program counter and interrupted program resumes operation from where it

left off.

External Memory:

The 8051 has three very general types of memory. To effectively program the 8051 it is

necessary to have a basic understanding of these memory types.

The memory types are illustrated in the following graphic. They are: On-Chip Memory,

External Code Memory, and External RAM.

On-Chip Memory refers to any memory (Code, RAM, or other) that physically exists on the

microcontroller itself. On-chip memory can be of several types, but we'll get into that shortly.

External Code Memory is code (or program) memory that resides off-chip. This is often in the

form of an external EPROM.

External RAM is RAM memory that resides off-chip. This is often in the form of standard

static RAM or flash RAM.

Code Memory

Code memory is the memory that holds the actual 8051 program that is to be run. This memory

is limited to 64K and comes in many shapes and sizes: Code memory may be found on-chip,

either burned into the microcontroller as ROM or EPROM. Code may also be stored completely

off-chip in an external ROM or, more commonly, an external EPROM. Flash RAM is also

another popular method of storing a program. Various combinations of these memory types

may also be used--that is to say, it is possible to have 4K of code memory on-chip and 64k of

code memory off-chip in an EPROM.

When the program is stored on-chip the 64K maximum is often reduced to 4k, 8k, or 16k. This

varies depending on the version of the chip that is being used. Each version offers specific

capabilities and one of the distinguishing factors from chip to chip is how much ROM/EPROM

space the chip has.

However, code memory is most commonly implemented as off-chip EPROM. This is especially

true in low-cost development systems and in systems developed by students.

Programming Tip: Since code memory is restricted to 64K, 8051 programs are limited to

64K. Some assemblers and compilers offer ways to get around this limit when used with

specially wired hardware. However, without such special compilers and hardware, programs

are limited to 64K.

External RAM

As an obvious opposite of Internal RAM, the 8051 also supports what is called External RAM.

As the name suggests, External RAM is any random access memory which is found off-chip.

Since the memory is off-chip it is not as flexible in terms of accessing, and is also slower. For

example, to increment an Internal RAM location by 1 requires only 1 instruction and 1

instruction cycle. To increment a 1-byte value stored in External RAM requires 4 instructions

and 7 instruction cycles. In this case, external memory is 7 times slower!

What External RAM loses in speed and flexibility it gains in quantity. While Internal RAM is

limited to 128 bytes (256 bytes with an 8052), the 8051 supports External RAM up to 64K.

Programming Tip: The 8051 may only address 64k of RAM. To expand RAM beyond this

limit requires programming and hardware tricks. You may have to do this "by hand" since

many compilers and assemblers, while providing support for programs in excess of 64k, do not

support more than 64k of RAM. This is rather strange since it has been my experience that

programs can usually fit in 64k but often RAM is what is lacking. Thus if you need more than

64k of RAM, check to see if your compiler supports it-- but if it doesn't, be prepared to do it by

hand.

On-Chip Memory

As mentioned at the beginning of this chapter, the 8051 includes a certain amount of on-chip

memory. On-chip memory is really one of two types: Internal RAM and Special Function

Register (SFR) memory. The layout of the 8051's internal memory is presented in the following

memory map:

As is illustrated in this map, the 8051 has a bank of 128 bytes of Internal RAM. This Internal

RAM is found on-chip on the 8051 so it is the fastest RAM available, and it is also the most

flexible in terms of reading, writing, and modifying its contents. Internal RAM is volatile, so

when the 8051 is reset this memory is cleared.

The 128 bytes of internal ram is subdivided as shown on the memory map. The first 8 bytes

(00h - 07h) are "register bank 0". By manipulating certain SFRs, a program may choose to use

register banks 1, 2, or 3. These alternative register banks are located in internal RAM in

addresses 08h through 1Fh. We'll discuss "register banks" more in a later chapter. For now it is

sufficient to know that they "live" and are part of internal RAM.

Bit Memory also lives and is part of internal RAM. We'll talk more about bit memory very

shortly, but for now just keep in mind that bit memory actually resides in internal RAM, from

addresses 20h through 2Fh.

The 80 bytes remaining of Internal RAM, from addresses 30h through 7Fh, may be used by

user variables that need to be accessed frequently or at high-speed. This area is also utilized by

the microcontroller as a storage area for the operating stack. This fact severely limits the 8051s

stack since, as illustrated in the memory map, the area reserved for the stack is only 80 bytes--

and usually it is less since this 80 bytes has to be shared between the stack and user variables.

Register Banks

The 8051 uses 8 "R" registers which are used in many of its instructions. These "R" registers

are numbered from 0 through 7 (R0, R1, R2, R3, R4, R5, R6, and R7). These registers are

generally used to assist in manipulating values and moving data from one memory location to

another. For example, to add the value of R4 to the Accumulator, we would execute the

following instruction:

ADD A,R4

Thus if the Accumulator (A) contained the value 6 and R4 contained the value 3, the

Accumulator would contain the value 9 after this instruction was executed.

However, as the memory map shows, the "R" Register R4 is really part of Internal RAM.

Specifically, R4 is address 04h. This can be see in the bright green section of the memory map.

Thus the above instruction accomplishes the same thing as the following operation:

ADD A,04h

This instruction adds the value found in Internal RAM address 04h to the value of the

Accumulator, leaving the result in the Accumulator. Since R4 is really Internal RAM 04h, the

above instruction effectively accomplished the same thing.

But watch out! As the memory map shows, the 8051 has four distinct register banks. When the

8051 is first booted up, register bank 0 (addresses 00h through 07h) is used by default.

However, your program may instruct the 8051 to use one of the alternate register banks; i.e.,

register banks 1, 2, or 3. In this case, R4 will no longer be the same as Internal RAM address

04h. For example, if your program instructs the 8051 to use register bank 3, "R" register R4

will now be synonymous with Internal RAM address 1Ch.

The concept of register banks adds a great level of flexibility to the 8051, especially when

dealing with interrupts (we'll talk about interrupts later). However, always remember that the

register banks really reside in the first 32 bytes of Internal RAM.

Programming Tip: If you only use the first register bank (i.e. bank 0), you may use Internal

RAM locations 08h through 1Fh for your own use. But if you plan to use register banks 1, 2, or

3, be very careful about using addresses below 20h as you may end up overwriting the value of

your "R" registers!

Bit Memory

The 8051, being a communications-oriented microcontroller, gives the user the ability to access

a number of bit variables. These variables may be either 1 or 0.

There are 128 bit variables available to the user, numberd 00h through 7Fh. The user may make

use of these variables with commands such as SETB and CLR. For example, to set bit number

24 (hex) to 1 you would execute the instruction:

SETB 24h

It is important to note that Bit Memory is really a part of Internal RAM. In fact, the 128 bit

variables occupy the 16 bytes of Internal RAM from 20h through 2Fh. Thus, if you write the

value FFh to Internal RAM address 20h youve effectively set bits 00h through 07h. That is to

say that:

MOV 20h,#0FFh

is equivalent to:

SETB 00h

SETB 01h

SETB 02h

SETB 03h

SETB 04h

SETB 05h

SETB 06h

SETB 07h

As illustrated above, bit memory isnt really a new type of memory. Its really just a subset of

Internal RAM. But since the 8051 provides special instructions to access these 16 bytes of

memory on a bit by bit basis it is useful to think of it as a separate type of memory. However,

always keep in mind that it is just a subset of Internal RAM--and that operations performed on

Internal RAM can change the values of the bit variables.

Programming Tip: If your program does not use bit variables, you may use Internal RAM

locations 20h through 2Fh for your own use. But if you plan to use bit variables, be very careful

about using addresses from 20h through 2Fh as you may end up overwriting the value of your

bits!

Bit variables 00h through 7Fh are for user-defined functions in their programs. However, bit

variables 80h and above are actually used to access certain SFRs on a bit-by-bit basis. For

example, if output lines P0.0 through P0.7 are all clear (0) and you want to turn on the P0.0

output line you may either execute:

MOV P0,#01h

or you may execute:

SETB 80h

Both these instructions accomplish the same thing. However, using the SETB command will

turn on the P0.0 line without effecting the status of any of the other P0 output lines. The MOV

command effectively turns off all the other output lines which, in some cases, may not be

acceptable.

Programming Tip: By default, the 8051 initializes the Stack Pointer (SP) to 07h when the

microcontroller is booted. This means that the stack will start at address 08h and expand

upwards. If you will be using the alternate register banks (banks 1, 2 or 3) you must initialize

the stack pointer to an address above the highest register bank you will be using, otherwise the

stack will overwrite your alternate register banks. Similarly, if you will be using bit variables it

is usually a good idea to initialize the stack pointer to some value greater than 2Fh to guarantee

that your bit variables are protected from the stack.

Special Function Register (SFR) Memory

Special Function Registers (SFRs) are areas of memory that control specific functionality of the

8051 processor. For example, four SFRs permit access to the 8051s 32 input/output lines.

Another SFR allows a program to read or write to the 8051s serial port. Other SFRs allow the

user to set the serial baud rate, control and access timers, and configure the 8051s interrupt

system.

When programming, SFRs have the illusion of being Internal Memory. For example, if you

want to write the value "1" to Internal RAM location 50 hex you would execute the instruction:

MOV 50h,#01h

Similarly, if you want to write the value "1" to the 8051s serial port you would write this value

to the SBUF SFR, which has an SFR address of 99 Hex. Thus, to write the value "1" to the

serial port you would execute the instruction:

MOV 99h,#01h

As you can see, it appears that the SFR is part of Internal Memory. This is not the case. When

using this method of memory access (its called direct address), any instruction that has an

address of 00h through 7Fh refers to an Internal RAM memory address; any instruction with an

address of 80h through FFh refers to an SFR control register.

UNIT IV – 8051 MICRO CONTROLLER

PART - A

I. TWO MARK QUESTIONS:

1. What is Micro controller?

2. What is the difference between microprocessor & micro controller?

3. What are the features of ROM & RAM in 8051 micro controller?

4.Explain the instructions used to access external RAM.

5.List the applications of microcontroller?

SIXTEEN MARK QUESTIONS:

1. Draw and Explain the block diagram of 8051. (16)

2. Explain the memory structure of 8051 (16)

3. Explain interrupt structure of 8051. (16)

4. Explain the I/O port structure of 8051. (16)

5. Draw the pin configuration of 8051, Explain each pin. (16)

1. What is assembler

2. Mention the program used for assembling and running an assembly language program

3. How many instructions are used in 8051 family classify them

4. Mention the functional groups of 8051 instructions

5. Mention the various types of addressing modes used in 8051 instructions

6. What are the addressing modes used for accessing for SFR

7. What are the three important classes of data transfer instructions

8. Mention the various types of instructions uses stack memory during their Execution

9. What are the different types of MOVC instructions

10. What is the difference between MOVX A @ Ri and MOVX A, @DPTR instructions

11. What are the different types of arithmetic operations performed in signed and unsigned

numbers

12. Which is conditional flag used in signal operations

13. What will happen in OV flag during execution of MULAB instructions

14. What are the different types of addition function performed in 8051

15. What will happen during the execution of DA A instruction

16. How are the logical instructions classified

17. What are the different types of logical operations performed in 8051

18. What will happen during the execution of SWAPA instruction?

19. What is the use of compare instruction used in 8051

20. Mention the different types of compare instruction used in 8051

21. State the two ways of transferring data in serial manner

22. Define packed BCD numbers

23. What are the different types of byte level conditional jump instructions used in 8051

24. Mention the rotate instruction in 8051

25. Mention the different types of unconditional jumps instruction

26. What is the basic difference between jump and call instruction

27. What are the different types of bit level jump instructions

28. What is the basic difference between AJMP and LJMP instructions

29. Why do the call instructions use the stack memory

30. What is the basic difference RET RETI instructions

31. What is the use of time delay routine

32. What are the instructions used for changing the control program

33. Mention some assembler directives

UNIT V

Addressing

While operating, the processor processes data as per program instructions. Each instruction

consists of two parts. One part describes WHAT should be done, while the other explains HOW

to do it. The latter part can be a data (binary number) or the address at which the data is stored.

Two ways of addressing are used for all 8051 microcontrollers depending on which part of

memory should be accessed:

Direct Addressing

On direct addressing, the address of memory location containing data to be read is specified in

instruction. The address may contain a number being changed during operation (variable). For

example:

Since the address is only one byte in size (the largest number is 255), only the first 255

locations of RAM can be accessed this way. The first half of RAM is available for use, while

another half is reserved for SFRs.

MOV A,33h; Means: move a number from address 33 hex. to accumulator

Indirect Addressing

On indirect addressing, a register containing the address of another register is specified in

instruction. Data to be used in the program is stored in the letter register. For example:

Indirect addressing is only used for accessing RAM locations available for use (never for

accessing SFRs). This is the only way of accessing all the latest versions of the microcontrollers

with additional memory block (128 locations of RAM). Simply put, when the program

encounters instruction including ―@‖ sign and if the specified address is higher than 128 ( 7F

hex.), the processor knows that indirect addressing is used and skips memory space reserved for

SFRs.

MOV A,@R0; Means: Store the value from the register whose address is in the R0 register into accumulator

On indirect addressing, registers R0, R1 or Stack Pointer are used for specifying 8-bit

addresses. Since only 8 bits are avilable, it is possible to access only registers of internal RAM

this way (128 locations when speaking of previous models or 256 locations when speaking of

latest models of microcontrollers). If an extra memory chip is added then the 16-bit DPTR

Register (consisting of the registers DPTRL and DPTRH) is used for specifying address. In this

way it is possible to access any location in the range of 64K.

2.5 Special Function Registers (SFRs)

Special Function Registers (SFRs) are a sort of control table used for running and monitoring

the operation of the microcontroller. Each of these registers as well as each bit they include, has

its name, address in the scope of RAM and precisely defined purpose such as timer control,

interrupt control, serial communication control etc. Even though there are 128 memory

locations intended to be occupied by them, the basic core, shared by all types of 8051

microcontrollers, has only 21 such registers. Rest of locations are intensionally left unoccupied

in order to enable the manufacturers to further develop microcontrollers keeping them

compatible with the previous versions. It also enables programs written a long time ago for

microcontrollers which are out of production now to be used today.

A Register (Accumulator)

A register is a general-purpose register used for storing intermediate results obtained during

operation. Prior to executing an instruction upon any number or operand it is necessary to store

it in the accumulator first. All results obtained from arithmetical operations performed by the

ALU are stored in the accumulator. Data to be moved from one register to another must go

through the accumulator. In other words, the A register is the most commonly used register and

it is impossible to imagine a microcontroller without it. More than half instructions used by the

8051 microcontroller use somehow the accumulator.

B Register

Multiplication and division can be performed only upon numbers stored in the A and B

registers. All other instructions in the program can use this register as a spare accumulator (A).

R Registers (R0-R7)

This is a common name for 8 general-purpose registers (R0, R1, R2 ...R7). Even though they are

not true SFRs, they deserve to be discussed here because of their purpose. They occupy 4 banks within

RAM. Similar to the accumulator, they are used for temporary storing variables and intermediate results

during operation. Which one of these banks is to be active depends on two bits of the PSW Register.

Active bank is a bank the registers of which are currently used

The following example best illustrates the purpose of these registers. Suppose it is necessary to

perform some arithmetical operations upon numbers previously stored in the R registers:

(R1+R2) - (R3+R4). Obviously, a register for temporary storing results of addition is needed.

This is how it looks in the program:

MOV A,R3; Means: move number from R3 into accumulator

ADD A,R4; Means: add number from R4 to accumulator (result remains in accumulator)

MOV R5,A; Means: temporarily move the result from accumulator into R5

MOV A,R1; Means: move number from R1 to accumulator

ADD A,R2; Means: add number from R2 to accumulator

SUBB A,R5; Means: subtract number from R5 (there are R3+R4)

Program Status Word (PSW) Register

PSW register is one of the most important SFRs. It contains several status bits that reflect the

current state of the CPU. Besides, this register contains Carry bit, Auxiliary Carry, two register

bank select bits, Overflow flag, parity bit and user-definable status flag.

P - Parity bit. If a number stored in the accumulator is even then this bit will be automatically

set (1), otherwise it will be cleared (0). It is mainly used during data transmit and receive via

serial communication.

- Bit 1. This bit is intended to be used in the future versions of microcontrollers.

OV Overflow occurs when the result of an arithmetical operation is larger than 255 and cannot

be stored in one register. Overflow condition causes the OV bit to be set (1). Otherwise, it will

be cleared (0).

RS0, RS1 - Register bank select bits. These two bits are used to select one of four register

banks of RAM. By setting and clearing these bits, registers R0-R7 are stored in one of four

banks of RAM.

RS1 RS2 Space in RAM

0 0 Bank0 00h-07h

0 1 Bank1 08h-0Fh

1 0 Bank2 10h-17h

1 1 Bank3 18h-1Fh

F0 - Flag 0. This is a general-purpose bit available for use.

AC - Auxiliary Carry Flag is used for BCD operations only.

CY - Carry Flag is the (ninth) auxiliary bit used for all arithmetical operations and shift

instructions.

Data Pointer Register (DPTR)

DPTR register is not a true one because it doesn't physically exist. It consists of two separate

registers: DPH (Data Pointer High) and (Data Pointer Low). For this reason it may be treated as

a 16-bit register or as two independent 8-bit registers. Their 16 bits are primarly used for

external memory addressing. Besides, the DPTR Register is usually used for storing data and

intermediate results.

Stack Pointer (SP) Register

A value stored in the Stack Pointer points to the first free stack address and permits stack

availability. Stack pushes increment the value in the Stack Pointer by 1. Likewise, stack pops

decrement its value by 1. Upon any reset and power-on, the value 7 is stored in the Stack

Pointer, which means that the space of RAM reserved for the stack starts at this location. If

another value is written to this register, the entire Stack is moved to the new memory location.

P0, P1, P2, P3 - Input/Output Registers

If neither external memory nor serial communication system are used then 4 ports with in total

of 32 input/output pins are available for connection to peripheral environment. Each bit within

these ports affects the state and performance of appropriate pin of the microcontroller. Thus, bit

logic state is reflected on appropriate pin as a voltage (0 or 5 V) and vice versa, voltage on a pin

reflects the state of appropriate port bit.

As mentioned, port bit state affects performance of port pins, i.e. whether they will be

configured as inputs or outputs. If a bit is cleared (0), the appropriate pin will be configured as

an output, while if it is set (1), the appropriate pin will be configured as an input. Upon reset

and power-on, all port bits are set (1), which means that all appropriate pins will be configured

as inputs.

Types of instructions

Depending on operation they perform, all instructions are divided in several groups:

Arithmetic Instructions

Branch Instructions

Data Transfer Instructions

Logic Instructions

Bit-oriented Instructions

The first part of each instruction, called MNEMONIC refers to the operation an instruction

performs (copy, addition, logic operation etc.). Mnemonics are abbreviations of the name of

operation being executed. For example:

INC R1 - Means: Increment register R1 (increment register R1);

LJMP LAB5 - Means: Long Jump LAB5 (long jump to the address marked as LAB5);

JNZ LOOP - Means: Jump if Not Zero LOOP (if the number in the accumulator is not 0, jump to the

address marked as LOOP);

The other part of instruction, called OPERAND is separated from mnemonic by at least one

whitespace and defines data being processed by instructions. Some of the instructions have no

operand, while some of them have one, two or three. If there is more than one operand in an

instruction, they are separated by a comma. For example:

RET - return from a subroutine;

JZ TEMP - if the number in the accumulator is not 0, jump to the address marked as TEMP;

ADD A,R3 - add R3 and accumulator;

CJNE A,#20,LOOP - compare accumulator with 20. If they are not equal, jump to the address marked as

LOOP;

Arithmetic instructions

Arithmetic instructions perform several basic operations such as addition, subtraction, division,

multiplication etc. After execution, the result is stored in the first operand. For example:

ADD A,R1 - The result of addition (A+R1) will be stored in the accumulator.

Arithmetic Instructions

Mnemonic Description Byte Cycle

ADD A,Rn Adds the register to the accumulator 1 1

ADD A,direct Adds the direct byte to the accumulator 2 2

ADD A,@Ri Adds the indirect RAM to the accumulator 1 2

ADD A,#data Adds the immediate data to the accumulator 2 2

ADDC A,Rn Adds the register to the accumulator with a carry flag 1 1

ADDC

A,direct Adds the direct byte to the accumulator with a carry flag 2 2

ADDC A,@Ri Adds the indirect RAM to the accumulator with a carry

flag 1 2

ADDC

A,#data

Adds the immediate data to the accumulator with a carry

flag 2 2

SUBB A,Rn Subtracts the register from the accumulator with a

borrow 1 1

SUBB

A,direct

Subtracts the direct byte from the accumulator with a

borrow 2 2

SUBB A,@Ri Subtracts the indirect RAM from the accumulator with a

borrow 1 2

SUBB A,#data Subtracts the immediate data from the accumulator with

a borrow 2 2

INC A Increments the accumulator by 1 1 1

INC Rn Increments the register by 1 1 2

INC Rx Increments the direct byte by 1 2 3

INC @Ri Increments the indirect RAM by 1 1 3

DEC A Decrements the accumulator by 1 1 1

DEC Rn Decrements the register by 1 1 1

DEC Rx Decrements the direct byte by 1 1 2

DEC @Ri Decrements the indirect RAM by 1 2 3

INC DPTR Increments the Data Pointer by 1 1 3

MUL AB Multiplies A and B 1 5

DIV AB Divides A by B 1 5

DA A Decimal adjustment of the accumulator according to

BCD code 1 1

Branch Instructions

There are two kinds of branch instructions:

Unconditional jump instructions: upon their execution a jump to a new location from where the

program continues execution is executed.

Conditional jump instructions: a jump to a new program location is executed only if a specified

condition is met. Otherwise, the program normally proceeds with the next instruction.

Branch Instructions

Mnemonic Description Byte Cycle

ACALL addr11 Absolute subroutine call 2 6

LCALL addr16 Long subroutine call 3 6

RET Returns from subroutine 1 4

RETI Returns from interrupt subroutine 1 4

AJMP addr11 Absolute jump 2 3

LJMP addr16 Long jump 3 4

SJMP rel Short jump (from –128 to +127 locations relative to

the following instruction) 2 3

JC rel Jump if carry flag is set. Short jump. 2 3

JNC rel Jump if carry flag is not set. Short jump. 2 3

JB bit,rel Jump if direct bit is set. Short jump. 3 4

JBC bit,rel Jump if direct bit is set and clears bit. Short jump. 3 4

JMP @A+DPTR Jump indirect relative to the DPTR 1 2

JZ rel Jump if the accumulator is zero. Short jump. 2 3

JNZ rel Jump if the accumulator is not zero. Short jump. 2 3

CJNE A,direct,rel Compares direct byte to the accumulator and jumps if

not equal. Short jump. 3 4

CJNE A,#data,rel Compares immediate data to the accumulator and

jumps if not equal. Short jump. 3 4

CJNE

Rn,#data,rel

Compares immediate data to the register and jumps if

not equal. Short jump. 3 4

CJNE

@Ri,#data,rel

Compares immediate data to indirect register and

jumps if not equal. Short jump. 3 4

DJNZ Rn,rel Decrements register and jumps if not 0. Short jump. 2 3

DJNZ Rx,rel Decrements direct byte and jump if not 0. Short jump. 3 4

NOP No operation 1 1

Data Transfer Instructions

Data transfer instructions move the content of one register to another. The register the content

of which is moved remains unchanged. If they have the suffix ―X‖ (MOVX), the data is

exchanged with external memory.

Data Transfer Instructions

Mnemonic Description Byte Cycle

MOV A,Rn Moves the register to the accumulator 1 1

MOV A,direct Moves the direct byte to the accumulator 2 2

MOV A,@Ri Moves the indirect RAM to the accumulator 1 2

MOV A,#data Moves the immediate data to the accumulator 2 2

MOV Rn,A Moves the accumulator to the register 1 2

MOV Rn,direct Moves the direct byte to the register 2 4

MOV Rn,#data Moves the immediate data to the register 2 2

MOV direct,A Moves the accumulator to the direct byte 2 3

MOV direct,Rn Moves the register to the direct byte 2 3

MOV direct,direct Moves the direct byte to the direct byte 3 4

MOV direct,@Ri Moves the indirect RAM to the direct byte 2 4

MOV direct,#data Moves the immediate data to the direct byte 3 3

MOV @Ri,A Moves the accumulator to the indirect RAM 1 3

MOV @Ri,direct Moves the direct byte to the indirect RAM 2 5

MOV @Ri,#data Moves the immediate data to the indirect RAM 2 3

MOV

DPTR,#data Moves a 16-bit data to the data pointer 3 3

MOVC

A,@A+DPTR

Moves the code byte relative to the DPTR to the

accumulator (address=A+DPTR) 1 3

MOVC

A,@A+PC

Moves the code byte relative to the PC to the

accumulator (address=A+PC) 1 3

MOVX A,@Ri Moves the external RAM (8-bit address) to the

accumulator 1 3-10

MOVX

A,@DPTR

Moves the external RAM (16-bit address) to the

accumulator 1 3-10

MOVX @Ri,A Moves the accumulator to the external RAM (8-bit

address) 1 4-11

MOVX

@DPTR,A

Moves the accumulator to the external RAM (16-bit

address) 1 4-11

PUSH direct Pushes the direct byte onto the stack 2 4

POP direct Pops the direct byte from the stack/td> 2 3

XCH A,Rn Exchanges the register with the accumulator 1 2

XCH A,direct Exchanges the direct byte with the accumulator 2 3

XCH A,@Ri Exchanges the indirect RAM with the accumulator 1 3

XCHD A,@Ri Exchanges the low-order nibble indirect RAM with

the accumulator 1 3

Logic Instructions

Logic instructions perform logic operations upon corresponding bits of two registers. After

execution, the result is stored in the first operand.

Logic Instructions

Mnemonic Description Byte Cycle

ANL A,Rn AND register to accumulator 1 1

ANL A,direct AND direct byte to accumulator 2 2

ANL A,@Ri AND indirect RAM to accumulator 1 2

ANL A,#data AND immediate data to accumulator 2 2

ANL direct,A AND accumulator to direct byte 2 3

ANL direct,#data AND immediae data to direct register 3 4

ORL A,Rn OR register to accumulator 1 1

ORL A,direct OR direct byte to accumulator 2 2

ORL A,@Ri OR indirect RAM to accumulator 1 2

ORL direct,A OR accumulator to direct byte 2 3

ORL direct,#data OR immediate data to direct byte 3 4

XRL A,Rn Exclusive OR register to accumulator 1 1

XRL A,direct Exclusive OR direct byte to accumulator 2 2

XRL A,@Ri Exclusive OR indirect RAM to accumulator 1 2

XRL A,#data Exclusive OR immediate data to accumulator 2 2

XRL direct,A Exclusive OR accumulator to direct byte 2 3

XORL direct,#data Exclusive OR immediate data to direct byte 3 4

CLR A Clears the accumulator 1 1

CPL A Complements the accumulator (1=0, 0=1) 1 1

SWAP A Swaps nibbles within the accumulator 1 1

RL A Rotates bits in the accumulator left 1 1

RLC A Rotates bits in the accumulator left through carry 1 1

RR A Rotates bits in the accumulator right 1 1

RRC A Rotates bits in the accumulator right through carry 1 1

Bit-oriented Instructions

Similar to logic instructions, bit-oriented instructions perform logic operations. The difference

is that these are performed upon single bits.

Bit-oriented Instructions

Mnemonic Description Byte Cycle

CLR C Clears the carry flag 1 1

CLR bit Clears the direct bit 2 3

SETB C Sets the carry flag 1 1

SETB bit Sets the direct bit 2 3

CPL C Complements the carry flag 1 1

CPL bit Complements the direct bit 2 3

ANL C,bit AND direct bit to the carry flag 2 2

ANL C,/bit AND complements of direct bit to the carry flag 2 2

ORL C,bit OR direct bit to the carry flag 2 2

ORL C,/bit OR complements of direct bit to the carry flag 2 2

MOV C,bit Moves the direct bit to the carry flag 2 2

MOV bit,C Moves the carry flag to the direct bit 2 3

3.2 Description of all 8051 instructions

Here is a list of the operands and their meanings:

A - accumulator;

Rn - is one of working registers (R0-R7) in the currently active RAM memory bank;

Direct - is any 8-bit address register of RAM. It can be any general-purpose register or a SFR (I/O

port, control register etc.);

@Ri - is indirect internal or external RAM location addressed by register R0 or R1;

#data - is an 8-bit constant included in instruction (0-255);

#data16 - is a 16-bit constant included as bytes 2 and 3 in instruction (0-65535);

addr16 - is a 16-bit address. May be anywhere within 64KB of program memory;

addr11 - is an 11-bit address. May be within the same 2KB page of program memory as the first byte

of the following instruction;

rel - is the address of a close memory location (from -128 to +127 relative to the first byte of the

following instruction). On the basis of it, assembler computes the value to add or subtract from the

number currently stored in the program counter;

bit - is any bit-addressable I/O pin, control or status bit; and

C - is carry flag of the status register (register PSW).

ACALL addr11 - Absolute subroutine call

Assembly Language program: ntroduction

It was time that hardware-oriented to the core made compromise if they wanted to stay ―in the

game‖. Namely, unlike other circuits which only need to be connected to other components and

powered in order to be of any use, microcontrollers require to be programmed as well.

Fortunately, they still didn't progress so far in their evolution, so that all microcontroller

families ―understand‖ only one language - machine language. That's a good thing. The bad one

is that, even primitive, this language of zeros and ones can only be understood by

microcontrollers and some of the experts working on its development. In order to bridge this

gap between machine and humans, the first high-level programming language called Assembly

language was created.

The main problem of remembering codes recognized as instructions by electronics was solved

therefore, but another one, equally complicated to both us and ―them‖(microcontrollers) arose.

This problem was also easily solved by means of the program for a PC called assembler and a

simple device called programmer.

This program enables the PC to receive commands in the form of abbreviations and convert

them unerringly into so called ―executable file‖. The moment of compiling a program into

machine language is crucial as this file, called HEX file, represents a series of binary numbers

understandable to microcontrollers only. The program written in assembly language cannot be

executed practically unless this file is loaded into the microcontroller memory. This is the

moment when the last link in the chain - the programmer - appears on the scene. It is a small

device connected to a PC via some of the ports and has a socket for placing chip in.

5.1 Elements of Assembly Language

Assembly language is basically like any other language, which means that it has its words, rules

and syntax. The basic elements of assembly language are:

Labels;

Orders;

Directives; and

Comments.

Syntax of Assembly language

When writing a program in assembly language it is necessary to observe specific rules in order

to enable the process of compiling into executable ―HEX-code‖ to run without errors. These

compulsory rules are called syntax and there are only several of them:

Every program line may consist of a maximum of 255 characters;

Every program line to be compiled, must start with a symbol, label, mnemonics or directive;

Text following the mark ―;‖ in a program line represents a comment ignored (not compiled) by the

assembler; and

All the elements of one program line (labels, instructions etc.) must be separated by at least one space

character. For the sake of better clearness, a push button TAB on a keyboard is commonly used instead

of it, so that it is easy to delimit columns with labels, directives etc. in a program.

I. TWO MARK QUESTIONS:

1. What is the use of DA instruction in 8051?

2. What is the function of program counter in 8051?

3. What is the job of the TMOD register?

4. Name any four conditional jump instructions of 8051.

5. Explain the bit level logical instructions of 8051.

PART - B

II. SIXTEEN MARK QUESTIONS:

1. List the instruction set of 8051, microcontroller that affect the flag bits. (16)

2. How 8051 micro controller can be interfaced with external ROM, Explain with Examples.

(16)

3. Explain the matrix keyboard interface of 8051. (16)

4. Draw the format of SCON register. Explain different bits in it. (16)

5. Write an assembly language program to find ―Fibonacci Series‖ of ―N‖ given term. (16)

6. Write an assembly language program for stepper motor control. (16)

Two mark Questions: Unit IV and Unit V:

1. How many I/o ports are in 8051 mention their names

2. Which port is called multifunctional I/O port

3. Specify the byte address of 8051 I/O port

4. How is internal ram classified

5. How many bit addressable locations in internal ram area

6. Specify the address range of bit addressable locations in internal RAM

7. What type of addressing is used for accessing bit addressable internal RAM

8. What will happen during the execution of MOV P2.0, c instruction

9. How many timers are in 8051 specify their names

10. Mention the four modes of timer operation what are the registers used for timer/counter

operation

11. What Is the use of gate bit in TMOD registers

12. Define timer operation

13. Define counter operation

14. Specify the different modes of serial communication

15. What are the registers used for timer counter operations

16. What is the difference between mode2 and mode3 of serial communication

17. How is the serial transmission initiated

18. What are the condition required for initiating serial reception

19. What are the registers used for serial communication in 8051

20. Specify the baud rate of serial communication in mode 2

21. What is the use of RS 232

22. Why drivers are used in between RS 232 and microcontroller

23. What is interrupt signal

24. Mention the various types of interrupts in 8051

25. Specify the vector address of 8051 interrupts

26. What are the SFR registers used in interrupt operation

27. Specify the priorities of interrupt within level

UNIVERSITY QUESTIONS:

2008 Anna University EC1303-Microprocessor and its Applications Question Paper

EC1303-MICROPROCESSORS AND ITS APPLICATIONS

(Common to B.E (Part-time) Fourth Semester Regulation 2005)

Time:Three hours Maximum:100 marks

Answer ALL questions

PART A –(2*10=20marks)

1. What are the classifications of instruction set according to word size?

2. Name the modes available in 8255 A control word format.

3. What are the methods used for communication in 8055?

4. List the control words of RS-232 C.

5. What are the segment registers of 8086?

6. Name any four flags of 8086.

7. What are the addressing modes of 8051?

8. List the interrupts in 8051.

9. What are the functions of assembler and linker in 8051?

10. What are the commonly used ADC’s and DAC.

PART-B(16x5=80)

11.(a) Draw and explain the pin details of 8085A briefly. [ 16]

Or

(b)(i) What are the flags affected by ALU in 8085? Explain briefly. [10]

(ii) Draw the schematic diagram of memory interfacing in 8085. [6]

12.(a)(i)Draw and explain the control word format of 8255A for ADC operation. [ 8 ]

(ii)Give a brief note on the following [8 ]

(1) 8251 I/O device

(2) GPIB Bus

Or

(b) Draw and explain the logic diagram of 8279 [16]

13.(a)(i) Draw the pin diagram of 8086 CPU with its control signals. [8 ]

(ii) Explain how an interrupt is responded by 8086 CPU. [8 ]

Or

(b)(i) Write a program in 8086 to find an average between two temperatures. [8 ]

(ii) Describe data transfer instructions of 8086 CPU. [8 ]

14.(a)(i) Explain the features of 8051 microcontroller [6]

(ii) Draw and explain the connection diagrams of 8051 with external ROM. [10]

Or

(b)(i) Explain the basic structure of assembly language program of 8051. [8 ]

(ii) Explain the memory organization of 8051. [8 ]

15.(a)(i)List and explain conditional jump instructions of 8051 [6]

(ii) Draw and explain briefly the connection diagram of ADC with peripheral device

with one example. [10]

Or

(b)(i) What are the features of LCD? How it is interfaced with 8051? [2+6]

(ii) Write a program in 8051 to transfer letter ‘A’ serially at 4800 bandrate,continuously . *8 +