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MIPS Processor
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MIPS Processor. Registers in MIPS In MIPS, there are 32 Registers. We need read up to two registers, and write to up to one register. Think registers.

Jan 15, 2016

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MIPS Processor

MIPS ProcessorRegisters in MIPSIn MIPS, there are 32 Registers.We need read up to two registers, and write to up to one register.Think registers as D flip-flops. Each register has 32 Dffs.The control signals are: readReg1, readReg2: 5 bits. Used to specify which reg to read.writeReg: 5-bits. Used to specify which reg to write.Data: if write, what data should be written into the reg.RegWrite: whether to write or not.

This is for read.The data is connected to every register.Use RegWrite, generate a ``LOAD signal for the register you want to write to.Every register has a LOAD signal. If that signal is `1, new data will be set. Only the target registers LOAD signal is `1. To write to a registerRAM

11/8/2007 10:04:17 AMweek11-5.ppt6A RAM Example

RAM. Control signals:address: If write, which location to write to. If read, which location to read from.Chip select: whether to use this chip or not.Output enable: whether to enable output (output some voltage or in high-impedence state)Write enable: whether to read or write.Din: if write, what data should be written into the location specified by address. Assume that there is a RAM with only 2 address lines and two bit data lines. How many bits can it hold?

The processorWe now know all the parts in the processor. ALUPCRegister fileAlsoRAMHow to put them together? How to make them execute an instruction as we need?ALU

The execution of an instructionFirst we need to fetch the instruction at the address given by the current PC from instruction memoryThen we need to decode the instructionBased on the instruction, we need to do accordinglyFor sequential instructions, we then go the next instruction by increasing the PC. For jump and branch instructions, PC will be changed

11/18/2007 7:39:36 PMweek13-1.ppt10Basic MIPS ImplementationWe will focus on design of a basic MIPS processor that includes a subset of the core MIPS instruction setThe arithmetic-logic instructions add, sub, and, or, and sltThe memory-reference instructions load word and store wordThe instructions branch equal and jump

11/18/2007 7:39:36 PMweek13-1.ppt12MIPS Implementation OverviewFor every instruction, the first two steps are identicalFetch the instruction from the memory according to the value of the program counterRead one or two registers (using fields of instructions to select the registers)For load word, we need to read only one registerMost other instructions (except jump) require we read two registersAfter the two steps, the actions required depend on the instructionsHowever, the actions are similar11/18/2007 7:39:38 PMweek13-1.ppt13Instruction Fetch and PC IncrementSince for every instruction, the first step is to fetch the instruction from memoryIn addition, for most instructions, the next instruction will be at PC + 4

11/18/2007 7:39:38 PMweek13-1.ppt14R-type InstructionsAlso called arithmetic-logical instructionsIncluding add, sub, and, or, and sltEach one reads from two registers, performs an arithmetic or logical operation on the registers, and then write the result to a register11/15/2007 5:02:08 PMweek-13-3.ppt15R-type Instructions

Suppose the instruction is add $t0, $t1, $t2, what are the read reg1, read reg2, and write reg? What is the value of RegWrite? How to control the ALU to do add? Datapath only for R-type instructions

Datapath only for R-type instructions (Answer)

11/15/2007 5:02:10 PMweek-13-3.ppt18Data Transfer InstructionsLoad word and store word instructions have the following general formlw $rt, offset_value($rs) opcode (6 bits) rs (5 bits) rt (5 bits) offset (16 bits)sw $rt, offset_value($rs)opcode (6 bits) rs (5 bits) rt (5 bits) offset (16 bits)They need to compute a memory address by adding the base register to the sign-extended 16-bit offset ()18LoadFor instruction load $t0, 16($t1), what should the control signal be?

RegWrite = 1ALUOp = add code19Data path

Do both lw and sw, and ask for student participation20Data path only for lw (answer)

Data path only for sw (answer)

11/18/2007 7:39:42 PMweek13-1.ppt23Branch InstructionBeq has three operands, two registers that are compared for equality and a 16-bit offset used to compute the branch-target addressbeq $rs, $rt, offsetopcode (6 bits) rs (5 bits) rt (5 bits) offset (16 bits)Note that the 16-bit offset is given in terms of instructions, not bytes and is relative to PC + 4Designing a processor only for beq

Are these enough? How many adders do we need? How to do the selection?Designing a processor only for beq

11/18/2007 7:39:43 PMweek13-1.ppt26Designing a processor only for beq (answer)

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