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2ELE0065 Mini Project ROM-Based Sine Wave Generator Introductory Lecture BSc Hon. Multimedia Technology. Mini Projects. Author: University of Hertfordshire Date created: Date revised: 2009 Abstract The following resources come from the 2009/10 BEng in Digital Systems and Computer Engineering (course number 2ELE0065) from the University of Hertfordshire. All the mini projects are designed as level two modules of the undergraduate programmes. The objectives of this module are to demonstrate, within an embedded development environment: Processor – to – processor communication Multiple processors to perform one computation task using parallel processing This project requires the establishment of a communication protocol between two 68000-based microcomputer systems. Using ‘C’, students will write software to control all aspects of complex data transfer system, demonstrating knowledge of handshaking, transmission protocols, transmission overhead, bandwidth, memory addressing. Students will then demonstrate and analyse parallel processing of a mathematical problem using two processors. This project requires two students working as a team. © University of Hertfordshire 2009 This work is licensed under a Creative Commons Attribution 2.0 License.
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Mini Project- ROM Based Sine Wave Generator

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The following resources come from the 2009/10 BEng in Digital Systems and Computer Engineering (course number 2ELE0065) from the University of Hertfordshire. All the mini projects are designed as level two modules of the undergraduate programmes.

The objectives of this module are to demonstrate, within an embedded development environment:

• Processor – to – processor communication
• Multiple processors to perform one computation task using parallel processing

This project requires the establishment of a communication protocol between two 68000-based microcomputer systems. Using ‘C’, students will write software to control all aspects of complex data transfer system, demonstrating knowledge of handshaking, transmission protocols, transmission overhead, bandwidth, memory addressing. Students will then demonstrate and analyse parallel processing of a mathematical problem using two processors. This project requires two students working as a team.
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Page 1: Mini Project- ROM Based Sine Wave Generator

2ELE0065

Mini Project ROM-Based Sine Wave Generator

Introductory Lecture

BSc Hon. Multimedia Technology. Mini Projects.

Author: University of HertfordshireDate created:Date revised: 2009

AbstractThe following resources come from the 2009/10 BEng in Digital Systems and Computer Engineering (course number 2ELE0065) from the University of Hertfordshire. All the mini projects are designed as level two modules of the undergraduate programmes.

The objectives of this module are to demonstrate, within an embedded development environment:

• Processor – to – processor communication• Multiple processors to perform one computation task using parallel processing

This project requires the establishment of a communication protocol between two 68000-based microcomputer systems. Using ‘C’, students will write software to control all aspects of complex data transfer system, demonstrating knowledge of handshaking, transmission protocols, transmission overhead, bandwidth, memory addressing. Students will then demonstrate and analyse parallel processing of a mathematical problem using two processors. This project requires two students working as a team.

© University of Hertfordshire 2009 This work is licensed under a Creative Commons Attribution 2.0 License.

Page 2: Mini Project- ROM Based Sine Wave Generator

2ELE0065

Contents– Outline– Sequential Logic– D Flip-Flop– D Flip-FLOP with Asynchronous RESET– D Flip-FLOP with Synchronous RESET– 2-bit Counter with Asynchronous RESET– Memories– Array Types– Array type conversion– Conversion Summary– Resizing– Modelling memories – RAM– Modelling memories – ROM– VHDL Test Benches– WAIT Statement– Assertion Statement– A Test Bench Template– A Test Bench Example– Credits

In addition to the resources found below there are supporting documents which should be used in combination with this resource. Please see:

Mini Projects - Introductory presentation.

Mini Projects - E-Log.

Mini Projects - Staff & Student Guide.

Mini Projects - Standard Grading Criteria.

Mini Projects - Reflection.

You will also need the ‘Mini Project- ROM-Based Sine Wave Generator’ text document.

Page 3: Mini Project- ROM Based Sine Wave Generator

2ELE0065 Outline

Sequential design using VHDL

o Flip Flops

o Counters

o Memories

RAMs

ROMs

Page 4: Mini Project- ROM Based Sine Wave Generator

2ELE0065 Sequential Logic

Digital electronics is classified into:o Combinatorial logic

o Sequential logic

Combinatorial logic: output is a function of, and only of, the present input

Sequential logic : output depends not only on the present input but also on the history of the input

o It has storage (memory)

Combinatoriallogic Memory

element

Inputs

outputs

Page 5: Mini Project- ROM Based Sine Wave Generator

2ELE0065 Sequential Logic

Two types of Sequential circuits:

o Synchronous sequential circuits

o Asynchronous sequential circuits

Synchronous: logic responds to changes of input signals according to the state of a clock signal

Asynchronous: logic responds to the external system almost instantly

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2ELE0065 D Flip-FLOP

D Q

D Flip-Flop

CLK

Timing diagram

CLK D Q (t+1)

0 - Q (t)

1 0 0

1 1 1

Truth table

t0 t1 t2 t3

CLK

D

Q

Time

Page 7: Mini Project- ROM Based Sine Wave Generator

2ELE0065 D Flip-FLOP

D Q

D Flip-Flop

CLK

entity DFF isport( D: in std_logic;

CLK: in std_logic;Q: out std_logic );

end DFF;----------------------------------------------architecture DFF_arch of DFF isbegin

process (CLK) begin

-- clock rising edge

if (CLK='1' and CLK'event) then Q <= D;end if;

end process;

end DFF_arch;

Detecting Rising Clock Edge:

(CLK='1' and CLK'event) or rising_edge(CLK)

Detecting Falling Clock Edge?

Page 8: Mini Project- ROM Based Sine Wave Generator

2ELE0065 D Flip-FLOP with Asynchronous RESET

Timing diagram t0 t1 t2 t3

CLK

D

QTime

ARESET

D Q

D Flip-Flop

CLK

ARESET

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2ELE0065 D Flip-FLOP with Asynchronous RESET

D Q

D Flip-Flop

CLK

ARESET

entity DFF isport( D: in std_logic;

CLK: in std_logic;ARESET in std_logic;Q: out std_logic );

end DFF;----------------------------------------------architecture DFF_arch of DFF isbegin

process (CLK, ARESET) begin

if (ARESET =’1’) then Q <= '0';elsif (CLK='1' and CLK'event) then Q <= D;end if;

end process;

end DFF_arch;

Page 10: Mini Project- ROM Based Sine Wave Generator

2ELE0065 D Flip-FLOP with Synchronous RESET

Timing diagram

D Q

D Flip-Flop

CLK

SRESET

Exercise 1 entity DFF isport( D, CLK, SRESET: in std_logic;

Q: out std_logic );end DFF;

-----------------------------------------------------------------------------------

architecture DFF_arch of DFF is

?end DFF_arch;

t0 t1 t2 t3

CLK

D

QTime

SRESET

Page 11: Mini Project- ROM Based Sine Wave Generator

2ELE0065 D Flip-FLOP with Synchronous RESET

D Q

D Flip-Flop

CLK

SRESET

entity DFF isport( D: in std_logic;

CLK: in std_logic;SRESET in std_logic;Q: out std_logic );

end DFF;----------------------------------------------architecture DFF_arch of DFF isbegin

process (CLK, SRESET) begin

if (CLK='1' and CLK'event) then

if (SRESET =’1’) then Q <= ’0’;

else Q <= D;end if;

end if;

end process;

end DFF_arch;

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2ELE0065 2-bit Counter with Asynchronous RESET

Timing diagram

Exercise 2

t0 t1 t2 t3

CLK

RESET

O

EN

t4 t5 t6 t7 t8

U 0 1 2 3 0

entity counter isport( CLK, RESET, EN: in std_logic;

O: out std_logic_vector (0 to 1) );end counter;-----------------------------------------------------------------------------------

architecture counter_arch of counter is

?end counter_arch;

Counter0 to 3

RESET

CLK

EN O

2

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2ELE0065

Counter0 to 3

RESET

CLK

EN O

2

entity counter isport( CLK, RESET, EN: in std_logic;

O: out std_logic_vector (0 to 1) );end counter;-----------------------------------------------------------------------------------

architecture counter_arch of counter is

signal O_sig: std_logic_vector(0 to 1);

begin

process(CLK, RESET, EN) begin

if (RESET = '1') then O_sig <= "00";

elsif (CLK = '1' and CLK'event) thenif EN = '1' thenO_sig <= O_sig + 1;end if;end if;

end process;

-- concurrent assignment statement O <= O_sig;

end counter_arch;

2-bit Counter with Asynchronous RESET

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2ELE0065 Memories

Array types

Writing to an array

Signed and unsigned types

Array type conversion

Conversion functions

Resizing functions

Modelling memories

o RAMs

o ROMs

Page 15: Mini Project- ROM Based Sine Wave Generator

2ELE0065 Array Types

An array is a collection of elements of the same type. The type of the elements can be any kind of type including another array type

Constrained array declaration: declares a new array type with a fixed number of elements

Unconstrained array declaration: the number of elements is not specified type ROM is

array (integer range <>) of std_logic_vector (3 downto 0);

constant ROM4x4: ROM (0 to 3) := ( 0 => "0001",

1 => "0010", 2 => "0100", others => "1000" );

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2ELE0065 Writing to an array

Write a value to a single array location

Fill the entire array with the same value

RAM(address)<= ”0000”;

Or

RAM (address) <= (others => ’0’);

type RAM256x4 is array (0 to 255) of std_logic_vector (3 downto 0);

signal RAM: RAM256x4;

RAM <= (others => ”0000”);

Or

RAM <= (others => (others => ’0’));

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2ELE0065 SIGNED and UNSIGNED types

The package NUMERIC_STD exists for the purpose of doing arithmetic on vectors

It contains two new data types: unsigned and signed

o They represent unsigned and two’s complement binary numbers

o They are vectors, and so are very similar to std_logic_vector in use

Page 18: Mini Project- ROM Based Sine Wave Generator

2ELE0065 Array type conversion

unsigned, signed and std_logic_vector are known as closely related types in VHDL

o They are all arrays of the type STD_LOGIC

X <= type_name (Y)

signal A : unsigned (7 downto 0);signal B : signed (7 downto 0);signal C : std_logic_vector (7 downto 0);

A <= unsigned (B);B <= signed (A);A <= unsigned (C);C <= ? (B)

Page 19: Mini Project- ROM Based Sine Wave Generator

2ELE0065 Conversion functions

A function can be written to convert a value from any data type to a different data type

VHDL does NOT provide any predefined conversion functions

o Ready written conversion functions are available in the packages distributed by synthesis tool vendors and other specialised VHDL utility vendors

library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;-----------------------------------------------

signal A : unsigned (7 downto 0);signal B : signed (7 downto 0);signal N : integer;

Page 20: Mini Project- ROM Based Sine Wave Generator

2ELE0065 Numeric_std and std_logic_vector

In order to do arithmetic operations on values of the type std_logic_vector the values must first be converted to one of the types unsigned or signed

Using numeric_std, conversions between the types std_logic_vector and integer have to be in two steps

library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;-----------------------------------------------

signal A : std_logic_vector (7 downto 0);signal B : integer;

-----------------------------------------------

B <= TO_INTEGER (UNSIGNED(A));

A <= STD_LOGIC_VECTOR (TO_UNSIGNED (B, 8));

Page 21: Mini Project- ROM Based Sine Wave Generator

2ELE0065 Conversions- Summary

Page 22: Mini Project- ROM Based Sine Wave Generator

2ELE0065 Resizing

Numeric_std package contains resizing functions

They are used for resizing a signed/unsigned value

NATURAL is an integer subtype (0 to integer’high)

Page 23: Mini Project- ROM Based Sine Wave Generator

2ELE0065 Resizing - Example

library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;-----------------------------------------------

signal A : unsigned (7 downto 0);signal B : unsigned (15 downto 0);signal C : signed (7 downto 0);signal D : signed (15 downto 0);

------------------------------------------------- statement 1B <= resize (A, 16); -- or (A, B’lenght)

--statement 2D <= resize (C, 16);

--statement 3A <= resize (B, 8); -- or A <= B(7 downto 0)

--statement 4C <= resize (D, 8);

--statement 5C <= D(10 downto 3);

Statement 1

Statement 2

Statements 3 and 4

Statement 5

Page 24: Mini Project- ROM Based Sine Wave Generator

2ELE0065 Modelling memories - RAM

entity RAM_ENT is

port( CLK: in std_logic; EN: in std_logic; -- Enable RE: in std_logic; -- Read Enable WE: in std_logic; -- Write Enable RD_Addr: in std_logic_vector(8 downto 0); -- Read Address WR_Addr: in std_logic_vector(8 downto 0); -- Write Address WR_Data: in std_logic_vector(7 downto 0); -- Data input of RAM RD_Data: out std_logic_vector(7 downto 0) -- Data output of RAM);end RAM_ENT;

Page 25: Mini Project- ROM Based Sine Wave Generator

2ELE0065 Modelling memories - RAM

architecture RAM_ARCH of RAM_ENT is

type ram_type is array (0 to 511) of std_logic_vector(7 downto 0);

signal ram: ram_type;

begin -- Read process process(CLK, RE) begin if (CLK'event and CLK='1') then if EN='1' then if RE='1' then RD_Data <= ram(to_integer(unsigned(RD_Addr))); else RD_Data <= (others => 'Z'); end if; end if; end if; end process;

-- Write process process(CLK, WE) begin if (CLK'event and CLK='1') then if EN='1' then if WE='1' then ram(to_integer(unsigned(WR_Addr))) <= WR_Data; end if; end if; end if; end process;

end RAM_ARCH;

Page 26: Mini Project- ROM Based Sine Wave Generator

2ELE0065 Modelling memories - ROM

entity ROM_ent is port ( CLK : in std_logic; CE : in std_logic; RE : in std_logic; ADDR : in std_logic_vector (2 downto 0); DATA : out std_logic_vector (3 downto 0) );end ROM_ent;

Page 27: Mini Project- ROM Based Sine Wave Generator

2ELE0065 Modelling memories - ROM

architecture ROM_arch of ROM_ent is

type ROM is array (0 to 7) of std_logic_vector (3 downto 0);

constant Content: ROM := ( 0 => "0001", 1 => "0010", 2 => "0100", 3 => "1000", 4 => "1010", 5 => "0011", 6 => "1100", others => "1111" );

begin

process(CLK, RE, CE) begin if( CLK'event and CLK = '1' ) then if CE = '1' then if( RE = '1' ) then

DATA <= Content(to_integer(unsigned (ADDR)));

else DATA <= "ZZZZZZZZ"; end if; end if; end if; end process;

end ROM_arch;

Page 28: Mini Project- ROM Based Sine Wave Generator

2ELE0065

Wait statement

After Statement

Assertion statement

Writing a VHDL test bench

o Test Bench template

o Example

VHDL Test BenchesVHDL Test Benches

Page 29: Mini Project- ROM Based Sine Wave Generator

2ELE0065 WAIT Statement

The wait statement explicitly specifies the conditions under which a process may resume execution after being suspended

wait for time expression;

wait on signal;

wait until <condition>;

Page 30: Mini Project- ROM Based Sine Wave Generator

2ELE0065 WAIT Statement

1. Causes suspension of the process for a period of time given by the evaluation of time expression

2. Causes a process to suspend execution until an events occurs on one or more signals in a group of signals

3. The third form can specify a <condition> that evaluates to a Boolean value, TRUE or FALSE

1- wait for time expression;

wait for 10 ns;

2- wait on signal;

wait on clk, reset;

3- wait until <condition>;

wait until A>B;

Page 31: Mini Project- ROM Based Sine Wave Generator

2ELE0065 WAIT Statement - Example

A process that generates a clock with a 10 ns period

-- Clock generation process

Clock_gen: process

beginCLK <= '0';wait for 5 ns;CLK <= '1';wait for 5 ns;

end process clock_gen;

Page 32: Mini Project- ROM Based Sine Wave Generator

2ELE0065 Creating Signal Waveforms Using After Clause

It is possible to assign multiple values to a signal, each with a different delay value

Example

Must appear in increasing order

RESET <= ’1’, ’0’ after 10ns, ’1’ after 15ns,’0’ after 60ns;

Page 33: Mini Project- ROM Based Sine Wave Generator

2ELE0065 Assertion Statement

A statement that checks that a specified condition is true and reports an error if it is not

assert condition

report string

severity severity_level;

Must evaluate to a Boolean value (true or false)If false, it is said that an assertion violation occurred

A message to be reported when assertion violation occurred

Predefined severity names are: NOTE: used to pass information messages from simulatorWARNING: used in unusual situation in which the simulation can be continuedERROR: used when assertion violation makes continuation of the simulation not feasibleFAILURE: used when the assertion violation is a fatal error and the simulation must be stopped

Page 34: Mini Project- ROM Based Sine Wave Generator

2ELE0065 Assertion Statement

Example

assert not (S=’1’ and R=’1’)

report ”Both values of signals S and R are equal to 1”

severity error;

When the values of the signals S and R are equal to ’1’, the message is displayed and the simulation is stopped because the severity is set to error

Page 35: Mini Project- ROM Based Sine Wave Generator

2ELE0065 VHDL Test Bench

A test bench is a specification in VHDL that plays the role of a complete simulation environment for the analysed Design

o Analysed design: Unit Under Test (UUT)

A test bench contains:

o The UUT

o Stimuli for the simulation

Page 36: Mini Project- ROM Based Sine Wave Generator

2ELE0065 VHDL Test Bench

The UUT is instantiated as a component of the test bench

The architecture of the test bench specifies stimuli for the UUT’s ports

testbench

TesterUnit Under

Test(UUT)

Page 37: Mini Project- ROM Based Sine Wave Generator

2ELE0065 A Test Bench Template

testbenchUnit Under

Test(UUT)

Tester

entity model_name isport (input_signals: in type; output_signals: out type);end model_name;

architecture model_arch of model_name is

[Declarations]

begin

architecture body

end model_arch;

entity test_bench_name is --the entity interface is emptyend test_bench_name;

architecture test_bench_arch of test_bench_name is

-- Component declaration for the UUT

component model_name isport (input_signals: in type; output_signals: out type);end component;

--Declare all signals used to connect tester and model

signal internal_signals : type := initialisation;

begin

-- Instantiate the UUT

uut: model_name port map ( port => signal1, … );

-- Place stimulus here

end test_bench_arch;

Page 38: Mini Project- ROM Based Sine Wave Generator

2ELE0065 A Test Bench Example

Truth table

entity DFF isport( CLK: in std_logic;

D: in std_logic;Q: out std_logic;RESET: in std_logic );

end DFF;----------------------------------------------architecture DFF_arch of DFF isbegin

process (CLK, RESET) begin

-- Sequential statements -- to implement the D Filp-Flop

end process;

end DFF_arch;

VHDL code to describe the D FF

Page 39: Mini Project- ROM Based Sine Wave Generator

2ELE0065 A Test Bench Example

VHDL test bench to simulate the D FF

Page 40: Mini Project- ROM Based Sine Wave Generator

2ELE0065 A Test Bench Example

Page 41: Mini Project- ROM Based Sine Wave Generator

2ELE0065 A Test Bench Example

FALSE

Page 42: Mini Project- ROM Based Sine Wave Generator

2ELE0065 A Test Bench Exercise

entity JKFF isport( CLK, J, K, RESET: in std_logic;

Q: out std_logic );end JKFF;

architecture JKFF_arch of JKFF isbegin process (CLK, RESET) begin

-- Sequential statements -- to implement the JK FF

end process;

end JKFF_arch;

Write the process part of the test bench that generates the following inputs:

Page 43: Mini Project- ROM Based Sine Wave Generator

2ELE0065 Solution

Page 44: Mini Project- ROM Based Sine Wave Generator

2ELE0065

This resource was created by the University of Hertfordshire and released as an open educational resource through the Open Engineering Resources project of the HE Academy Engineering Subject Centre. The Open Engineering Resources project was funded by HEFCE and part of the JISC/HE Academy UKOER programme.

Where screenshots are taken from Altium Designer 6, and appear courtesy of Premier EDA Solutions Ltd.

© University of Hertfordshire 2009

                

This work is licensed under a Creative Commons Attribution 2.0 License.

The name of the University of Hertfordshire, UH and the UH logo are the name and registered marks of the University of Hertfordshire. To the fullest extent permitted by law the University of Hertfordshire reserves all its rights in its name and marks which may not be used except with its written permission.

The JISC logo is licensed under the terms of the Creative Commons Attribution-Non-Commercial-No Derivative Works 2.0 UK: England & Wales Licence.  All reproductions must comply with the terms of that licence.

The HEA logo is owned by the Higher Education Academy Limited may be freely distributed and copied for educational purposes only, provided that appropriate acknowledgement is given to the Higher Education Academy as the copyright holder and original publisher.