MC0062 Digital Systems, Computer Organization & Architecture

Model Question Paper

Subject Code: MC0062

Subject Name: Digital System, Computer organization and

Architecture.

Credits: 4 Marks: 140

Part A(one mark questions)

1. In Decimal number system, the digits to the right side of the decimal point are known as

_______________

A. fractional part

B. integer part.

C. Real part

D. Imaginary part.

2. The binary value of the decimal number 10 is equal to ______________

A. 11011(2)

B. 1010(2)

C. 1011(2)

D. 1101(2)

3. In Boolean algebra, 1+1= ____________

A. 1

B. 2

C. 11

D. 10

4. In Boolean Algebra, a+bc = _______________

A. (a).(b+c)

B. (a+b).(a+c)

C. (a+b).(b+c)

D. (a+c).(b)

5. The ANDed terms in a Sum of products (SOP) form are known as _______________

A. sum

B. product

C. maxterms

D. minterms.

6. The output of a NOR gate is LOW any time at least one of its inputs is

___________________

A. LOW

B. HIGH

C. Neither LOW nor HIGH

D. None of the above.

7. What is the main purpose of Karnaugh map (K-map) ?

A. Convert logic expression into SOP form

B. Convert logic expression into POS form

C. Simplify logic expression

D. Map the logic expression into table form.

8. The four variable K-map consists of _________ cells

A. 4

B. 8

C. 16

D. 32

9. How many inputs are there in full adder?

A. 1

B. 2

C. 3

D. 4

10. How many inputs are there in full subtractor?

A. 1

B. 2

C. 3

D. 4

11. In SR latch circuit, when S = 0 and R = 0, the output of the latch ___________________

A. changes the previous value

B. retains the same previous value

C. changes the input to complements.

D. retains the same input value.

12. Flip-flops whose output changes during positive transition of the clock are known as

_____________________

A. positive edge triggered flip-flop

B. negative edge triggered flip-flop

C. positive flip-flop

D. negative flipflop

13. A 2-bit ripple down counter counts from ______________________

A. 10→ 11 → 01 → 00 → 11.

B. 11→ 10 → 01 → 00 → 11.

C. 11→ 00 → 01 → 10 → 11.

D. 00→ 10 → 01 → 11 → 11.

14. Decade counter counts from ___________________

A. 0000 to 1111

B. 0001 to 1010

C. 1001 to 0000

D. 0000 to 1001

15. In synchronous counter, flip-flops are connected to a __________________

A. same clock signal

B. different clock signal

C. inputs and outputs of other flip-flops

D. All of the above.

16. If the sequence of states in a counter changes from an upper state to the lower state then it

is known as __________________

A. up-counter

B. down-counter

C. up/down counter

D. asynchronous counter.

17. Data is loaded into all stages of shift register at once in ______________________

A. a parallel-in/serial-out shift register

B. a serial-in/serial-out shift register

C. a serial-in/parallel-out shift register

D. Ring counter.

18. Which of the following shift registers delay data by one clock time for each stage?

A. Parallel-in, parallel-out

B. synchronous counter.

C. Serial-in, serial-out

D. Parallel-in, serial-out

19. Which converter accepts an n-bit binary word as input and generates a proportional analog

voltage or current output signal

A. A Digital to Analog Converter

B. A Analog to Digital Converter

C. Digital to digital converter

D. Analog to Digital converter.

20. Which of the following is programmed to perform a sequence of data transfers on behalf of

the CPU?

A. Registers

B. NIC

C. DMA controller

D. RDMA

21. Which of the following is a collection of logic circuits designed to perform arithmetic and

logical operations?

A. Control Unit

B. ALU

C. Registers

D. Memory

22. The CPU fetches an instruction in RAM to a register which is referred as a/an _____

A. Control Unit

B. Registers

C. Address bus

D. Instruction register

23. Which of the following register contains the instruction most recently fetched?

A. IR

B. MAR

C. PC

D. MBR

24. The result of ALU operations are reflected back in the register as _____

A. accumulator

B. flags

C. parity

D. AC

25. Which of the given register is used with devices to hold the information during transfers.

E. Memory

F. Buffer

G. CPU

H. Information

26. The PCI bus was developed by _____.

A. Sun Microsystems

B. IBM

C. Intel

D. Microsoft

27. _____ instructions are reserved for the use of operating system.

A. Addressing

B. Stack

C. Queue

D. System control

28. Programmers use organizations called _____ to represent the data used in computations.

A. Programs

B. Data structures

C. Addressing modes

D. Stacks

29. Booth algorithm is a powerful algorithm for _______________ multiplication.

A. Unsigned number

B. Signed number

C. Real number

D. Binary number

30. The mantissa is represented as a ___________integer.

A. sign bit

B. signed magnitude

C. unsigned

D. unsigned magnitude

31. Memory cycle time is usually ________ than the memory access time.

A. Higher

B. Same

C. Lower

D. None of these

32. A semiconductor memory constructed using MOS capacitor stores information in the form of

_________

A. Charge on a capacitor

B. Flip flop voltage levels

C. Electron Density

D. Electron Spin

33. Which of the following helps the programmer to find errors in the program?

A. Compiler

B. Assembler

C. Linker

D. Debugger

34. Which of the following are needed by the control unit to determine the status of the CPU and

outcome of previous ALU operations?

A. Flags

B. Instruction register

C. Control signals

D. Control bus

35. The major distinction between multiprocessors and multi–computers lies in __________.

A. CPU sharing

B. Memory sharing

C. Networking

D. USB

36. What happens when an instruction depends on the results of a previous instruction?

A. Structural hazards

B. Data hazards

C. Control hazards

D. Dependency Hazards

37. In a superscalar processor, ___________________are used.

A. multiple instruction pipelines

B. single instruction pipelines

C. double instruction pipelines

D. precoding

38. Which one of the given processors executes one instruction per cycle?

A. Vector processors

B. Scalar processors

C. Sequel Processors

D. Thread Processors

39. In a superscalar processor, ___________________are used.

A. multiple instruction pipelines

B. single instruction pipelines

C. double instruction pipelines

D. precoding

40. A Boolean vector can be used as a _______________ for enabling or disabling

component operations in a vector instruction.

A. Masking vector

B. Super vector

C. Control vector

D. Triggering vector

Part B (Two mark questions)

41. The octal value 65 (8) is equal to ____________in decimal and the decimal value 99 (10) is

equal to ______________in octal.

E. 65 (10) , 2 4 3 (8)

F. 53 (10) , 1 4 3 (8)

G. 56 (10) , 1 4 9 (8)

H. 22 (10) , 1 8 3 (8)

42. In Boolean algebra, _____________ baa

A. a + b

B. a

C. b

D. 1

43. Which of the following is/are NOT a Universal GATE.

1. AND Gate

2. NOT Gate

3. NOR Gate

4. NAND Gate.

A. 1 only

B. 2 only

C. Both 1 and 2

D. Both 3 and 4.

44. To simplify a six variable Boolean expression which of the method would be suitable for

simplifying it?

A. Boolean Algebraic method

B. K-map

C. Quine McClusky method

D. Hand computation

45. How many full adders will be required for 2 bit binary number addition

A. 1

B. 2

C. 3

D. 4

46. In JK flip-flop, When J = 1 and K = 1, the output ______________________

A. toggles between two states 0 and 1

B. remains same as before.

C. are compliments of input

D. is same as input.

47. How many flip-flops are required to realize mod-8 counter?

A. 1

B. 2

C. 3

D. 4

48. A 4 bit synchronous binary down-counter can be made from _______________

A) 1 Jk flip-flop

B) 2 Jk flip-flop

C) 3 Jk flip-flop

D) 4 Jk flip-flop

49. If the complement output of a ring counter is fed back to the input instead of the true output,

then it results in ________________________

A. a Johnson counter.

B. Ring counter

C. Serial-in, parallel-out shift register

D. parellel-in, parallel-out shift register

50. Which of the following is/are true?

1. CISC processors have larger instruction sets that often include some particular

complex instructions.

2. RISC processors opt for smaller instruction set with simpler instructions.

A. 1 only

B. 2 only

C. Both 1 and 2

D. None of the above

51. Which of the following are the responsibilities of Control Unit?

1. Instruction interpretation

2. Instruction sequencing

3. Instruction Splitting

A. 1, 2 only

B. 2, 3 only

C. 1, 3 only

D. All of the above

52. What are the different segments of Intel 8086 family?

A. stack segment, code segment, data segment

B. extra segment

C. index segment, stack segment, data segment

D. Both A) and B)

53. Which of the following is/are true?

1. The speed of parallel mode transmission is higher than serial mode transmission

2. The throughput of serial mode transmission is higher than parallel mode transmission.

A. 1 only

B. 2 only

C. Both 1 and 2

D. None of the above

54. In _____________________ operand is held in register named in address field where as in

_________________ operand is in memory cell pointed to by contents of register R.

A. Register Indirect Addressing mode, Displacement Addressing

mode

B. Register Addressing mode, Register Indirect Addressing mode

C. Indirect mode, Register Indirect Addressing mode

D. Displacement Addressing mode, Immediate Addressing mode

55. IF x=0001 and y=1111, then the binary subtraction of x and y will be________

A. 0010

B. 1010

C. 0001

D. 1001

56. Data transfer between the main memory and the CPU register takes place through which of

the following registers?

1. MBR

2. MAR

3. MDR

A. 1, 2 only

B. 2, 3 only

C. 1, 3 only

D. All of the above

57. What are the features of single bus detached DMA?

A. CPU is suspended twice

B. Each transfer uses bus twice

C. Separate I/O bus, CPU is suspended once

D. Both A) and B)

58. ___________ specifies address for read or write operation whereas ___________ holds

data to write or last data read.

A. Program counter, Memory Address Register

B. Memory Address Register, Memory Buffer register

C. Program counter, Instruction register

D. Memory Buffer register, Memory Address Register

59. Which of the following are different families of pipelined vector processors?

1. Memory–to–memory

2. Register–to–register

3. Memory to register

A. 1, 2 only

B. 2, 3 only

C. 1, 3 only

D. All the above

60. Which of the following is/are true?

1. CISC processors have larger instruction sets that often include some particular complex

instructions.

2. RISC processors opt for smaller instruction set with simpler instructions.

A. 1 only

B. 2 only

C. Both 1 and 2

D. None of the above

Part C (Four mark questions)

61. 10001(2) – 11101(2) = __________________

A. 01100(2)

B. 01110(2)

C. 01010(2)

D. 11110(2)

62. Which of the following are the correct statement for DeMorgan’s theorem ?

i. The complement of a product equals the sum of the complements.

ii. The complement of a sum equals the product of the complements

iii. The complement of a product equals the product of the complements

iv. The complement of a sum equals the sum of the complements

A. i and iv only

B. i, ii and iv only

C. i and ii only

D. i, ii, iii and iv

63. State True (T) or False (F).

i. Product of Sum (POS) expression is the ANDed representation of two or more OR functions

ii. The ORed terms in a POS form are known as maxterms.

iii. Sum of products (SOP) expression is two or more AND functions ORed together.

iv. The ANDed terms in a SOP form are known as minterms.

A. i-T, ii-F, iii-T, iv-F

B. i-F, ii-T, iii-F, iv-T

C. i-T, ii-T, iii-T, iv-T

D. i-F, ii-T, iii-T, iv-T

64. Which of the following statements are INCORRECT with respect to K-map and Quine-

McClusky Method?

i. Quine-McClusky method is more effective than K-mapif the number of Boolean variables

is more.

ii. Both K-map and Quine-McClusky method are used for simplification of logic expression

iii. K-map is suitable for simplifying logic expression if the number of variable is only 2

iv. Solution of logical expression with Quine McClusky method involves in the computation

of prime implicants, from which minimal sum should be selected.

A. Only i & ii

B. Only iii.

C. Only ii and iv

D. Only iv.

65. What does the Decimal to BCD encoder do?

A. It converts Decimal inputs to BCD outputs.

B. It converts BCD inputs to Decimal outputs.

C. It encodes decimal value to BCD value

D. Both a and c.

66. How can you make JK flip-flop into T flip-flop?

A) by connecting JK together in flip-flop and having J=K=0

B) by connecting JK together in flip-flop and having J=K=1

C) by connecting JK together to its output

D) by connecting output into clock signal

67. Why are ripple counters connected in cascade?.

A) to have increased modulus counter.

B) to have decreased modulus counter.

C) to increase the frequency of clock

D) to decrease the frequency of clock

68. State True (T) / False (F).

i. 32–bit data bus is used to write/read 16–bits of data to or from memory

ii. There are usually 3 kinds of buses

iii. A bus consists of only 1 wire

iv. Devices connected to the bus must share the bus

A. i–T, ii–T, iii–T, iv–T

B. i–T, ii–F, iii–T, iv–F

C. i–F, ii–F, iii–T, iv–T

D. i–F, ii–T, iii–F, iv–T

69. Identify, from the following, the tasks performed by CPU.

i. Compile instructions.

ii. Interpret instructions.

iii. Rewrite data

iv. Process data

A. ii and iv only

B. i, ii and iv only

C. ii, iii and iv only

D. i, ii, iii and iv

70. From the following options, identify the incorrect way of transferring information between

different modules of the system.

a. CPU to i/o

b. CPU to memory

c. Memory to processor

d. I/O to CPU

e. I/O to ALU

f. I/O to or from memory

A. Only a

B. Only e

C. Both a and b

D. Only f

71. Which of the following are data types provided by VAX machine?

1. Binary logical

2. Binary integer

3. Floating point

4. Character

A) 1, 2, 3 only

B) 2, 3, 4 only

C) 1, 3, 4 only

D) All the above

72. Which of the following statements are INCORRECT with respect to Booth’s multiplication

algorithm?

a. It is a powerful algorithm for signed number multiplication

b. It is used for performing unsigned integer division

c. It handles positive and negative numbers uniformly

d. It generates a 2n-bit product

e. It is efficient when there are long runs of ones in the multiplier

A. Only b & c

B. Only d.

C. Only c

D. Only b.

73. Which of the following are replacement algorithms in cache design?

1. LRU

2. FIFO

3. LFU

4. SJF

A) 1, 2, 3 only

B) 2, 3, 4 only

C) 1, 3, 4 only

D) All of the above

74. Which of the following statements are false with respect to memory mapped I/O.

a. No special commands for I/O

b. Devices and memory share an address space

c. I/O looks like memory read/write

d. Large selection of memory access commands available

e. Limited set

A) Only c

B) Only d

C) Only e

D) All a,b,c,d,e

75. Which of the following registers are involved in the fetch cycle?

1. MAR

2. MBR

3. PC

4. IR

A) 1, 2, 4 only

B) 2, 3, 4 only

C) 1, 3, 4 only

D) All 1,2,3,4

Answer Keys

Part - A Part - B Part - C

Q. No. Ans. Key

Q.

No. Ans. Key Q. No. Ans. Key Q. No. Ans. Key

1 A 21 B 41 B 61 A

2 B 22 D 42 A 62 C

3 A 23 A 43 C 63 C

4 B 24 B 44 C 64 B

5 D 25 B 45 B 65 D

6 B 26 C 46 A 66 B

7 C 27 D 47 C 67 A

8 C 28 B 48 D 68 D

9 C 29 B 49 A 69 A

10 C 30 B 50 C 70 B

11 B 31 C 51 A 71 B

12 A 32 A 52 D 72 D

13 D 33 D 53 A 73 A

14 D 34 C 54 B 74 C

15 A 35 A 55 A 75 D

16 B 36 A 56 B

17 A 37 B 57 D

18 C 38 B 58 B

19 A 39 A 59 B

20 C 40 A 60 C