Main Report

SMART ARMED ROBOT FOR MILITARY APPLICATION

A Project report Submitted in partial fulfillment of the requirements for the award of the

degree of

BACHELOR OF TECHNOLOGY

IN

ELECTRONICS AND COMMUNICATION ENGINEERING

BY

Batch No. : B14

M. SATYA NARAYANA 07G21A0482

SHAIK SEEMA 07G21A0483

B.REKHA RANI 07G21A0474

M.VENKATESULU 08G25A0408

Under the esteemed guidance of

Mr. K. Kishore,M.Tech.,

Assistant professor, Dept. of ECE,

ASCET.

DEPARTMENT OF

ELECTRONICS AND COMMUNICATION ENGINEERING

AUDISANKARA COLLEGE OF ENGINEERING AND TECHNOLOGY

(NBA Accredited Institution)

Approved by AICTE (Affiliated to JNTU-Anantapur)

NH-5, BYPASS ROAD, GUDUR-524101, SPSR NELLORE (Dt).

ANDHRA PRADESH

ASCET.ECE.dept 1

2007-2011

ABSTRACT

Out new Combat robot is pc operated , it has got two  barrel turret through bullet

can be fired, pc camera in synchronization with the turret can rotate up and down ,left and

right up to a safe firing limit. turret and camera mechanism has been installed on spy

robot vehicle, which has all the function like tank, Turing to any angle on its axis,

moving forward and reverse turning left and right, running instantly into reverse

direction.

This robot is radio operated and has all the controls like a normal car.  A gun and laser

module has been installed on it, so that it can fire on enemy remotely when required,this

is not possible until a wireless camera is installed.  Wireless camera will send real time

video and audio signals which could be seen on a remote monitor and action can be taken

accordingly.  It can silently enter into enemy area and send us all the information through

its’ tiny camera eyes. It is designed for, fighting as well as suicide attack.

The heart of the project is the AT89S52 microcontroller which will be used for

controlling the vehicle. Camera is used to visualize the path and surroundings. The aim is

to use the readily available material to construct low cost prototype. L293D is used as

motor drivers controlled by microcontroller. The RF transmitter and receiver is used for

wireless communication between robot and the user.

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INDEX

TITLE PAGE NO

Chapter 1: INTRODUCTION 6

1.1: Introduction to Embedded System 6

1.2: Characteristics 7

1.3: User Interface 8

Chapter 2: SCOPE OF THE PROJECT & PROPOSED APPROACH

2.1: Block Diagram 10

2.1.1: Block diagram of transmitter section 10

2.1.2: Block diagram of robot section 11

2.2: Schematic Diagram 13

2.3: Flow Chart 14

Chapter 3: HARDWARE DESCRIPTION

3.1: Hardware Components Used

3.2: Hardware Explanation

3.2.1: Power Supply

3.2.2: Microcontroller

3.2.3: RF Communication

3.2.4: Motor Driver

3.2.5: DC Motor

3.2.6: Gun & Laser Module

3.2.7: Camera

Chapter 4: WORKING

Chapter 5: SOFTWARE DESCRIPTION

5.1: Software

ASCET.ECE.dept 3

5.2: Source Code

Chapter 6: IMPLEMENTATION

Chapter 7: RESULT ANALYSIS

Chapter 8: CONCLUSION AND FUTURE SCOPE

ABBREVATIONS

BIBILIOGRAPHY

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LIST OF FIGURES PAGE NO

Block diagram of the project

Schematic diagram of the project

Flowchart of the project

Pin diagram of AT89S52

LIST OF TABLES PAGE NO

ASCET.ECE.dept 5

CHAPTER 1

INTRODUCTION

Being able to achieve reliable communication is an important open area of

research to robotics as well as other technology areas. As interest in robotics continuous

to grow, robots are increasingly being integrated in everyday life. The results of this

integration are end-users possessing less and less technical knowledge of the technology.

Here in this project we are going to use RF communication for remote accessing

of automated system. The main theme of this project is to create a smart robot for

military and surveillance purposes controlled using wireless communication. The

microcontroller we use in the project are AT89S52, at the robot. We use camera for

visualizing the path and identifying the surroundings and targets. For defending purpose

we use gun and laser to point out targets, which are mounted on the robot section.

1.1 Introduction to Embedded System

An embedded system is a computer system designed to perform one or a

few dedicated function often with real-time computing constraints. It is embedded as part

of a complete device often including hardware and mechanical parts. By contrast, a

general-purpose computer, such as a personal computer (PC), is designed to be flexible

and to meet a wide range of end-user needs. Embedded systems control many devices in

common use today.

Embedded systems are controlled by one or more main processing cores that

are typically either microcontrollers or digital signal processors (DSP). The key

characteristic, however, is being dedicated to handle a particular task, which may require

very powerful processors. For example, air traffic control systems may usefully be

viewed as embedded, even though they involve mainframe computers and dedicated

ASCET.ECE.dept 6

regional and national networks between airports and radar sites (each radar probably

includes one or more embedded systems of its own).

Since the embedded system is dedicated to specific tasks, design engineers

can optimize it to reduce the size and cost of the product and increase the reliability and

performance. Some embedded systems are mass-produced, benefiting from economies of

scale.

Physically, embedded systems range from portable devices such as digital

watches and MP3 players, to large stationary installations like traffic lights, factory

controllers, or the systems controlling nuclear power plants. Complexity varies from low,

with a single microcontroller chip, to very high with multiple units, peripherals and

networks mounted inside a large chassis or enclosure.

In general, "embedded system" is not a strictly definable term, as most

systems have some element of extensibility or programmability. For example, handheld

computers share some elements with embedded systems such as the operating systems

and microprocessors which power them, but they allow different applications to be

loaded and peripherals to be connected. Moreover, even systems which do not expose

programmability as a primary feature generally need to support software updates. On a

continuum from "general purpose" to "embedded", large application systems will have

subcomponents at most points even if the system as a whole is "designed to perform one

or a few dedicated functions", and is thus appropriate to call "embedded".

1.2 Characteristics

1. Embedded systems are designed to do some specific task, rather than be a general-

purpose computer for multiple tasks. Some also have real-time performance constraints

that must be met, for reasons such as safety and usability; others may have low or no

performance requirements, allowing the system hardware to be simplified to reduce costs.

2. Embedded systems are not always standalone devices. Many embedded systems

consist of small, computerized parts within a larger device that serves a more general

purpose. For example, the Gibson Robot Guitar features an embedded system for tuning

the strings, but the overall purpose of the Robot Guitar is, of course, to play music.[5]

Similarly, an embedded system in an automobile provides a specific function as a

subsystem of the car itself.

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3. The program instructions written for embedded systems are referred to as firmware,

and are stored in read-only memory or Flash memory chips. They run with limited

computer hardware resources: little memory, small or non-existent keyboard and/or

screen

1.3 User interface

Embedded system text user interface using Micro VGA

Embedded systems range from no user interface at all — dedicated only

to one task to complex graphical user interfaces that resemble modern computer desktop

operating systems. Simple embedded devices use buttons, LEDs, graphic or character

LCDs (for example popular HD44780 LCD) with a simple menu system.

More sophisticated devices use graphical screen with touch sensing or screen-edge

buttons provide flexibility while minimizing space used: the meaning of the buttons can

change with the screen, and selection involves the natural behavior of pointing at what's

desired. Handheld systems often have a screen with a "joystick button" for a pointing

device.

Some systems provide user interface remotely with the help of a serial (e.g. RS-

232, USB, I²C, etc.) or network (e.g. Ethernet) connection. In spite of the potentially

necessary proprietary client software and/or specialist cables that are needed, this

approach usually gives a lot of advantages: extends the capabilities of embedded system,

avoids the cost of a display, simplifies BSP, allows to build rich user interface on the PC.

A good example of this is the combination of an embedded web server running on an

embedded device (such as an IP camera) or a network routers. The user interface is

displayed in a web browser on a PC connected to the device, therefore needing no

bespoke software to be installed.

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Reliability

Embedded systems often reside in machines that are expected to run continuously

for years without errors, and in some cases recover by themselves if an error occurs.

Therefore the software is usually developed and tested more carefully than that for

personal computers, and unreliable mechanical moving parts such as disk drives,

switches or buttons are avoided.

Specific reliability issues may include

1.The system cannot safely be shut down for repair, or it is too inaccessible to repair.

Examples include space systems, undersea cables, navigational beacons, bore-hole

systems, and automobiles.

2.The system must be kept running for safety reasons. "Limp modes" are less tolerable.

Often backups are selected by an operator. Examples include aircraft navigation, reactor

control systems, safety-critical chemical factory controls, train signals, engines on single-

engine aircraft.

3.The system will lose large amounts of money when shut down: Telephone switches,

factory controls, bridge and elevator controls, funds transfer and market making,

automated sales and service.

A variety of techniques are used, sometimes in combination, to recover from errors

—both software bugs such as memory leaks, and also soft errors in the hardware:

•watchdog timer that resets the computer unless the software periodically notifies the

watchdog

•subsystems with redundant spares that can be switched over to

•software "limp modes" that provide partial function

•Designing with a Trusted Computing Base (TCB) architecture[6] ensures a highly secure

& reliable system environment

•An Embedded Hypervisor is able to provide secure encapsulation for any subsystem

component, so that a compromised software component cannot interfere with other

subsystems, or privileged-level system software. This encapsulation keeps faults from

propagating from one subsystem to another, improving reliability. This may also allow a

subsystem to be automatically shut down and restarted on fault detection.

•Immunity Aware Programming.

ASCET.ECE.dept 9

CHAPTER 2

SCOPE OF PROJECT AND PROPOSED APPROACH

2.1 BLOCK DIAGRAM OF TRANSMITTER SECTION

Fig2.1: Block diagram of transmitter section

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2.2 BLOCK DIAGRAM OF ROBOT SECTION

Fig 2.2: Block diagram of robot section

2.2.1 DESCRIPTION OF BLOCK DIAGRAM

2.2.1.1 Robot section:

2.2.1.1.1 Power supply:

This section is meant for supplying Power to all the sections and we supposed to

design 5v dc power supply. It basically consists of a Transformer to step down the 230V

ASCET.ECE.dept 11

ac to 12V ac followed by diodes. Here diodes are used to rectify the ac to dc. After

rectification the obtained rippled dc is filtered using a capacitor Filter. A positive voltage

regulator is used to regulate the obtained dc voltage of 12v.

2.2.1.1.2 Microcontroller:

The major heart of this project is AT89S52 microcontroller, the reasons

why we selected this in our project are: It is a high performance, low-power Atmel 8-bit

Microcontroller with 8Kbytes of In-System RAM 32 I/O lines, three 16-bit

timer/counters, a eight-vector two-level interrupt architecture, a full duplex serial port,

on-chip oscillator, and clock circuitry.

In addition, the AT89S52 is designed with static logic for operation down to zero

frequency and supports two software selectable power saving modes. The idle mode

stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system

to continue functioning. The power down mode saves the RAM contents but freezes the

oscillator, disabling all other chip functions until the next hardware reset. The flash

program memory supports both parallel programming and in serial In-System

Programming (ISP). The 89S52 is also In-Application Programmable (IAP), allowing the

Flash program memory to be reconfigured even while the application is running.

.

2.2.1.1..3 Motor Drivers:

L293D is a dual H-Bridge motor driver. So with one IC, two DC motors can be

interfaced which can be controlled in both clockwise and counter clockwise directions

and its direction of motion can also be fixed. The four I/O’s can be used to connect up to

four DC motors.

2.2.1.1..4 DC Motors:

Here, we use Five high efficiency, high quality, low cost DC motors with

gearbox for robotics applications. A motor consists of a rotor and a permanent magnetic

field stator. DC motors are most commonly used in variable speed and torque.

ASCET.ECE.dept 12

2.3 SCHEMATIC DIAGRAM

Fig 2.3: Schematic diagram of the project

2.4 FLOW CHART

ASCET.ECE.dept 13

CHAPTER 3

HARDWARE COMPONENT DESCRIPTION

3.1 HARDWARE COMPONENTS USED

Power supply

Microcontroller

RF communication

Motor driver

DC motor

Gun and laser module

Camera

3.2 HARDWARE EXPLANATION

3.2.1 POWER SUPPLY

3.2.1.1 Introduction

The power supplies are designed to convert high voltage AC mains

electricity to a suitable low voltage supply for electronic circuits and other devices. A

power supply can be broken down into a series of blocks, each of which performs a

particular function. A dc power supply which maintains the output voltage constant

irrespective of ac mains fluctuations or load variations is known as “Regulated D.C

Power Supply”.

For example a 5V regulated power supply system is shown below:

ASCET.ECE.dept 14

Figure 3.2.1 Components of a typical linear supply

3.2.1.2 Transformer:

A transformer is an electrical device which is used to convert electrical power

from one electrical circuit to another without change in frequency. Transformer converts

AC electricity from one voltage to another with little loss of power.

3.2.1.3 Rectifier:

A circuit which is used to convert a.c to d.c is known as Rectifier. The process of

conversion of a.c to d.c is called “Rectification”.

3.2.1.3.1 Bridge Rectifier:

A bridge rectifier makes use of four diodes in a bridge arrangement to achieve

full-wave rectification. This is a widely used configuration, both with individual diodes

wired and with single component bridges where the diode is wired internally.

3.2.1.4 Filter:

A filter is a device which removes the ac component of rectifier output but allows

the de component to reach the load.

3.2.1.5 Regulator:

Voltage regulator ICs are available with fixed (typically 5, 12 and 15V) or variable

output voltages. Many of the fixed voltage regulator ICs have 3 leads and look like power

transistors, such as the 7805 IC. The LM7805 is simple to use. We simply connect the

positive lead of our unregulated DC Power supply (anything from 9VDC to 24VDC) to

the Input pin, connect the negative lead to the Common pin and then when we turn on

the power, we get a 5 volt supply from the output pin.

3.2.2MICROCONTROLLER

Microcontroller is a true computer on a chip. The design incorporates all the

features found in a microprocessor CPU: arithmetic and logic unit, stack pointer, program

counter and registers. It was also added with some additional features like RAM, ROM,

serial I/O, counters and clock circuit. Like the microprocessor, a microcontroller is a

ASCET.ECE.dept 15

general purpose device, but one that is meant to read data, perform limited calculations

on that data and control its environment based those calculations.

The prime use of a microcontroller is to control the operation of a machine

using a fixed program that is stored in ROM and that does not change over the lifetime of

the system. The design approach of a microcontroller uses a more limited set of single

byte and double byte instructions that are used to move code and data from internal

memory to ALU. Many instructions are coupled with pins on the IC package; the pins are

capable of having several different functions depending on the wishes of the programmer.

The microcontroller is concerned with getting the data from and on to its own pins; the

architecture and instruction set are optimized to handle data in bit and byte size.

3.2.2.1INTRODUCTION TO MICROCONTROLLER (AT89S52):

The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller

with 8K bytes of in-system programmable Flash memory. The device is manufactured

using Atmel’s high-density non-volatile memory technology and is compatible with the

Industry standard 80C51 instruction set and pin out. The on-chip Flash allows the

program memory to be reprogrammed in-system or by a conventional non-volatile

memory programmer. By combining a versatile 8-bit CPU with in-system programmable

Flash on a monolithic chip, the Atmel’s AT89S52 is a powerful microcontroller which

provides a highly-flexible and cost-effective solution to many embedded control

application.

3.2.2.2FEATURES:

Compatible with MCS-51 Products

8K Bytes of In-System Programmable (ISP) Flash Memory – Endurance: 1000

write/Erase Cycles

4.0V to 5.5V Operating Range , Fully Static Operation: 0 Hz to 33 MHz

256 x 8-bit Internal RAM

32 Programmable I/O Lines

Three 16-bit Timer/Counters

Eight Interrupt Sources ,Three-level Program Memory Lock

ASCET.ECE.dept 16

Full Duplex UART (Universal Asynchronous Receiver Transmitter) Serial

Channel

Low-power Idle and Power-down Modes

Interrupt Recovery from Power-down Mode

Dual Data Pointer

Power-off Flag

Fast Programming Time

Flexible In System Programming (Byte and Page Mode)

3.2.2.3 PIN DIAGRAM:

Fig3.2.2.3: Pin Diagram of AT89S52

PIN DESCRIPTION: VCC: Supply voltage.

GND: ground

ASCET.ECE.dept 17

PORT 0:

Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin

can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as

high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order

address/data bus during accesses to external program and data memory. In this mode, P0

has internal pull-ups. Port 0 also receives the code bytes during Flash programming and

outputs the code bytes during program verification. External pull-ups are required during

program verification.

PORT 1:

Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output

buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are

pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that

are externally being pulled low will source current (IIL) because of the internal pull-ups.

In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count

input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown

in the following table

PORT PIN ALTERNATE FUNCTIONS

P1.0 T2 (external count input to Timer/Counter 2), clock-out

P1.1 T2EX (Timer/Counter 2 capture/reload trigger and

direction control)

P1.5 MOSI (used for In-System Programming)

P1.6 MISO (used for In-System Programming)

P1.7 SCK (used for In-System Programming)

PORT 2:

Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output

buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are

pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that

are externally being pulled low will source current (IIL) because of the internal pull-ups.

Port 2 emits the high-order address byte during fetches from external program memory

and during accesses to external data memory that uses 16-bit addresses (MOVX @

ASCET.ECE.dept 18

DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During

accesses to external data memories that use 8-bit addresses (MOVX @ RI), Port 2 emits

the contents of the P2 Special Function Register. Port 2 also receives the high-order

address bits and some control signals during Flash programming

PORT 3:

Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3

output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they

are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins

that are externally being pulled low will source current (IIL) because of the pull-ups. Port

3 receives some control signals for Flash programming and verification. Port 3 also

serves the functions of various special features of the AT89S52, as shown in the

following table

P3.0 – RXD (serial input port)

P3.1 - TXD (serial output port)

P3.2 – INT0 (external interrupt 0)

P3.3 – INT1 (external interrupt 1)

P3.4 – T0 (timer 0 external input)

P3.5 – T1 (timer 1 external input)

P3.6 – WR (external data memory write strobe)

P3.7 – RD (external data memory read strobe)

Port 3 also receives some control signals for Flash programming and verification.

RST: Reset input.

A high on this pin for two machine cycles while the oscillator is running resets

the device. This pin drives high for 96 oscillator periods after the watch dog times out.

ALE/PROG:

Address Latch Enable is an output pulse for latching the low byte of the

address during accesses to external memory. This pin is also the program pulse input

(PROG) during programming.

In normal operation, ALE is emitted at a constant rate of 1/6th the

oscillator frequency and may be used for external timing or clocking purposes. Note,

ASCET.ECE.dept 19

however, that one ALE pulse is skipped during each access to external data memory. If

desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit

set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is

weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in

external execution mode.

PSEN:

Program Store Enable is the read strobe to external program memory. When

the AT89S52 is executing code from external program memory, PSEN is activated twice

each machine cycle, except that two PSEN activations are skipped during each access to

external data memory.

EA/VPP:

External Access Enable. EA must be strapped to GND in order to enable the

device to fetch code from external program memory locations starting at 0000H up to

FFFFH. However that if lock bit 1 is programmed, EA will be internally latched on reset.

EA should be strapped to VCC for internal program executions. This pin also then

receives 12-volt programming enable voltage (VPP) during Flash programming when 12-

volt Programming is selected.

XTAL1:

Input to the inverting oscillator amplifier and input to the internal clock

operating circuit.

XTAL2:

Output from the inverting oscillator amplifier.

3.2.2.4BLOCK DIAGRAM:

The AT89S52 is designed with static logic for operation down to zero

frequency and supports two software selectable power saving modes. The Idle Mode

stops the CPU while allowing the RAM; timer/counters, serial port, and interrupt system

to continue functioning. The Power-down mode saves the RAM contents but freezes the

oscillator disabling all other chip functions until the next hardware reset.

ASCET.ECE.dept 20

SPECIAL FUNCTION REGISTERS:

The AT89S52 operations that do not use the internal 256-byte RAM

addresses from 00h to 7fh are done by a group of specific internal registers, each called a

special function register (SFR), which may be addressed much like internal RAM, using

addresses from 80h to ffh. Some SFR’s are also bit addressable, as is the case for the bit

area of RAM. This feature allows the programmer to change only what needs to be

altered, leaving the remaining bits in that SFR unchanged. Not all of the addresses from

80h to ffh are used for SFR’s, and attempting to use an address that is not defined or

empty results in unpredictable results. PC is not part of the SFR and has no internal RAM

address. The names of the SFR’s and their functions are given in the following list.

ASCET.ECE.dept 21

Fig3.2.2.4: Block diagram of AT89s52

ASCET.ECE.dept 22

3.2.2.5LIST OF SPECIAL FUNCTION REGISTERS:

Name Function

A Accumulator

B Arithmetic

DPH addressing external memory

DPL addressing external memory

IE Interrupt enables control

IP Interrupt priority

P0 Input/output port latch

P1 Input/output port latch

P2 Input/output port latch

P3 Input/output port latch

PCON Power control

PSW Program status word

SCON Serial port control

SBUF Serial port data buffer

SP Stack pointer

TMOD Timer/counter mode control

TCON Timer/counter control

TL0 Timer 0 low byte

TH0 Timer 0 high byte

TL1 Timer 1 low byte

TH1 Timer 1 high byte

3.2.2.6INTERRUPTS:

A computer program has only two ways to determine the condition that exist

in Internal and external circuits. One method uses software instructions that jump to

Subroutines on the states of flags and port pins. The second method responds to hardware

Signals, called interrupts that force the program to call a subroutine. Software techniques

use processor time that could be devoted to other tasks, interrupts take processor time

only when action by the program is needed. Most applications of microcontrollers

involve responding to events quickly enough to control the environment that generates

ASCET.ECE.dept 23

the events. Interrupts are often the only way in which real time programming can be done

successfully.

Interrupts may be generated by internal chip operations or provided by

external Sources. Any interrupt can cause the microcontroller to perform a hardware call

to an Interrupt handling sub-routine that is located at a predetermine absolute address in

Program memory.8 interrupts are provided in 89s52.Three of these are generated

automatically by internal operations: timer flag 0, timer flag1 and the serial port.

The AT89S52 has a total of six interrupt vectors: two external interrupts (INT0 and

INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. Each of

these interrupt sources can be individually enabled or disabled by setting or clearing a bit

in Special Function Register IE. IE also contains a global disable bit, EA, which disables

all interrupts at once.

All interrupt functions are under the control of the program. The

programmer is able to alter the control bits in the Interrupt Enable register (IE), the

Interrupt Priority register (IP), and the Timer Control register (TCON). The program can

block all or any combination of the interrupts from acting on the program by suitably

setting or clearing bits in these registers.

After the interrupt has been handled by the interrupt subroutine, which is

placed by the programmer at the interrupt location in the program memory, the

interrupted program must resume operation at the instruction where the interrupt took

place. Program resumption is done by storing the interrupted PC address on the stack in

RAM before changing the PC to the interrupt address in ROM. The PC address will be

restored from the stack after an RET1 instruction is executed at the end of the interrupt

subroutine.

Timer flag interrupt:

When a timer /counter overflows the corresponding timer flag TF0 or TF1 is

set to 1. The flag is cleared to 0 when the resulting interrupt generates a program call to

the appropriate timer subroutine in memory.

Serial port interrupt:

If a data byte is received, an interrupt bit. RI is set to 1 in the SCON register.

When a data byte has been transmitted an interrupt bit, T1, is set in SCON. These are

ASCET.ECE.dept 24

ORed together to provide a single interrupt to the processor which is the serial port

interrupt. These bits are not cleared when the interrupt generated program call is made by

the processor. The program that handles serial data communication must reset R1 or T1

to 0 to enable the next data communication operation.

External interrupts:

Pins INT0 and INT1 are used by external circuitry. Inputs on these pins can

set the interrupt flags IE0 and IE1 in the TCON register to 1 by two different methods.

The IEX flags may be set when the INTX pin signal reaches a low level, or the flags may

be set when a high to low transition takes place on the INTX pin. Bits IT0 and IT1 in

TCON program the INTX pins for low level interrupt when set to 0 and program the

INTX pins for transition interrupt when set to 1.

Flags IEX will be reset when a transition generated interrupt is accepted by the

processor and the interrupt subroutine is accessed. It is the responsibility of the system

designer and programmer to reset any level generated external interrupts when they are

serviced by the program. The external circuit must remove the low level before an RET1

is executed. Failure to remove the low will result in an immediate interrupt after RET1,

from the same source.

RESET:

A reset can be considered to be the ultimate interrupt because the program

may not block the action of the voltage on the RST pin. This type of interrupt is often

called non-makeable, because no combination of bits in any register can stop, or mask,

the reset action. Unlike other interrupts, the PC is not stored for later program

resumption. A reset is an absolute command to jump to program address 0000h and

commence running from there. Whenever a high level is applied to the RST pin, the

micro controller enters a reset condition. Internal RAM contents may change during reset.

Also the states of the internal RAM bytes when power is first applied to micro controller

are random. Register bank-0 is selected on reset as all bits in PSW are 0.

INTERRUPT CONTROL:

The program must be able, at critical times, to inhibit the action of some or

all of the interrupts so that critical operations can be finished. The IE register holds the

ASCET.ECE.dept 25

programmable bits that can enable or disable all the interrupts as a group, or if the group

is enabled, each individual interrupt source can be enabled or disabled.

It is desirable to be able to set priorities among competing interrupts that

may conceivably occur simultaneously. The IP register bits may be set by the program to

assign the priorities among various interrupt sources so that more important interrupts can

be serviced first should be two or more interrupts occur at the same time.

INTERRUPT ENABLE/DISABLE:

Bits in the IE register are set to 1 if the corresponding interrupt source is to

be enabled and set to 0 to disable the interrupt source. Bit EA is the master, or global bit

that can enable or disable all the interrupts.

INTERRUPT PRIORITY:

Register IP bits determine if any interrupt is to have a high or low priority.

Bits set to 1 give the accompanying interrupt a high priority; 0 assigns a low priority.

Interrupts with a high priority can interrupt another interrupt with a low priority. The low

priority interrupt continues after the higher is finished.

SOFTWARE GENERATED INTERRUPTS:

When any interrupt flag is set to 1 by any means, an interrupt is generated

unless blocked. This means that the program itself can cause interrupts of any kind to be

generated simply by setting the desired interrupt flag to 1using a program instruction

PROGRAM COUNTER AND DATA POINTER:

The AT89S52 contains two 16-bit registers, the program counter (PC) and

the data pointer (DPTR). Each is used to hold the address of a byte in memory. Program

instructions bytes are fetched from locations in memory that are addressed by the PC.

Program ROM may be on the chip at addresses 0000h to 0FFFh, external to the chip for

addresses that exceed 0FFFh, or totally external for all addresses from 0000h to FFFFh.

The PC is automatically incremented after every instruction byte is fetched and may also

be altered by certain instructions. The PC is the only register that does not have an

internal address.

The DPTR register is made up of two 8-bit registers, named DPH and

DPL, which are used to furnish memory addresses for internal and external code access

and external data access. The DPTR is under the control of program instructions and can

ASCET.ECE.dept 26

be specified by its 16-bit name, DPTR, or by each individual byte name, DPH and DPL.

DPTR does not have a single internal address; DPH and DPL are each assigned an

address.

A AND B CPU REGISTERS:

AT89S52 contains 34 general purpose, or working registers. Two of these

registers A and B, hold results of many instructions, particularly math and logical

operations, of the 8052 central processing unit. The other 32 are arranged as part of

internal RAM in four banks, B-0 to B-3 of 8 registers and comprise the mathematical

core.

The A (accumulator) register is the most versatile of the two CPU registers

and is used for many operations, including addition, subtraction, integer multiplication

and division, and Boolean bit manipulations. The A register is also used for all data

transfers between the 8052 and any external memory. The B register is used with the A

register for multiplication and division operations and has no other function other than as

a location where data may be stored.

FLAGS AND THE PROGRAM STATUS WORD (PSW):

Flags are 1-bit registers provided to store the results of certain program

instructions. Other instructions can test the condition of the flags and make decisions

based on the flag states. In order that the flags may be conveniently addresses, they are

grouped inside the program status word (PSW) and the power control (PCON) registers.

The AT89S52 has 4 math flags that respond automatically to the outcomes of math

operations and 3 general purpose user flags that can be set to 1 or cleared to 0 by the

programmer as desired. The math flags include carry (C), auxiliary carry (AC), overflow

(OV) and parity (P). User flags are named F0, GF0 and GF1. They are general purpose

flags that may be used by the programmer to record some event in the program. However

math flags are also affected by the math operations.

The PSW contains the math flags, user program flag(F0) and the register

select bits that identify which of the four general purpose register banks is currently used

by the program. The remaining 2 user flags, GF0 and GF1 are stored in PCON.

ASCET.ECE.dept 27

INTERNAL RAM AND ROM:

The 256 byte internal RAM is organized into 3 distinct areas. 32 bytes from

00h to 1Fh that make up 32 working registers are organized as 4 banks of 8 registers

each. The 4 register banks are numbered 0 to 3 and are made up of 8 registers R0 to R7.

Each register can be addressed by the name of the bank or by its RAM address. Thus R0

of bank-3 is R0 (if bank-3 is currently selected) or address 18h (whether bank-3 is

selected or not). Bits RS0 and RS1 in the PSW determine which bank of registers is

currently in use at any time when the program is running. Register banks not selected can

be used as general purpose RAM. Bank-0 is selected on reset.

A bit addressable area of 16 bytes occupies RAM byte addresses 20h to

2Fh, forming a total of 128 addressable bits. An addressable bit may be specified by its

bit address of 00h to 7Fh, or 8 bits may form any byte address from 20h to 2Fh.

Addressable bits are useful when the program need only remember a binary event.

The AT89S52 is organized so that data memory and program core

memory can be in two entirely different physical memory entities. Each has the same

address ranges. The corresponding block of internal program code, contained in an

internal ROM, occupies code address space 0000h to 0FFFh. The PC is ordinarily used to

address program code bytes from addresses 0000h to FFFFh. Program addresses higher

than 0FFFh, which exceed the internal ROM capacity, will cause the micro controller to

automatically fetch program code bytes from external program memory. The PC does not

care where the code is, whether it is in internal ROM totally or totally in external ROM or

in a combination of internal and external ROM.

STACK AND STACK POINTER:

The stack refers to an area of internal RAM that is used in conjunction

with certain opcodes to store and retrieve data quickly. The 8 bit stack pointer (SP)

register is used by the micro controller to hold an internal RAM address that is called the

top of the stack. The address held in the SP register is the location in the internal RAM

with the last byte of data was stored by the stack operation.

When data is to be placed on the stack, the SP increments before storing data on the stack

so that the stack grows up as the data is stored. As the data is retrieved from the stack the

ASCET.ECE.dept 28

byte is read from the stack, and then the SP decrements to point to the next available byte

of stored data.

The SP is set to 07h when the micro controller is reset and can be changed

to any internal RAM address by the programmer, using a data move command. The stack

is normally placed high in internal RAM, by an appropriate choice of the number placed

in SP register, to avoid conflict with the register, bit and scratch pad internal RAM areas.

Fig3.2.2.6: Oscillator connections

The heart of the AT89S52 is the circuitry that generates the clock pulses by

which all internal operations are synchronized. Pins XTAL1 and XTAL2 are provided for

connecting a resonant network to form an oscillator typically a quartz crystal and

capacitors are employed. The crystal frequency is the basic internal clock frequency of

the micro controller. The manufacturers make available 8052 designs that can run at

specified maximum and minimum frequencies, typically 1MHz to 16MHz. Minimum

ASCET.ECE.dept 29

frequencies imply that some internal memories are dynamic and must always operate

above a minimum frequency or data will be lost.

Serial data communication needs often dictate the frequency of the

oscillator because of the requirement that internal counters must divide the basic clock

rate to yield standard communication bit per second (baud) rates.

Ceramic resonators may be used as a low cost alternative to crystal

resonators. However, decreases in frequency stability and accuracy make the ceramic

resonator a poor choice if high speed serial data communication with other systems, or

critical timing, is to be done. The oscillator formed by the crystal, capacitors and an on-

chip inverter generates a pulse train at the frequency of the crystal.

The clock frequency establishes the smallest interval of time within the

micro controller called the pulse time. The smallest interval of time to accomplish any

simple instruction, or part of a complex instruction, is the machine cycle. The machine

cycle is itself made up of 6 states. A state is the basic time interval for discrete operations

of the micro controller such as fetching an opcode byte, decoding an opcode, executing

an opcode, or writing a data byte. Two oscillator pulses define each state.

Program instructions may require one, two or four machine cycles to be

executed, depending on the type of instruction. Instructions are fetched and executed by

the micro controller automatically beginning with the instruction located at ROM

memory address 0000h at the time the micro controller is first reset.

3.2..2.7MODES OF OPERATION:

IDLE MODE:

In idle mode, the CPU puts itself to sleep while all the on chip peripherals

remain active. The mode is invoked by software. The content of the on-chip RAM and all

the special functions registers remain unchanged during this mode. The idle mode can be

terminated by any enabled interrupt or by a hardware reset. When idle mode is terminated

by a hardware reset, the device normally resumes program execution from where it left

off, up to two machine cycles before the internal reset algorithm takes control.

On-chip hardware inhibits access to internal RAM in this event, but

access to the port pins is not inhibited. To eliminate the possibility of an unexpected write

ASCET.ECE.dept 30

to a port pin when idle mode is terminated by a reset, the instruction following the one

that invokes idle mode should not write to a port pin or to external memory.

POWER-DOWN MODE:

In the power-down mode, the oscillator is stopped, and the instruction

that invokes power-down is the last instruction executed. The on-chip RAM and Special

Function Registers retain their values until the power-down mode is terminated. The only

exit from power-down is a hardware reset. Reset redefines the SFRs but does not change

the on-chip RAM. The reset should not be activated before VCC is restored to its normal

operating level and must be held active long enough to allow the oscillator to restart and

stabilize.

3.2.2.8ADDRESSING MODES:

The CPU can access data in various ways. The data could be in a register

or in memory or to be provided as an immediate value. The various ways of accessing

data are called addressing modes.

The various ways of the addressing modes of a microprocessor are determined when

designed and therefore can’t be changed by the programmer. The 89S52 provides a total

of 5 addressing modes. They are as follows:

1. Immediate addressing mode:

In this addressing mode the source operand is a constant. In this mode the

operand comes immediately after the opcode. The immediate data must be preceded by

“#” sign. This mode can be used to load information into any of the registers.

Ex. Mov ro, #5h

2. Register addressing mode:

This mode involves the use of the registers to hold the data to be

executed. It should be noted that the source and the destination registers must match in

size. We can move data between register and accumulator but movement of data between

registers is not possible.

3. Direct addressing mode:

ASCET.ECE.dept 31

In this mode the data is in a RAM memory location whose address is

known and this address is given as a part of the instruction. We can use direct or indirect

addressing modes to access data stored either in the RAM or registers of the 89S52.

4. Register indirect addressing mode:

In this addressing mode a register is used as a pointer to the data. If the data

is inside the CPU, only the registers R0 and R1 are used for the purpose. In other words

R2-R7 cannot be used to hold the address of an operand located in RAM.

5. Indexed addressing mode:

This mode is widely used in accessing the data elements of lookup table

entries located in the programmed ROM space of the 89S52.The instruction used for this

purpose is “MOVC A, @A+DPTR”. The DPTR and the register A are used to form the

address of data element stored on the on-chip memory.

Absolute Maximum Ratings:

Operating temperature : -55 oC to +125 o C

Storage temperature : -65 oC to +150 oC

Voltage on any pin with respect to ground : -1.0V to +7.0V

Maximum operating voltage : 6.6V

DC output current : 15.0mA

Stresses beyond the absolute maximum ratings may cause permanent

damage to the device. Exposure to absolute maximum rating conditions for extended

periods may affect device reliability.

3.2.3 RF communication

ASCET.ECE.dept 32

The TWS-434 and RWS-434 are extremely small, and are excellent for applications

requiring short-range RF remote controls. The transmitter module is only 1/3 the size of

a standard postage stamp, and can easily be placed inside a small plastic enclosure.

TWS-434:

The transmitter output is up to 8mW at 433.92MHz with a range of

approximately 400 foot (open area) outdoors. Indoors, the range is approximately 200

foot, and will go through most walls.

The TWS-434 transmitter accepts both linear and digital inputs, can operate

from 1.5 to 12 Volts-DC, and makes building a miniature hand-held RF transmitter very

easy. The TWS-434 is approximately the size of a standard postage stamp.

ASCET.ECE.dept 33

Fig3.2.3: Sample Transmitter Application Circuit

RWS-434: The receiver also operates at 433.92MHz, and has a sensitivity of 3uV.

The RWS-434 receiver operates from 4.5 to 5.5 volts-DC, and has both linear and digital

outputs.

ASCET.ECE.dept 34

3.2.3.1 Remote Control Section

The circuit uses HT 640, HT 648 encoder and decoder. 433MHz ASK

transmitter and receiver is used for the remote control. H-bridge circuits are used for

driving motors. Two 12V DC/150RPM gear motors are used as drivers. The working of

the circuit is as follows.

When we are pressing any key in remote controller the HT 640 generate 8 bit

address and 4 bit data .The DIP switches are used for setting the address. Then the ASK

transmitter sends the 8 bit address and 4 bit data to the receiver Then the ASK receiver

receives the 8 bit address and 4 bit data and HT 648 decoder decodes the data, thus

enabling the appropriate output. Thus the output signals that are generated controls the H-

bridge which then rotates the motors.

ASCET.ECE.dept 35

The 433 MHZ ASK transmitter and receivers are extremely small, and are

excellent for applications requiring short-range RF remote controls. The transmitter

module is only 1/3rd the size of a standard postage stamp, and can easily be placed inside

a small plastic enclosure. The transmitter output is up to 8mW at 433.92MHz. The

transmitter accepts both linear and digital inputs and can operate from 1.5 to 12 Volts-

DC, and makes building a miniature hand-held RF transmitter very easy. The 433 MHZ

ASK transmitters is approximately the size of a standard postage stamp 433 MHZ ASK

receivers also operate at 433.92MHz, and have a sensitivity of 3uV. The receiver

operates from 4.5 to 5.5 volts-DC.

Fig3.2.3.1: Construction of RF operated robot

ASCET.ECE.dept 36

1. Take a hylam sheet with (20cm*15cm) size.

2. Fix two gear motors (12VDC 100rpm) in the hylam sheet by using aluminum pieces

and nut bolts as shown in the figure below.

3. Fix the ball castor as shown in the figure below.

4. Then fix the battery (9VDC 1.2Ah) on the top of the spy robot as shown in the figure

above.

5. Connect two motors to the PCB. The PCB is then connected to the battery.

6. Connect the wireless transmitter HT640 to the battery.

7. Connect the receiver to the robot or computer.

8. Switch on the remote controller and control the metal detector robot.

ASCET.ECE.dept 37

3.2.4 MOTOR DRIVER:

3.2.4.1 Introduction to Motor drivers:For construction of any robot, the important mechanical constraint is the number

of motors we are going to use. One can either two wheel drive or a four wheel drive. Four

wheel drive even though is complex than two wheel drive will provide more torque and

good control. Two wheel drive is very easy to construct.

3.2.4.2 L293D:

L293D is a dual H-Bridge motor driver. So with one IC, two DC motors can be

interfaced which can be controlled in both clockwise and counter clockwise directions

and its direction of motion can also be fixed. The four I/O’s can be used to connect up to

four DC motors. L293D has output current of 600mA and peak output current of 1.2A

per channel. Moreover for the protection of the circuit from back EMF, output diodes are

included within the IC. The output supply (VCC2) has a wide range from 4.5V to 36V,

which has made L293D a best choice for DC motor driver. The name "H-Bridge" is

derived from the actual shape of the switching circuit which controls the motion of the

motor. It is also known as "Full Bridge".

The L293 is an integrated circuit motor driver that can be used for simultaneous,

bi-directional control of two small motors. The L293 is limited to 600 mA, but in reality

can only handle much small currents unless we have done some serious heat sinking to

keep the case temperature down. If we are unsure about whether the L293 will work with

our motor, then we have to hook up the circuit and run our motor while keeping our

finger on the chip. If it gets too hot to touch, we can't use it with our motor.

The L293 comes in a standard 16-pin, dual-in line integrated circuit package.

There is an L293 and an L293D part number. We have picked the "D" version because it

has built in fly-back diodes to minimize inductive voltage spikes.

The pin out for the L293 in the 16-pin package is shown below in top view. Pin 1

is at the top left when the notch in the package faces up.

ASCET.ECE.dept 38

Figure 3.2.4.2(a): Pin Diagram of L293D Motor Driver

Figure 3.2.4.2(b): Connection Diagram of L293D Motor Driver

ASCET.ECE.dept 39

The following schematic shows how to connect the L293 to our motor and the

Stamp. Each motor takes 3 Stamp pins. If we are using only one motor, then we leave

pins 9, 10, 11, 12, 13, 14, and 15 empty.

Figure 3.2.4.2(c): Schematic of L293D Connection

Assume we have only one motor connected with the enable tied to Stamp Pin 0,

and the two direction controls tied to Stamp Pins 1 and 2.

Here is a table describing the control pin functions.

ENABLE DIRA DIRB Function

H H L Turn right

H L H Turn left

H L/H L/H Fast stop

L Either either Slow stop

Table 3.2.4.2(d): Describing control pin functions

ASCET.ECE.dept 40

3.2.4.3 H-Bridge:

Figure 4.4.2.1: H-Bridge operation

The H-Bridge consists of a four PNP transistors such as Q1, Q2, Q3 and Q4.

These transistors are arranged in a way that a DC motor M can rotate. A and B are

represented as two inputs for operating a motor through the transistors. For the circuit

operation, we are providing +12V DC as a VCC. The operation will be explained as

follows:

The inputs A and B can be applied as a either logic ‘0’ or logic ‘1’ i.e., may be

either 5V DC voltage or Ground. If the input A =logic ‘0’ and B=logic’1’ then

transistors Q1 and Q4 will be ‘ON’ state and Q2 and Q3 will be ‘OFF’ state. The current

flows from Q1 to Q4 so that the motor M can rotate in clockwise direction.

If the input A =logic ‘1’ and B=logic’0’ then transistors Q1 and Q4 will be ‘OFF’

state and Q2 and Q3 will be ‘ON’ state. The current flows from Q1 to Q4 so that the

motor M can rotate in Anti-clockwise direction.

If the input A =logic ‘1’ and B=logic’1’ then transistors Q1 and Q4 will be ‘OFF’

state and Q2 and Q3 will be ‘OFF’ state. No current flows from in the circuit. The circuit

will be in hold condition. The motor will not rotate any direction. So, there is no wastage

of power will occur. Otherwise, if both inputs are low that is all transistors are come

under working and more current will flows in the circuit. But the motor will be at hold

condition. More power is wasted.

ASCET.ECE.dept 41

By using two motors the robot can be moved in any direction. This steering

mechanism of the robot is called differential drive.

Left Motor Right Motor Robot Movement

Straight Straight Straight

Stop Straight LeftReverse Straight Sharp LeftStraight Stop RightStraight Reverse Sharp RightReverse Reverse Reverse

Table 4.2.4.1: Robot movement.

3.2.5 DC GEARED MOTOR:

In this project, we use four high efficiency, high quality, low cost DC motors with

gearbox for robotics applications. DC motors are configured in many types and sizes,

including brush less, servo and gear motor types. A motor consists of a rotor and a

permanent magnetic field stator. The magnetic field is maintained using either permanent

magnets or electromagnetic windings. DC motors are most commonly used in variable

speed,torque.

They are very easy to use and available in standard size. They have nuts and

threads on shaft to easily connect and internal threaded shaft for easily connecting it to

wheel.

3.2.5.1 Features: 45 RPM 12V DC motors with Gearbox

5kgcm torque

3000RPM base motor

6mm shaft diameter with internal hole

125gm weight

Same size motor available in various rpm

No-load current = 60 mA(Max), Load current = 300 mA(Max)

ASCET.ECE.dept 42

Figure 4.5: DC Geared Motor

3.2.6 Gun and laser module

A laser module is mounted on the robot along with a gun so that it is easier to

aim at the target by seeing through the monitor which is visible by using camera. Gun is

used in order to fire at the suspected target and is used for defending purpose. Hence gun

and laser module together follows a defending module which is used for defence.

3.2.7 Camera:

A gun and laser module has been installed on it, so that it can fire on enemy

remotely when required,this is not possible until a wireless camera is installed.  Wireless

camera will send real time video and audio signals which could be seen on a remote

monitor and action can be taken accordingly.  It can silently enter into enemy area and

send us all the information through its’ tiny camera eyes. It is designed for, fighting as

well as suicide attack.

ASCET.ECE.dept 43

CHAPTER 4

WORKING

In the first step the robot section is initialized by giving power supply, where It

basically consists of a transformer to step down the 230V ac to 5V/12V ac. The

rectifier converts ac to dc and the regulator eliminates ripple by setting DC output to a

fixed voltage. The operating voltage of microcontroller, DTMF receiver, ULN2003 is

5V and for motor is 12V.

In second step the transmitter section and camera section is supplied by 9V DC

power supply by using battery.

In third step the robot section has given commands by using switches in

transmitter section, where corresponding action is done accordingly to the predefined

instructions dumped in the microcontroller, by pressing a particular switch in the

transmitter section remote accordingly particular action is done by microcontroller by

commanding respective devices which are connected to it according to the dumped

code and as a result respective action is shown by robot section

By watching through monitor we can control the robot through remote this is

possible unless a wireless camera is mounted. the camera here we used will send audio

and video signals to us, so that we can easily visualize the path and identifying the

surroundings and targets.

By using laser module we can easily aim the target by visualize through

camera and can fire on the target by using gun.

ASCET.ECE.dept 44

CHAPTER 5

SOFTWARE DESCRIPTION

5.1Software

5.2 Source code

CHAPTER 6

IMPLEMENTATION

CHAPTER 7

RESULT ANALYSIS

CHAPTER 8

CONCLUSION AND FUTURE SCOPE

CONCLUSION:

The project “SMART ARMED ROBOT FOR MILITARY APPLICATION” has

been successfully designed and tested. Integrating features of all the hardware

components used have developed it. Presence of every module has been reasoned out and

placed carefully thus contributing to the best working of the unit. Secondly, using highly

advanced IC’s and with the help of growing technology the project has been successfully

implemented. With regards to the requirements gathered the manual work and the

complexity in having manual surveillance and security in all desirable places can be

achieved with the help of electronic devices without having primary human loss in case

of defense.

FUTURE SCOPE:

• By having Artificial Neural Networks.

• Robot Ants, James McLurkin invented Micro Robots that work together as a

Community.

• By having Image Processing in order to detect suspected targets automatically.

ASCET.ECE.dept 45

BIBILIOGRAPHY

REFERENCES

1. "The 8051 Microcontroller Architecture, Programming & Applications"

-- by Kenneth J Ayala.

2. "The 8051 Microcontroller & Embedded Systems"

-- by Mohammed Ali Mazidi & Janice Gillispie Mazidi.

3. "Power Electronics”

-- by M.D. Singh and K.B. Khanchandan.

4. "Linear Integrated Circuits”

-- by D. Roy Choudary & Shail Jain.

5. "Electrical Machines”

-- by S K Bhattacharya.

WEB SITES

1. WWW.MITEL.DATABOOK.COM

2. WWW.ATMEL.DATABOOK.COM

3. WWW.FRANKLIN.COM

4. WWW.KEIL.COM

ASCET.ECE.dept 46