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    LTC1871

    Wide Input Range, No RSENSETM

    Current Mode Boost, Flyback and SEPIC Controller

    The LTC®1871 is a wide input range, current mode, boost,flyback and SEPIC controller that drives an N-channelpower MOSFET and requires very few external compo-nents. Intended for low to medium power applications, iteliminates the need for a current sense resistor by utiliz-ing the power MOSFET’s on-resistance, thereby maximiz-ing efficiency.

    The IC’s operating frequency can be set with an externalresistor over a 50kHz to 1MHz range, and can be synchro-nized to an external clock using the MODE/SYNC pin.Burst Mode operation at light loads, a low minimumoperating supply voltage of 2.5V and a low shutdownquiescent current of 10µA make the LTC1871 ideallysuited for battery-operated systems.

    For applications requiring constant frequency operation,Burst Mode operation can be defeated using the MODE/ SYNC pin. Higher output voltage boost, SEPIC and fly-back applications are possible with the LTC1871 byconnecting the SENSE pin to a resistor in the source of thepower MOSFET.

    The LTC1871 is available in the 10-lead MSOP package.

    High Efficiency (No Sense Resistor Required) Wide Input Voltage Range: 2.5V to 36V Current Mode Control Provides Excellent

    Transient Response High Maximum Duty Cycle (92% Typ) ±2% RUN Pin Threshold with 100mV Hysteresis ±1% Internal Voltage Reference Micropower Shutdown: IQ = 10µA Programmable Operating Frequency

    (50kHz to 1MHz) with One External Resistor

    Synchronizable to an External Clock Up to 1.3 × fOSC User-Controlled Pulse Skip or Burst Mode® Operation Internal 5.2V Low Dropout Voltage Regulator Output Overvoltage Protection Capable of Operating with a Sense Resistor for High

    Output Voltage Applications Small 10-Lead MSOP Package

    Telecom Power Supplies Portable Electronic Equipment

    Burst Mode is a registered trademark of Linear Technology Corporation.No RSENSE is a trademark of Linear Technology Corporation.

    Figure 1. High Efficiency 3.3V Input, 5V Output Boost Converter (Bootstrapped)

    Efficiency of Figure 1

    , LTC and LT are registered trademarks of Linear Technology Corporation.

    OUTPUT CURRENT (A)

    30

        E    F    F    I    C    I    E    N    C    Y    (    %    )

    90

    100

    80

    50

    70

    60

    40

    0.001 0.1 1 10

    1871 F01b

    0.01

    Burst ModeOPERATION

    PULSE-SKIPMODE

    DESCRIPTIO  U

    FEATURES

    APPLICATIO SU

    TYPICAL APPLICATIO  U

    +

    RUN

    ITH

    FB

    FREQ

    MODE/SYNC

    SENSE

    VIN

    INTVCC

    GATE

    GND

    LTC1871

    RT80.6k1%

    R237.4k

    1%

    R112.1k1% CVCC

    4.7µFX5R

    CIN22µF6.3V×2

    M1

    D1

    L11µH

    RC22k

    CC16.8nF

    CC247pF

    COUT1150µF6.3V×4

    VIN3.3V

    VOUT5V

    7A(10A PEAK)

    GND1871 F01a

    +

    COUT222µF6.3VX5R×2

    CIN: TAIYO YUDEN JMK325BJ226MMCOUT1: PANASONIC EEFUEOJ151RCOUT2: TAIYO YUDEN JMK325BJ226MM

    D1: MBRB2515LL1: SUMIDA CEP125-H 1R0MHM1: FAIRCHILD FDS7760A

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    LTC1871

    (Note 1)

    VIN Voltage ............................................... –0.3V to 36VINTVCC Voltage ........................................... – 0.3V to 7V

    INTVCC Output Current ........................................ 50mAGATE Voltage ........................... –0.3V to VINTVCC + 0.3VITH, FB Voltages ....................................... – 0.3V to 2.7VRUN, MODE/SYNC Voltages ....................... –0.3V to 7VFREQ Voltage ............................................–0.3V to 1.5VSENSE Pin Voltage ................................... –0.3V to 36VOperating Temperature Range (Note 2) .. –40°C to 85°CJunction Temperature (Note 3)............................ 125°CStorage Temperature Range ................. –65°C to 150°CLead Temperature (Soldering, 10 sec).................. 300°C

    ORDER PARTNUMBER

    LTC1871EMS

    TJMAX = 125°C, θJA = 120°C/ W

    ABSOLUTE AXI U RATI GS      W W      W U

    PACKAGE/ORDER I FOR ATIOU UW

    ELECTRICAL CHARACTERISTICS

    MS PART MARKING

    LTSX

    12345

    RUNITHFB

    FREQMODE/ 

    SYNC

    109876

    SENSEVININTVCCGATEGND

    TOP VIEW

    MS PACKAGE10-LEAD PLASTIC MSOP

    SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

    Main Control Loop

    VIN(MIN) Minimum Input Voltage 2.5 V

    IQ Input Voltage Supply Current (Note 4)  Continuous Mode VMODE/SYNC = 5V, VFB = 1.4V, VITH = 0.75V 550 1000   µA  Burst Mode Operation, No Load VMODE/SYNC = 0V, VITH = 0.2V (Note 5) 250 500   µA  Shutdown Mode VRUN = 0V 10 20   µA

    VRUN+ Rising RUN Input Threshold Voltage 1.348 V

    VRUN– Falling RUN Input Threshold Voltage 1.223 1.248 1.273 V

    1.198 1.298 V

    VRUN(HYST) RUN Pin Input Threshold Hysteresis 50 100 150 mV

    IRUN RUN Input Current 1 60 nA

    VFB Feedback Voltage VITH = 0.2V (Note 5) 1.218 1.230 1.242 V 1.212 1.248 V

    IFB FB Pin Input Current VITH = 0.2V (Note 5) 18 60 nA

    ∆VFB Line Regulation 2.5V ≤ VIN ≤ 30V 0.002 0.02 %/V∆VIN ∆VFB Load Regulation VMODE/SYNC = 0V, VTH = 0.5V to 0.90V (Note 5) –1 –0.1 %

    ∆VITH∆VFB(OV)   ∆FB Pin, Overvoltage Lockout VFB(OV) – VFB(NOM) in Percent 2.5 6 10 %

    gm Error Amplifier Transconductance ITH Pin Load = ±5µA (Note 5) 650   µmho

    VITH(BURST) Burst Mode Operation ITH Pin Voltage Falling ITH Voltage (Note 5) 0.3 V

    VSENSE(MAX) Maximum Current Sense Input Threshold Duty Cycle < 20% 120 150 180 mV

    ISENSE(ON) SENSE Pin Current (GATE High) VSENSE = 0V 35 50   µA

    ISENSE(OFF) SENSE Pin Current (GATE Low) VSENSE = 30V 0.1 5   µA

    The  denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.VIN = VINTVCC = 5V, VRUN = 1.5V, RFREQ = 80k, VMODE/SYNC = 0V, unless otherwise specified.

    Consult LTC Marketing for parts specified with wider operating temperature ranges.

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    LTC1871

    TYPICAL PERFOR A CE CHARACTERISTICS    U      W

    FB Voltage vs Temp FB Voltage Line Regulation FB Pin Current vs Temperature

    TEMPERATURE (°C)

    –50

        F    B    V    O    L    T    A    G    E    (    V    )

    1.23

    1.24

    150

    1871 G01

    1.22

    1.210 50 100–25 25 75 125

    1.25

    VIN (V)

    01.229

        F    B    V    O    L    T    A    G    E    (    V    )

    1.230

    1.231

    5 10 15 20

    1871 G02

    25 30 35

    TEMPERATURE (°C)

    –500

        F    B    P    I    N    C    U    R    R    E    N    T    (   n    A    )

    10

    20

    30

    40

    60

    –25 250 50 10075

    1871 G03

    125 150

    50

    Shutdown Mode IQ vs VIN Burst Mode IQ vs VIN

    VIN (V)

    00

        S    H    U    T    D    O    W    N    M    O    D    E    I    Q    (     µ    A    )

    10

    20

    10 20 30 40

    1871 G04

    30

    Shutdown Mode IQ vs Temperature

    TEMPERATURE (°C)

    –500

        S    H    U    T    D    O    W    N    M    O    D    E    I    Q    (    µ    A    )

    5

    10

    15

    20

    –25 0 25 50

    1871 G05

    75 100 125 150

    VIN = 5V

    VIN (V)

    00

        B   u   r   s   t    M   o    d   e    I    Q    (     µ    A    )

    100

    200

    300

    400

    600

    10 20

    1871 G06

    30 40

    500

    Burst Mode IQ vs TemperatureGate Drive Rise and Fall Timevs CLDynamic IQ vs Frequency

    TEMPERATURE (°C)

    –500

        B   u   r   s

       t    M   o    d   e    I    Q    (     µ    A    )

    200

    500

    0 50 75

    1871 G07

    100

    400

    300

    –25 25 100 125 150

    FREQUENCY (kHz)

    00

        I    Q    (   m    A    )

    2

    6

    8

    10

    800

    18

    1871 G08

    4

    400 1200600200 1000

    12

    14

    16

    CL = 3300pFIQ(TOT) = 550µA + Qg • f

    CL (pF)

    00

        T    I    M    E    (   n   s    )

    10

    20

    30

    40

    60

    2000 4000 6000 8000

    1871 G09

    10000 12000

    50

    RISE TIME

    FALL TIME

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    LTC1871

    TYPICAL PERFOR A CE CHARACTERISTICS    U      W

    RUN Thresholds vs VIN RT vs Frequency

    Frequency vs Temperature SENSE Pin Current vs TemperatureMaximum Sense Thresholdvs Temperature

    INTVCC Load RegulationINTVCC Dropout Voltagevs Current, TemperatureINTVCC Line Regulation

    VIN (V)

    01.2

        R    U    N    T    H    R    E    S    H    O    L    D    S    (    V    )

    1.3

    1.4

    10 20   30   40

    1871 G10

    1.5

    RUN Thresholds vs Temperature

    TEMPERATURE (°C)

    –50

        R    U    N    T    H    R    E    S    H    O    L    D    S    (    V    )

    1.30

    1.35

    150

    1871 G11

    1.25

    1.200 50 100–25 25 75 125

    1.40

    FREQUENCY (kHz)

    100

        R    T    (    k     Ω    )

    300

    1000

    1871 G12

    10

    100

    200 10009008007006005004000

    TEMPERATURE (°C)

    –50275

        G    A    T    E    F    R    E    Q    U    E    N    C    Y    (    k    H   z    )

    280

    290

    295

    300

    325

    310

    0 50 75

    1871 G13

    285

    315

    320

    305

    –25 25 100 125 150

    TEMPERATURE (°C)

    –50140

        M    A    X    S    E    N    S    E    T    H    R    E    S    H    O    L    D    (   m    V    )

    145

    150

    155

    160

    –25 0 25 50

    1871 G14

    75 100 125 150

    TEMPERATURE (°C)

    –5025

        S    E    N    S    E    P    I    N    C    U    R    R    E    N    T    (     µ    A    )

    30

    35

    0 50 75

    1871 G15

    –25 25 100 125 150

    GATE HIGHVSENSE = 0V

    INTVCC LOAD (mA)

    0

        I    N    T    V    C    C    V    O    L    T    A    G    E    (    V    )

    5.2

    30 50 80

    1871 G16

    5.1

    5.010 20 40 60 70

    VIN = 7.5V

    VIN (V)

    05.1

        I    N    T    V    C    C    V    O    L    T    A    G    E    (    V    )

    5.2

    5.3

    10 20   30   40

    1871 G17

    5.4

    5 15   25   35

    INTVCC LOAD (mA)

    00

        D    R    O    P    O    U

        T    V    O    L    T    A    G    E    (   m    V    )

    50

    150

    200

    250

    500

    350

    5   10

    1871 G18

    100

    400

    450

    300

    15   20

    150°C

    75°C

    125°C

    25°C

    –50°C

    0°C

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    LTC1871

        U    U    UPI FU CTIO S

    RUN (Pin 1): The RUN pin provides the user with anaccurate means for sensing the input voltage and pro-gramming the start-up threshold for the converter. The

    falling RUN pin threshold is nominally 1.248V and thecomparator has 100mV of hysteresis for noise immunity.When the RUN pin is below this input threshold, the IC isshut down and the VIN supply current is kept to a lowvalue (typ 10µA). The Absolute Maximum Rating for thevoltage on this pin is 7V.

    ITH (Pin 2): Error Amplifier Compensation Pin. The cur-rent comparator input threshold increases with thiscontrol voltage. Nominal voltage range for this pin is 0Vto 1.40V.

    FB (Pin 3):  Receives the feedback voltage from theexternal resistor divider across the output. Nominalvoltage for this pin in regulaton is 1.230V.

    FREQ (Pin 4): A resistor from the FREQ pin to groundprograms the operating frequency of the chip. The nomi-nal voltage at the FREQ pin is 0.6V.

    MODE/SYNC (Pin 5): This input controls the operatingmode of the converter and allows for synchronizing the

    operating frequency to an external clock. If the MODE/ SYNC pin is connected to ground, Burst Mode operationis enabled. If the MODE/SYNC pin is connected to INTVCC,or if an external logic-level synchronization signal isapplied to this input, Burst Mode operation is disabledand the IC operates in a continuous mode.

    GND (Pin 6): Ground Pin.

    GATE (Pin 7): Gate Driver Output.

    INTVCC (Pin 8): The Internal 5.20V Regulator Output. Thegate driver and control circuits are powered from thisvoltage. Decouple this pin locally to the IC ground with aminimum of 4.7µF low ESR tantalum or ceramic

    capacitor.VIN (Pin 9): Main Supply Pin. Must be closely decoupledto ground.

    SENSE (Pin 10): The Current Sense Input for the ControlLoop. Connect this pin to the drain of the power MOSFETfor VDS sensing and highest efficiency. Alternatively, theSENSE pin may be connected to a resistor in the sourceof the power MOSFET. Internal leading edge blanking isprovided for both sensing methods.

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    LTC1871

    BLOCK DIAGRA      W

    +

    +

    +1.230V

    85mVOV

    50k

    EA

    UV

    TOSTART-UP

    CONTROL

    BURSTCOMPARATOR

    S

    RQ

    LOGICPWM LATCH

    CURRENTCOMPARATOR

    0.30V

    1.230V

    5.2V

    +2.00V

    1.230VSLOPE

    1.230V

    ILOOP

    FB

    ITH

    +

    gm

    3

    MODE/SYNC

    5

    FREQ

    4

    2

    INTVCC

    8   LDO

    V-TO-I

    OSCV-TO-I

    SLOPE

    COMPENSATION

    BIAS ANDSTART-UPCONTROL

    VIN

    BIAS VREF

    IOSC

    RLOOP

         –

         +

         –

         +

    C1

    SENSE

    10

    GND

    1871 BD

    6

    GATE

    INTVCC

    GND

    7

    VIN

    1.248V

    9

    RUN

    C2

    1

    0.6V

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    LTC1871

    Main Control Loop

    The LTC1871 is a constant frequency, current mode

    controller for DC/DC boost, SEPIC and flyback converterapplications. The LTC1871 is distinguished from conven-tional current mode controllers because the current con-trol loop can be closed by sensing the voltage drop acrossthe power MOSFET switch instead of across a discretesense resistor, as shown in Figure 2. This sensing tech-nique improves efficiency, increases power density, andreduces the cost of the overall solution.

    OPERATIOU

    to rise, which causes the current comparator C1 to trip ata higher peak inductor current value. The average inductorcurrent will therefore rise until it equals the load current,thereby maintaining output regulation.

    The nominal operating frequency of the LTC1871 is pro-grammed using a resistor from the FREQ pin to groundand can be controlled over a 50kHz to 1000kHz range. Inaddition, the internal oscillator can be synchronized to anexternal clock applied to the MODE/SYNC pin and can belocked to a frequency between 100% and 130% of itsnominal value. When the MODE/SYNC pin is left open, it ispulled low by an internal 50k resistor and Burst Modeoperation is enabled. If this pin is taken above 2V or an

    external clock is applied, Burst Mode operation is disabledand the IC operates in continuous mode. With no load (oran extremely light load), the controller will skip pulses inorder to maintain regulation and prevent excessive outputripple.

    The RUN pin controls whether the IC is enabled or is in alow current shutdown state. A micropower 1.248V refer-ence and comparator C2 allow the user to program thesupply voltage at which the IC turns on and off (compara-tor C2 has 100mV of hysteresis for noise immunity). Withthe RUN pin below 1.248V, the chip is off and the inputsupply current is typically only 10µA.

    An overvoltage comparator OV senses when the FB pinexceeds the reference voltage by 6.5% and provides areset pulse to the main RS latch. Because this RS latch isreset-dominant, the power MOSFET is actively held off forthe duration of an output overvoltage condition.

    The LTC1871 can be used either by sensing the voltagedrop across the power MOSFET or by connecting theSENSE pin to a conventional shunt resistor in the sourceof the power MOSFET, as shown in Figure 2. Sensing the

    voltage across the power MOSFET maximizes converterefficiency and minimizes the component count, but limitsthe output voltage to the maximum rating for this pin(36V). By connecting the SENSE pin to a resistor in thesource of the power MOSFET, the user is able to programoutput voltages significantly greater than 36V.

    COUTVSW

    VSW

    2a. SENSE Pin Connection forMaximum Efficiency (VSW < 36V)

    VOUTVIN

    GND

    L   D

    +

    COUT

    RS

    1871 F02

    2b. SENSE Pin Connection for PreciseControl of Peak Current or for VSW > 36V

    VOUTVIN

    GND

    L   D

    +

    GATE

    GND

    VIN

    SENSE

    GATE

    GND

    VIN

    SENSE

    Figure 2. Using the SENSE Pin On the LTC1871

    For circuit operation, please refer to the Block Diagram ofthe IC and Figure 1. In normal operation, the powerMOSFET is turned on when the oscillator sets the PWMlatch and is turned off when the current comparator C1resets the latch. The divided-down output voltage is com-pared to an internal 1.230V reference by the error amplifierEA, which outputs an error signal at the ITH pin. The voltageon the ITH  pin sets the current comparator C1 inputthreshold. When the load current increases, a fall in the FBvoltage relative to the reference voltage causes the ITH pin

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    LTC1871

    APPLICATIO S I FOR ATIO      W    U U    U

    When the oscillator’s internal logic circuitry detects asynchronizing signal on the MODE/SYNC pin, the internaloscillator ramp is terminated early and the slope compen-

    sation is increased by approximately 30%. As a result, inapplications requiring synchronization, it is recommendedthat the nominal operating frequency of the IC be pro-grammed to be about 75% of the external clock frequency.Attempting to synchronize to too high an external fre-quency (above 1.3fO) can result in inadequate slope com-pensation and possible subharmonic oscillation (or jitter).

    The external clock signal must exceed 2V for at least 25ns,and should have a maximum duty cycle of 80%, as shownin Figure 5. The MOSFET turn on will synchronize to the

    rising edge of the external clock signal.

    to charge and discharge an internal oscillator capacitor. Agraph for selecting the value of RT for a given operatingfrequency is shown in Figure 6.

    Figure 6. Timing Resistor (RT) Value

    Figure 5. MODE/SYNC Clock Input and SwitchingWaveforms for Synchronized Operation

    1871 F05

    2V TO 7VMODE/ SYNC

    GATE

    IL

    tMIN = 25ns

    0.8T

    D = 40%

    T T = 1/fO

    FREQUENCY (kHz)100

        R    T    (    k     Ω    )

    300

    1000

    1871 F06

    10

    100

    200 10009008007006005004000

    Programming the Operating Frequency

    The choice of operating frequency and inductor value is atradeoff between efficiency and component size. Low

    frequency operation improves efficiency by reducingMOSFET and diode switching losses. However, lowerfrequency operation requires more inductance for a givenamount of load current.

    The LTC1871 uses a constant frequency architecture thatcan be programmed over a 50kHz to 1000kHz range witha single external resistor from the FREQ pin to ground, asshown in Figure 1. The nominal voltage on the FREQ pin is0.6V, and the current that flows into the FREQ pin is used

    INTVCC Regulator Bypassing and Operation

    An internal, P-channel low dropout voltage regulator pro-duces the 5.2V supply which powers the gate driver andlogic circuitry within the LTC1871, as shown in Figure 7.The INTVCC regulator can supply up to 50mA and must bebypassed to ground immediately adjacent to the IC pins

    with a minimum of 4.7µF tantalum or ceramic capacitor.Good bypassing is necessary to supply the high transientcurrents required by the MOSFET gate driver.

    For input voltages that don’t exceed 7V (the absolutemaximum rating for this pin), the internal low dropoutregulator in the LTC1871 is redundant and the INTVCC pincan be shorted directly to the VIN pin. With the INTVCC pinshorted to VIN, however, the divider that programs theregulated INTVCC voltage will draw 10µA of current fromthe input supply, even in shutdown mode. For applications

    that require the lowest shutdown mode input supplycurrent, do not connect the INTVCC pin to VIN. Regardlessof whether the INTVCC pin is shorted to VIN or not, it isalways necessary to have the driver circuitry bypassedwith a 4.7µF tantalum or low ESR ceramic capacitor toground immediately adjacent to the INTVCC and GNDpins.

    In an actual application, most of the IC supply current isused to drive the gate capacitance of the power MOSFET.

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    LTC1871

    APPLICATIO S I FOR ATIO      W    U U    U

    As a result, high input voltage applications in which a largepower MOSFET is being driven at high frequencies cancause the LTC1871 to exceed its maximum junctiontemperature rating. The junction temperature can beestimated using the following equations:

    IQ(TOT) ≈ IQ + f • QGPIC = VIN • (IQ + f • QG)

    TJ = TA + PIC • RTH(JA)

    The total quiescent current IQ(TOT) consists of the staticsupply current (IQ) and the current required to charge anddischarge the gate of the power MOSFET. The 10-pinMSOP package has a thermal resistance of RTH(JA)  =120°C/W.

    As an example, consider a power supply with VIN = 5V andVO = 12V at IO = 1A. The switching frequency is 500kHz,and the maximum ambient temperature is 70°C. The

    power MOSFET chosen is the IRF7805, which has amaximum RDS(ON) of 11mΩ (at room temperature) and amaximum total gate charge of 37nC (the temperaturecoefficient of the gate charge is low).

    IQ(TOT) = 600µA + 37nC • 500kHz = 19.1mA

    PIC = 5V • 19.1mA = 95mW

    TJ = 70°C + 120°C/W • 95mW = 81.4°C

    This demonstrates how significant the gate charge currentcan be when compared to the static quiescent current inthe IC.

    To prevent the maximum junction temperature from beingexceeded, the input supply current must be checked whenoperating in a continuous mode at high VIN. A tradeoffbetween the operating frequency and the size of the power

    MOSFET may need to be made in order to maintain areliable IC junction temperature. Prior to lowering theoperating frequency, however, be sure to check withpower MOSFET manufacturers for their latest-and-great-est low QG, low RDS(ON) devices. Power MOSFET manu-facturing technologies are continually improving, withnewer and better performance devices being introducedalmost yearly.

    Output Voltage Programming

    The output voltage is set by a resistor divider according to

    the following formula:

    V V  R

    RO = +

      

         

    1 230 1  2

    1. •

    The external resistor divider is connected to the output asshown in Figure 1, allowing remote voltage sensing. Theresistors R1 and R2 are typically chosen so that the error

    Figure 7. Bypassing the LDO Regulator and Gate Driver Supply

    +

    +

    1.230V

    R2 R1

    P-CH

    5.2V

    DRIVER  GATE

    CVCC4.7µF

    CIN

    INPUTSUPPLY2.5V TO 30V

    GND

    PLACE AS CLOSE ASPOSSIBLE TO DEVICE PINS

    M1

    1871 F07

    INTVCC

    VIN

    GND

    LOGIC

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    APPLICATIO S I FOR ATIO      W    U U    U

    caused by the current flowing into the FB pin duringnormal operation is less than 1% (this translates to amaximum value of R1 of about 250k).

    Programming Turn-On and Turn-Off Thresholdswith the RUN Pin

    The LTC1871 contains an independent, micropower volt-age reference and comparator detection circuit that re-mains active even when the device is shut down, as shownin Figure 8. This allows users to accurately program aninput voltage at which the converter will turn on and off.The falling threshold voltage on the RUN pin is equal to theinternal reference voltage of 1.248V. The comparator has

    100mV of hysteresis to increase noise immunity.

    The turn-on and turn-off input voltage thresholds areprogrammed using a resistor divider according to thefollowing formulas:

    V V  R

    R

    V V  R

    R

    IN OFF

    IN ON

    ( )

    ( )

    . •

    . •

    = +  

         

    = +  

         

    1 248 1  2

    1

    1 348 1  2

    1

    The resistor R1 is typically chosen to be less than 1M.

    For applications where the RUN pin is only to be used asa logic input, the user should be aware of the 7VAbsolute Maximum Rating for this pin! The RUN pin can

    be connected to the input voltage through an external 1Mresistor, as shown in Figure 8c, for “always on” operaton.

    +

    RUNCOMPARATOR

    VIN

    RUNR2

    R1

    INPUTSUPPLY OPTIONAL

    FILTERCAPACITOR

    +

    –GND

    1871 F8a

    BIAS ANDSTART-UPCONTROL

    1.248VµPOWER

    REFERENCE

    6V

    Figure 8b. On/Off Control Using External LogicFigure 8c. External Pull-Up Resistor OnRUN Pin for “Always On” Operation

    Figure 8a. Programming the Turn-On and Turn-Off Thresholds Using the RUN Pin

    +

    RUNCOMPARATOR

    1.248V

    1871 F08b

    RUN

    6VEXTERNAL

    LOGIC CONTROL

    +

    RUNCOMPARATOR

    VIN

    RUN

    R21M

    INPUTSUPPLY

    +

    –GND 1.248V

    1871 F08c

    6V

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    APPLICATIO S I FOR ATIO      W    U U    U

    Application Circuits

    A basic LTC1871 application circuit is shown in

    Figure 1. External component selection is driven by thecharacteristics of the load and the input supply. The firsttopology to be analyzed will be the boost converter,followed by SEPIC (single ended primary inductanceconverter).

    Boost Converter: Duty Cycle Considerations

    For a boost converter operating in a continuous conduc-tion mode (CCM), the duty cycle of the main switch is:

    D

      V V V

    V V

    O D IN

    O D=

      +

    +

     

     

     

      

    where VD is the forward voltage of the boost diode. Forconverters where the input voltage is close to the outputvoltage, the duty cycle is low and for converters thatdevelop a high output voltage from a low voltage inputsupply, the duty cycle is high. The maximum outputvoltage for a boost converter operating in CCM is:

    V  V

    D  VO MAX

    IN MIN

    MAXD( )

    ( )

    –  –=

    ( )1

    The maximum duty cycle capability of the LTC1871 istypically 92%. This allows the user to obtain high outputvoltages from low input supply voltages.

    Boost Converter: The Peak and Average Input Currents

    The control circuit in the LTC1871 is measuring the inputcurrent (either by using the RDS(ON) of the power MOSFETor by using a sense resistor in the MOSFET source), so theoutput current needs to be reflected back to the input inorder to dimension the power MOSFET properly. Based on

    the fact that, ideally, the output power is equal to the inputpower, the maximum average input current is:

    I  I

    D

    Thepeak input current is

    I  I

    D

    IN MAXO MAX

    MAX

    IN PEAKO MAX

    MAX

    ( )( )

    ( )( )

    :

    •–

    =

    = +  

         

    1

    12 1

    χ

    The maximum duty cycle, DMAX, should be calculated atminimum VIN.

    Boost Converter: Ripple Current ∆IL and the ‘χ’ FactorThe constant ‘χ’ in the equation above represents thepercentage peak-to-peak ripple current in the inductor,relative to its maximum value. For example, if 30% ripplecurrent is chosen, then χ = 0.30, and the peak current is15% greater than the average.

    For a current mode boost regulator operating in CCM,slope compensation must be added for duty cycles above50% in order to avoid subharmonic oscillation. For theLTC1871, this ramp compensation is internal. Having an

    internally fixed ramp compensation waveform, however,does place some constraints on the value of the inductorand the operating frequency. If too large an inductor isused, the resulting current ramp (∆IL) will be small relativeto the internal ramp compensation (at duty cycles above50%), and the converter operation will approach voltagemode (ramp compensation reduces the gain of the currentloop). If too small an inductor is used, but the converter isstill operating in CCM (near critical conduction mode), theinternal ramp compensation may be inadequate to preventsubharmonic oscillation. To ensure good current mode

    gain and avoid subharmonic oscillation, it is recom-mended that the ripple current in the inductor fall in therange of 20% to 40% of the maximum average current. Forexample, if the maximum average input current is 1A,choose a ∆IL  between 0.2A and 0.4A, and a value ‘χ’between 0.2 and 0.4.

    Boost Converter: Inductor Selection

    Given an operating input voltage range, and having chosenthe operating frequency and ripple current in the inductor,the inductor value can be determined using the followingequation:

    L  V

    I f  D

    where

    I  I

    D

    IN MIN

    LMAX

    LO MAX

    MAX

    =∆

    ∆ =

    ( )

    ( )

    •  •

    :

    •–

    χ1

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    LTC1871

    Remember that boost converters are not  short-circuitprotected. Under a shorted output condition, the inductorcurrent is limited only by the input supply capability. For

    applications requiring a step-up converter that is short-circuit protected, please refer to the applications sectioncovering SEPIC converters.

    The minimum required saturation current of the inductorcan be expressed as a function of the duty cycle and theload current, as follows:

    I  I

    DL SAT

    O MAX

    MAX( )

    ( )•

    –≥ + 

        

      1

    2 1

    χ

    The saturation current rating for the inductor should bechecked at the minimum input voltage (which results inthe highest inductor current) and maximum outputcurrent.

    Boost Converter: Operating in Discontinuous Mode

    Discontinuous mode operation occurs when the loadcurrent is low enough to allow the inductor current to runout during the off-time of the switch, as shown in Figure 9.Once the inductor current is near zero, the switch anddiode capacitances resonate with the inductance to form

    damped ringing at 1MHz to 10MHz. If the off-time is longenough, the drain voltage will settle to the input voltage.

    Depending on the input voltage and the residual energy inthe inductor, this ringing can cause the drain of the powerMOSFET to go below ground where it is clamped by thebody diode. This ringing is not harmful to the IC and it hasnot been shown to contribute significantly to EMI. Anyattempt to damp it with a snubber will degrade the efficiency.

    Boost Converter: Inductor Core Selection

    Once the value for L is known, the type of inductor must be

    selected. High efficiency converters generally cannot af-ford the core loss found in low cost powdered iron cores,forcing the use of more expensive ferrite, molypermalloyor Kool Mµ® cores. Actual core loss is independent of coresize for a fixed inductor value, but is very dependent on theinductance selected. As inductance increases, core lossesgo down. Unfortunately, increased inductance requiresmore turns of wire and therefore, copper losses willincrease. Generally, there is a tradeoff between core lossesand copper losses that needs to be balanced.

    Ferrite designs have very low core losses and are preferred

    at high switching frequencies, so design goals can con-centrate on copper losses and preventing saturation.Ferrite core material saturates “hard,” meaning that theinductance collapses rapidly when the peak design currentis exceeded. This results in an abrupt increase in inductorripple current and consequently, output voltage ripple. Donot allow the core to saturate!

    Molypermalloy (from Magnetics, Inc.) is a very good, lowcost core material for toroids, but is more expensive thanferrite. A reasonable compromise from the same manu-

    facturer is Kool Mµ.Boost Converter: Power MOSFET Selection

    The power MOSFET serves two purposes in the LTC1871:it represents the main switching element in the powerpath, and its RDS(ON) represents the current sensing ele-ment for the control loop. Important parameters for thepower MOSFET include the drain-to-source breakdownvoltage (BVDSS), the threshold voltage (VGS(TH)), the on-resistance (RDS(ON)) versus gate-to-source voltage, thegate-to-source and gate-to-drain charges (QGS and QGD,

    respectively), the maximum drain current (ID(MAX)) andthe MOSFET’s thermal resistances (RTH(JC) and RTH(JA)).

    The gate drive voltage is set by the 5.2V INTVCC low dropregulator. Consequently, logic-level threshold MOSFETsshould be used in most LTC1871 applications. If low inputvoltage operation is expected (e.g., supplying power from

    APPLICATIO S I FOR ATIO      W    U U    U

    Kool Mµ is a registered trademark of Magnetics, Inc.

    Figure 9. Discontinuous Mode Waveforms

    MOSFET DRAINVOLTAGE

    2V/DIV

    INDUCTORCURRENT

    2A/DIV

    VIN = 3.3VVOUT = 5V

    IOUT = 200mA

    2µs/DIV 1871 F09

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    a lithium-ion battery or a 3.3V logic supply), then sublogic-level threshold MOSFETs should be used.

    Pay close attention to the BVDSS specifications for theMOSFETs relative to the maximum actual switch voltage inthe application. Many logic-level devices are limited to 30Vor less, and the switch node can ring during the turn-off ofthe MOSFET due to layout parasitics. Check the switchingwaveforms of the MOSFET directly across the drain andsource terminals using the actual PC board layout (not juston a lab breadboard!) for excessive ringing.

    During the switch on-time, the control circuit limits themaximum voltage drop across the power MOSFET toabout 150mV (at low duty cycle). The peak inductor

    current is therefore limited to 150mV/RDS(ON). The rela-tionship between the maximum load current, duty cycleand the RDS(ON) of the power MOSFET is:

    R V  D

    IDS ON SENSE MAX

    MAX

    O MAX T

    ( ) ( )

    ( )

    •  –

    • •

    ≤+ 

        

      

    1

    12

    χ ρ

    The VSENSE(MAX) term is typically 150mV at low dutycycle, and is reduced to about 100mV at a duty cycle of92% due to slope compensation, as shown in Figure 10.

    The ρT term accounts for the temperature coefficient ofthe RDS(ON) of the MOSFET, which is typically 0.4%/ °C.Figure 11 illustrates the variation of normalized RDS(ON)over temperature for a typical power MOSFET.

    Another method of choosing which power MOSFET to useis to check what the maximum output current is for a givenRDS(ON), since MOSFET on-resistances are available in

    discrete values.

    I V  D

    RO MAX SENSE MAX

    MAX

    DS ON T

    ( ) ( )

    ( )

    •  –

    • •

    =+ 

        

      

    1

    12

    χ ρ

    It is worth noting that the 1 – DMAX relationship betweenIO(MAX) and RDS(ON) can cause boost converters with awide input range to experience a dramatic range of maxi-mum input and output current. This should be taken intoconsideration in applications where it is important to limitthe maximum current drawn from the input supply.

    Calculating Power MOSFET Switching and ConductionLosses and Junction Temperatures

    In order to calculate the junction temperature of the powerMOSFET, the power dissipated by the device must beknown. This power dissipation is a function of the dutycycle, the load current and the junction temperature itself(due to the positive temperature coefficient of its RDS(ON)).As a result, some iterative calculation is normally requiredto determine a reasonably accurate value. Since the

    controller is using the MOSFET as both a switching and asensing element, care should be taken to ensure that theconverter is capable of delivering the required load currentover all operating conditions (line voltage and tempera-ture), and for the worst-case specifications for VSENSE(MAX)

    APPLICATIO S I FOR ATIO      W    U U    U

    DUTY CYCLE

    0

        M    A    X    I    M    U    M

        C    U    R    R    E    N

        T    S    E    N    S    E    V    O    L    T    A    G    E    (   m    V    )

    100

    150

    0.8

    1871 F10

    50

    00.2   0.4   0.5   1.0

    200

    Figure 10. Maximum SENSE Threshold Voltage vs Duty Cycle

    JUNCTION TEMPERATURE (°C)

    –50

          ρ    T    N    O    R    M    A    L    I    Z    E    D    O    N    R    E    S    I    S    T    A    N    C    E

    1.0

    1.5

    150

    1871 F11

    0.5

    00 50 100

    2.0

    Figure 11. Normalized RDS(ON) vs Temperature

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    and the RDS(ON) of the MOSFET listed in the manufacturer’sdata sheet.

    The power dissipated by the MOSFET in a boost converteris:

    P  I

    D  R D

    k V  I

    D  C f

    FETO MAX

    MAXDS ON MAX T

    OO MAX

    MAXRSS

    =  

      

      

    +( )

    ( )( )

    .   ( )

    –  • • •

    • •–

      • •

    1

    1

    2

    1 85

    ρ

    The first term in the equation above represents the I2Rlosses in the device, and the second term, the switching

    losses. The constant, k = 1.7, is an empirical factor in-versely related to the gate drive current and has the dimen-sion of 1/current.

    From a known power dissipated in the power MOSFET, itsjunction temperature can be obtained using the followingformula:

    TJ = TA + PFET • RTH(JA)

    The RTH(JA) to be used in this equation normally includesthe RTH(JC) for the device plus the thermal resistance fromthe case to the ambient temperature (RTH(CA)). This value

    of TJ can then be compared to the original, assumed valueused in the iterative calculation process.

    Boost Converter: Output Diode Selection

    To maximize efficiency, a fast switching diode with lowforward drop and low reverse leakage is desired. Theoutput diode in a boost converter conducts current duringthe switch off-time. The peak reverse voltage that thediode must withstand is equal to the regulator outputvoltage. The average forward current in normal operationis equal to the output current, and the peak current is equalto the peak inductor current.

    I I  I

    DD PEAK L PEAK

    O MAX

    MAX( ) ( )

    ( )•

    –= = + 

        

      1

    2 1

    χ

    The power dissipated by the diode is:

    PD = IO(MAX) • VD

    and the diode junction temperature is:

    TJ = TA + PD • RTH(JA)

    The RTH(JA) to be used in this equation normally includesthe RTH(JC) for the device plus the thermal resistance fromthe board to the ambient temperature in the enclosure.

    Remember to keep the diode lead lengths short and toobserve proper switch-node layout (see Board LayoutChecklist) to avoid excessive ringing and increaseddissipation.

    Boost Converter: Output Capacitor Selection

    Contributions of ESR (equivalent series resistance), ESL

    (equivalent series inductance) and the bulk capacitancemust be considered when choosing the correct compo-nent for a given output ripple voltage. The effects of thesethree parameters (ESR, ESL and bulk C) on the outputvoltage ripple waveform are illustrated in Figure 12e for atypical boost converter.

    The choice of component(s) begins with the maximumacceptable ripple voltage (expressed as a percentage ofthe output voltage), and how this ripple should be dividedbetween the ESR step and the charging/discharging ∆V.For the purpose of simplicity we will choose 2% for themaximum output ripple, to be divided equally betweenthe ESR step and the charging/discharging ∆V. Thispercentage ripple will change, depending on the require-ments of the application, and the equations providedbelow can easily be modified.

    For a 1% contribution to the total ripple voltage, the ESRof the output capacitor can be determined using thefollowing equation:

    ESR  V

    ICOUT

    O

    IN PEAK

    ≤ 0 01. •

    ( )

    where:

    I  I

    DIN PEAK

    O MAX

    MAX( )

    ( )•

    –= + 

        

      1

    2 1

    χ

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    For the bulk C component, which also contributes 1% tothe total ripple:

    C   IV f

    OUTO MAX

    O≥   ( )

    . • •0 01

    For many designs it is possible to choose a single capaci-tor type that satisfies both the ESR and bulk C require-ments for the design. In certain demanding applications,however, the ripple voltage can be improved significantlyby connecting two or more types of capacitors in parallel.For example, using a low ESR ceramic capacitor canminimize the ESR step, while an electrolytic capacitor canbe used to supply the required bulk C.

    Once the output capacitor ESR and bulk capacitance havebeen determined, the overall ripple voltage waveformshould be verified on a dedicated PC board (see BoardLayout section for more information on component place-ment). Lab breadboards generally suffer from excessiveseries inductance (due to inter-component wiring), andthese parasitics can make the switching waveforms looksignificantly worse than they would be on a properlydesigned PC board.

    The output capacitor in a boost regulator experiences high

    RMS ripple currents, as shown in Figure 12. The RMSoutput capacitor ripple current is:

    I I  V V

    VRMS COUT O MAX

    O IN MIN

    IN MIN( ) ( )

    ( )

    ( )•

      –≈

    Note that the ripple current ratings from capacitor manu-facturers are often based on only 2000 hours of life. Thismakes it advisable to further derate the capacitor or tochoose a capacitor rated at a higher temperature thanrequired. Several capacitors may also be placed in parallel

    to meet size or height requirements in the design.Manufacturers such as Nichicon, United Chemicon andSanyo should be considered for high performance through-hole capacitors. The OS-CON semiconductor dielectriccapacitor available from Sanyo has the lowest product ofESR and size of any aluminum electrolytic, at a somewhathigher price.

    In surface mount applications, multiple capacitors mayhave to be placed in parallel in order to meet the ESR orRMS current handling requirements of the application.

    Aluminum electrolytic and dry tantalum capacitors areboth available in surface mount packages. In the case oftantalum, it is critical that the capacitors have been surgetested for use in switching power supplies. An excellentchoice is AVX TPS series of surface mount tantalum. Also,ceramic capacitors are now available with extremely lowESR, ESL and high ripple current ratings.

    Boost Converter: Input Capacitor Selection

    The input capacitor of a boost converter is less critical than

    the output capacitor, due to the fact that the inductor is inseries with the input and the input current waveform is

    APPLICATIO S I FOR ATIO      W    U U    U

    VIN

    L D

    SW

    12a. Circuit Diagram

    12b. Inductor and Input Currents

    COUT

    VOUT

    RL

    IINIL

    12c. Switch Current

    ISW

    tON

    12d. Diode and Output Currents

    12e. Output Voltage Ripple Waveform

    IO

    ID

    VOUT(AC)

    tOFF

    ∆VESR

    RINGING DUE TOTOTAL INDUCTANCE(BOARD + CAP)

    ∆VCOUT

    Figure 12. Switching Waveforms for a Boost Converter

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    continuous (see Figure 12b). The input voltage source im-pedance determines the size of the input capacitor, whichis typically in the range of 10µF to 100µF. A low ESR capaci-tor is recommended, although it is not as critical as for theoutput capacitor.

    The RMS input capacitor ripple current for a boost con-verter is:

    I  V

    L f  DRMS CIN

    IN MINMAX( )

    ( ). •

    •  •= 0 3

    Please note that the input capacitor can see a very highsurge current when a battery is suddenly connected to theinput of the converter and solid tantalum capacitors canfail catastrophically under these conditions. Be sure tospecify surge-tested capacitors!

    Burst Mode Operation and Considerations

    The choice of MOSFET RDS(ON) and inductor value alsodetermines the load current at which the LTC1871 entersBurst Mode operation. When bursting, the controller clampsthe peak inductor current to approximately:

    I  mV

    RBURST PEAK

    DS ON( )

    ( )=   30

    which represents about 20% of the maximum 150mVSENSE pin voltage. The corresponding average currentdepends upon the amount of ripple current. Lower induc-tor values (higher ∆IL) will reduce the load current at whichBurst Mode operations begins, since it is the peak currentthat is being clamped.

    APPLICATIO S I FOR ATIO      W    U U    U

    Table 1. Recommended Component Manufacturers

    VENDOR COMPONENTS TELEPHONE WEB ADDRESS

    AVX Capacitors (207) 282-5111 avxcorp.com

    BH Electronics Inductors, Transformers (952) 894-9590 bhelectronics.comCoilcraft Inductors (847) 639-6400 coilcraft.com

    Coiltronics Inductors (407) 241-7876 coiltronics.com

    Diodes, Inc Diodes (805) 446-4800 diodes.com

    Fairchild MOSFETs (408) 822-2126 fairchildsemi.com

    General Semiconductor Diodes (516) 847-3000 generalsemiconductor.com

    International Rectifier MOSFETs, Diodes (310) 322-3331 irf.com

    IRC Sense Resistors (361) 992-7900 irctt.com

    Kemet Tantalum Capacitors (408) 986-0424 kemet.com

    Magnetics Inc Toroid Cores (800) 245-3984 mag-inc.com

    Microsemi Diodes (617) 926-0404 microsemi.com

    Murata-Erie Inductors, Capacitors (770) 436-1300 murata.co.jp

    Nichicon Capacitors (847) 843-7500 nichicon.com

    On Semiconductor Diodes (602) 244-6600 onsemi.com

    Panasonic Capacitors (714) 373-7334 panasonic.com

    Sanyo Capacitors (619) 661-6835 sanyo.co.jp

    Sumida Inductors (847) 956-0667 sumida.com

    Taiyo Yuden Capacitors (408) 573-4150 t-yuden.com

    TDK Capacitors, Inductors (562) 596-1212 component.tdk.com

    Thermalloy Heat Sinks (972) 243-4321 aavidthermalloy.com

    Tokin Capacitors (408) 432-8020 tokin.com

    Toko Inductors (847) 699-3430 tokoam.com

    United Chemicon Capacitors (847) 696-2000 chemi-com.com

    Vishay/Dale Resistors (605) 665-9301 vishay.comVishay/Siliconix MOSFETs (800) 554-5565 vishay.com

    Vishay/Sprague Capacitors (207) 324-4140 vishay.com

    Zetex Small-Signal Discretes (631) 543-7100 zetex.com

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    The output voltage ripple can increase during Burst Modeoperation if ∆IL is substantially less than IBURST. This canoccur if the input voltage is very low or if a very large

    inductor is chosen. At high duty cycles, a skipped cyclecauses the inductor current to quickly decay to zero.However, because ∆IL is small, it takes multiple cycles forthe current to ramp back up to IBURST(PEAK). During thisinductor charging interval, the output capacitor mustsupply the load current and a significant droop in theoutput voltage can occur. Generally, it is a good idea tochoose a value of inductor ∆IL between 25% and 40% ofIIN(MAX). The alternative is to either increase the value ofthe output capacitor or disable Burst Mode operationusing the MODE/SYNC pin.

    Burst Mode operation can be defeated by connecting theMODE/SYNC pin to a high logic-level voltage (either witha control input or by connecting this pin to INTVCC). In thismode, the burst clamp is removed, and the chip canoperate at constant frequency from continuous conduc-tion mode (CCM) at full load, down into deep discontinu-ous conduction mode (DCM) at light load. Prior to skip-ping pulses at very light load (i.e.,

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    resistor value would be 10mΩ, and the power dissi-pated in this resistor would be 514mW at maximumoutput current. Assuming an efficiency of 90%, this

    sense resistor power dissipation represents 1.3% ofthe overall input power. In other words, for this appli-cation, the use of VDS  sensing would increase theefficiency by approximately 1.3%.

    For more details regarding the various terms in theseequations, please refer to the section Boost Converter:Power MOSFET Selection.

    3. The losses in the inductor are simply the DC inputcurrent squared times the winding resistance. Express-ing this loss as a function of the output current yields:

    P  I

    D  RR WINDING

    O MAX

    MAXW( )

    ( )

    –  •=

      

         1

    2

    4. Losses in the boost diode. The power dissipation in theboost diode is:

    PDIODE = IO(MAX) • VD

    The boost diode can be a major source of power loss ina boost converter. For the 3.3V input, 5V output at 7Aexample given above, a Schottky diode with a 0.4V

    forward voltage would dissipate 2.8W, which repre-sents 7% of the input power. Diode losses can becomesignificant at low output voltages where the forwardvoltage is a significant percentage of the output voltage.

    5. Other losses, including CIN and CO ESR dissipation andinductor core losses, generally account for less than2% of the total additional loss.

    Checking Transient Response

    The regulator loop response can be verified by looking atthe load transient response. Switching regulators gener-ally take several cycles to respond to an instantaneousstep in resistive load current. When the load step occurs,VO immediately shifts by an amount equal to (∆ILOAD)(ESR),and then CO begins to charge or discharge (depending onthe direction of the load step) as shown in Figure 13. Theregulator feedback loop acts on the resulting error ampoutput signal to return VO to its steady-state value. Duringthis recovery time, VO can be monitored for overshoot orringing that would indicate a stability problem.

    A second, more severe transient can occur when connect-

    ing loads with large (>1µF) supply bypass capacitors. Thedischarged bypass capacitors are effectively put in parallelwith CO, causing a nearly instantaneous drop in VO. Noregulator can deliver enough current to prevent this prob-lem if the load switch resistance is low and it is drivenquickly. The only solution is to limit the rise time of theswitch drive in order to limit the inrush current di/dt to theload.

    Boost Converter Design Example

    The design example given here will be for the circuit shownin Figure 1. The input voltage is 3.3V, and the output is 5Vat a maximum load current of 7A (10A peak).

    1. The duty cycle is:

    D  V V V

    V VO D IN

    O D=

      ++

      

          =

      ++

      =– . – .

    .  . %

    5 0 4 3 3

    5 0 4  38 9

    2. Pulse-skip operation is chosen so the MODE/SYNC pinis shorted to INTVCC.

    3. The operating frequency is chosen to be 300kHz toreduce the size of the inductor. From Figure 5, theresistor from the FREQ pin to ground is 80k.

    4. An inductor ripple current of 40% of the maximum loadcurrent is chosen, so the peak input current (which isalso the minimum saturation current) is:

    I  I

    D  AIN PEAK

    O MAX

    MAX( )

    ( )•

    –  . •

    – .  .= + 

        

        = =1

    2 1  1 2

      7

    1 0 39  13 8

    χ

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    IOUT2A/DIV

    VOUT (AC)100mV/DIV

    Figure 13. Load Transient Response for a 3.3V Input,5V Output Boost Converter Application, 0.7A to 7A Step

    VIN = 3.3VVOUT = 5VMODE/SYNC = INTVCC(PULSE-SKIP MODE)

    100µs/DIV 1871 F13

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    The inductor ripple current is:

    ∆ = = =I  I

    D

      ALO MAX

    MAX

    χ •–

      . •

    – .

      .( )

    1

      0 4  7

    1 0 39

      4 6

    And so the inductor value is:

    L  V

    I f  D

      V

    A kHz  H

    IN MIN

    LMAX= ∆

      = = µ( )•

      •  .

    . •  • . .

    3 3

    4 6 300  0 39 0 93

    The component chosen is a 1µH inductor made bySumida (part number CEP125-H 1ROMH) which has asaturation current of greater than 20A.

    5. With the input voltage to the IC bootstrapped to theoutput of the power supply (5V), a logic-level MOSFET

    can be used. Because the duty cycle is 39%, themaximum SENSE pin threshold voltage is reduced fromits low duty cycle typical value of 150mV to approxi-mately 140mV. Assuming a MOSFET junction tempera-ture of 125°C, the room temperature MOSFET RDS(ON)should be less than:

    R V  D

    I

    VA

    m

    DS ON SENSE MAXMAX

    O MAX T

    ( ) ( )

    ( )

    •  –

    • •

    . •  – .

    .• • .

    .

    ≤+ 

        

      

    =+ 

        

      = Ω

    1

    12

    0 140  1 0 39

    1  0 4

    2  7 1 5

    6 8

    χ ρ

    The MOSFET used was the Fairchild FDS7760A, whichhas a maximum RDS(ON) of 8mΩ at 4.5V VGS, a BVDSSof greater than 30V, and a gate charge of 37nC at 5VVGS.

    6. The diode for this design must handle a maximum DCoutput current of 10A and be rated for a minimumreverse voltage of VOUT, or 5V. A 25A, 15V diode from

    On Semiconductor (MBRB2515L) was chosen for itshigh power dissipation capability.

    7. The output capacitor usually consists of a high valuedbulk C connected in parallel with a lower valued, lowESR ceramic. Based on a maximum output ripplevoltage of 1%, or 50mV, the bulk C needs to be greaterthan:

    C  I

    V f

    AV kHz

      F

    OUTOUT MAX

    OUT≥ =

    = µ

    ( )

    . • •

    . • •

    0 01

    70 01 5 300

      466

    The RMS ripple current rating for this capacitor needsto exceed:

    I I  V V

    V

    A  V V

    V  A

    RMS COUT O MAXO IN MIN

    IN MIN( ) ( )

    ( )

    ( )•

      –

    •  – .

    .

    ≥ =

    =7  5 3 3

    3 3  5

    To satisfy this high RMS current demand, four 150µFPanasonic capacitors (EEFUEOJ151R) are required.In parallel with these bulk capacitors, two 22µF, lowESR (X5R) Taiyo Yuden ceramic capacitors(JMK325BJ226MM) are added for HF noise reduction.Check the output ripple with a single oscilloscopeprobe connected directly across the output capacitorterminals, where the HF switching currents flow.

    8. The choice of an input capacitor for a boost converterdepends on the impedance of the source supply and the

    amount of input ripple the converter will safely tolerate.For this particular design and lab setup a 100µF SanyoPoscap (6TPC 100M), in parallel with two 22µF TaiyoYuden ceramic capacitors (JMK325BJ226MM) is re-quired (the input and return lead lengths are kept to afew inches, but the peak input current is close to 20A!).As with the output node, check the input ripple with asingle oscilloscope probe connected across the inputcapacitor terminals.

    PC Board Layout Checklist

    1. In order to minimize switching noise and improveoutput load regulation, the GND pin of the LTC1871should be connected directly to 1) the negative termi-nal of the INTVCC decoupling capacitor, 2) the negativeterminal of the output decoupling capacitors, 3) thesource of the power MOSFET or the bottom terminal ofthe sense resistor, 4) the negative terminal of the inputcapacitor and 5) at least one via to the ground plane

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    immediately adjacent to Pin 6. The ground trace on thetop layer of the PC board should be as wide and shortas possible to minimize series resistance and induc-

    tance.

    2. Beware of ground loops in multiple layer PC boards. Tryto maintain one central ground node on the board anduse the input capacitor to avoid excess input ripple for

    high output current power supplies. If the ground plane

    LTC1871

    M1

    VIN

    1871 F14

    VOUT

    SWITCH NODE IS ALSOTHE HEAT SPREADERFOR L1, M1, D1

    L1

    RT

    RC CC

    R3

    J1

    CIN

    COUT

    CVCC

    R1

    R2

    PSEUDO-KELVINSIGNAL GROUND

    CONNECTION

    TRUE REMOTE

    OUTPUT SENSING

     VIAS TO GROUND PLANE

    R4

    PIN 1

    COUT

    BULK C LOW ESR CERAMIC

    JUMPER

    D1

    Figure 14. LTC1871 Boost Converter Suggested Layout

    RUN

    ITH

    FB

    FREQ

    MODE/ SYNC

    SENSE

    VIN

    INTVCC

    GATE

    GND

    LTC1871

    +

    R4

    J110

    9

    8

    7

    6

    1

    2

    3

    4

    5

    CVCC

    PSEUDO-KELVINGROUND CONNECTION

    CIN

    M1

    D1

    L1

    VIN

    GND

    1871 F15

    VOUT

    SWITCHNODE

    COUT

    RC

    R1

    RT

    BOLD LINES INDICATE HIGH CURRENT PATHS

    R2

    CC

    R3

         +

    Figure 15. LTC1871 Boost Converter Layout Diagram

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    is to be used for high DC currents, choose a path awayfrom the small-signal components.

    3. Place the CVCC capacitor immediately adjacent to theINTVCC and GND pins on the IC package. This capacitorcarries high di/dt MOSFET gate drive currents. A lowESR and ESL 4.7µF ceramic capacitor works well here.

    4. The high di/dt loop from the bottom terminal of theoutput capacitor, through the power MOSFET, throughthe boost diode and back through the output capacitorsshould be kept as tight as possible to reduce inductiveringing. Excess inductance can cause increased stresson the power MOSFET and increase HF noise on theoutput. If low ESR ceramic capacitors are used on the

    output to reduce output noise, place these capacitorsclose to the boost diode in order to keep the seriesinductance to a minimum.

    5. Check the stress on the power MOSFET by measuringits drain-to-source voltage directly across the deviceterminals (reference the ground of a single scope probedirectly to the source pad on the PC board). Beware ofinductive ringing which can exceed the maximum speci-fied voltage rating of the MOSFET. If this ringing cannotbe avoided and exceeds the maximum rating of the

    device, either choose a higher voltage device or specifyan avalanche-rated power MOSFET. Not all MOSFETsare created equal (some are more equal than others).

    6. Place the small-signal components away from highfrequency switching nodes. In the layout shown inFigure 14, all of the small-signal components have beenplaced on one side of the IC and all of the powercomponents have been placed on the other. This alsoallows the use of a pseudo-Kelvin connection for thesignal ground, where high di/dt gate driver currentsflow out of the IC ground pin in one direction (to the

    bottom plate of the INTVCC decoupling capacitor) andsmall-signal currents flow in the other direction.

    7. If a sense resistor is used in the source of the powerMOSFET, minimize the capacitance between the SENSEpin trace and any high frequency switching nodes. TheLTC1871 contains an internal leading edge blankingtime of approximately 180ns, which should be ad-equate for most applications.

    8. For optimum load regulation and true remote sensing,the top of the output resistor divider should connectindependently to the top of the output capacitor (Kelvin

    connection), staying away from any high dV/dt traces.Place the divider resistors near the LTC1871 in order tokeep the high impedance FB node short.

    9. For applications with multiple switching power con-verters connected to the same input supply, make surethat the input filter capacitor for the LTC1871 is notshared with other converters. AC input current fromanother converter could cause substantial input voltageripple, and this could interfere with the operation of theLTC1871. A few inches of PC trace or wire (L ≈ 100nH)

    between the CIN of the LTC1871 and the actual sourceVIN  should be sufficient to prevent current sharingproblems.

    SEPIC Converter Applications

    The LTC1871 is also well suited to SEPIC (single-endedprimary inductance converter) converter applications. TheSEPIC converter shown in Figure 16 uses two inductors.The advantage of the SEPIC converter is the input voltagemay be higher or lower than the output voltage, and theoutput is short-circuit protected.

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    Figures 16. SEPIC Topolgy and Current Flow

    +     +

         +

    SW L2 COUT RL

    VOUT

    VIN

    C1 D1L1

    16a. SEPIC Topology

    +     +

         +

    RL

    VOUT

    VIN

    D1

    16c. Current Flow During Switch Off-Time

    +     +

         +

    RL

    VOUT

    VIN

    VIN

    VIN

    16b. Current Flow During Switch On-Time

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    The first inductor, L1, together with the main switch,resembles a boost converter. The second inductor, L2,together with the output diode D1, resembles a flyback or

    buck-boost converter. The two inductors L1 and L2 can beindependent but can also be wound on the same core sinceidentical voltages are applied to L1 and L2 throughout theswitching cycle. By making L1 = L2 and winding them onthe same core the input ripple is reduced along with costand size. All of the SEPIC applications information thatfollows assumes L1 = L2 = L.

    SEPIC Converter: Duty Cycle Considerations

    For a SEPIC converter operating in a continuous conduc-

    tion mode (CCM), the duty cycle of the main switch is:

    D  V V

    V V V

    O D

    IN O D

    =  +

    + +

     

      

      

    where VD is the forward voltage of the diode. For convert-ers where the input voltage is close to the output voltagethe duty cycle is near 50%.

    The maximum output voltage for a SEPIC converter is:

    V V V

      D

    D   V DO MAX IN DMAX

    MAX D MAX( ) –   – –= +( ) 11

    1

    The maximum duty cycle of the LTC1871 is typically 92%.

    SEPIC Converter: The Peak and AverageInput Currents

    The control circuit in the LTC1871 is measuring the inputcurrent (either using the RDS(ON) of the power MOSFET orby means of a sense resistor in the MOSFET source), sothe output current needs to be reflected back to the inputin order to dimension the power MOSFET properly. Based

    on the fact that, ideally, the output power is equal to theinput power, the maximum input current for a SEPICconverter is:

    I I  D

    D

    The peak input current is

    I I  D

    D

    IN MAX O MAXMAX

    MAX

    IN PEAK O MAXMAX

    MAX

    ( ) ( )

    ( ) ( )

    •–

    :

    • •–

    =

    = + 

      

      

    1

    12 1

    χ

    The maximum duty cycle, DMAX, should be calculated atminimum VIN.

    The constant ‘χ’ represents the fraction of ripple current inthe inductor relative to its maximum value. For example, if30% ripple current is chosen, then χ = 0.30 and the peakcurrent is 15% greater than the average.

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    Figures 17. SEPIC Converter Switching Waveforms

    17a. Input Inductor Current

    IINIL1

    SW

    ON

    SW

    OFF

    17b. Output Inductor Current

    IOIL2

    17c. DC Coupling Capacitor Current

    IO

    IIN

    IC1

    17e. Output Ripple Voltage

    VOUT(AC)

    ∆VESR

    RINGING DUE TOTOTAL INDUCTANCE(BOARD + CAP)

    ∆VCOUT

    17d. Diode Current

    IO

    ID1

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    It is worth noting here that SEPIC converters that operateat high duty cycles (i.e., that develop a high output voltagefrom a low input voltage) can have very high input cur-

    rents, relative to the output current. Be sure to check thatthe maximum load current will not overload the inputsupply.

    SEPIC Converter: Inductor Selection

    For most SEPIC applications the equal inductor values willfall in the range of 10µH to 100µH. Higher values willreduce the input ripple voltage and reduce the core loss.Lower inductor values are chosen to reduce physical sizeand improve transient response.

    Like the boost converter, the input current of the SEPICconverter is calculated at full load current and minimuminput voltage. The peak inductor current can be signifi-cantly higher than the output current, especially withsmaller inductors and lighter loads. The following formu-las assume CCM operation and calculate the maximumpeak inductor currents at minimum VIN:

    I I  V V

    V

    I I  V V

    V

    L PEAK O MAXO D

    IN MIN

    L PEAK O MAXIN MIN D

    IN MIN

    1

    2

    12

    12

    ( ) ( )( )

    ( ) ( )( )

    ( )

    • •

    • •

    = + 

      

      +

    = +  

       

    +

    χ

    χ

    The ripple current in the inductor is typically 20% to 40%(i.e., a range of ‘χ’ from 0.20 to 0.40) of the maximumaverage input current occurring at VIN(MIN) and IO(MAX)and ∆IL1  = ∆IL2. Expressing this ripple current as afunction of the output current results in the followingequations for calculating the inductor value:

    L

      V

    I f   D

    IN MIN

    L MAX= ∆( )

    •   •

    where

    I I  D

    DL O MAX

    MAX

    MAX

    :

    • •–

    ( )∆ = χ1

    By making L1 = L2 and winding them on the same core, thevalue of inductance in the equation above is replace by 2L

    due to mutual inductance. Doing this maintains the sameripple current and energy storage in the inductors. Forexample, a Coiltronix CTX10-4 is a 10µH inductor with twowindings. With the windings in parallel, 10µH inductanceis obtained with a current rating of 4A (the number of turnshasn’t changed, but the wire diameter has doubled).Splitting the two windings creates two 10µH inductorswith a current rating of 2A each. Therefore, substituting 2Lyields the following equation for coupled inductors:

    L L  V

    I f  D

    IN MIN

    LMAX1 2

    2= =

    ∆( )

    • •  •

    Specify the maximum inductor current to safely handle

    IL(PK)  specified in the equation above. The saturationcurrent rating for the inductor should be checked at theminimum input voltage (which results in the highestinductor current) and maximum output current.

    SEPIC Converter: Power MOSFET Selection

    The power MOSFET serves two purposes in the LTC1871:it represents the main switching element in the powerpath, and its RDS(ON)  represents the current sensingelement for the control loop. Important parameters for thepower MOSFET include the drain-to-source breakdown

    voltage (BVDSS), the threshold voltage (VGS(TH)), the on-resistance (RDS(ON)) versus gate-to-source voltage, thegate-to-source and gate-to-drain charges (QGS and QGD,respectively), the maximum drain current (ID(MAX)) andthe MOSFET’s thermal resistances (RTH(JC) and RTH(JA)).

    The gate drive voltage is set by the 5.2V INTVCC  lowdropout regulator. Consequently, logic-level thresholdMOSFETs should be used in most LTC1871 applications.If low input voltage operation is expected (e.g., supplyingpower from a lithium-ion battery), then sublogic-level

    threshold MOSFETs should be used.The maximum voltage that the MOSFET switch mustsustain during the off-time in a SEPIC converter is equal tothe sum of the input and output voltages (VO + VIN). As aresult, careful attention must be paid to the BVDSS speci-fications for the MOSFETs relative to the maximum actualswitch voltage in the application. Many logic-level devicesare limited to 30V or less. Check the switching waveformsdirectly across the drain and source terminals of the power

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    MOSFET to ensure the VDS remains below the maximumrating for the device.

    During the MOSFET’s on-time, the control circuit limits themaximum voltage drop across the power MOSFET toabout 150mV (at low duty cycle). The peak inductorcurrent is therefore limited to 150mV/RDS(ON). The rela-tionship between the maximum load current, duty cycleand the RDS(ON) of the power MOSFET is:

    R  V

    I   V V

    V

    DS ONSENSE MAX

    O MAXT   O D

    IN MIN

    ( )( )

    ( )

    ( )

    •≤+ 

        

        + 

      

       +

    1

    12

    1

    1χ ρ

    The VSENSE(MAX) term is typically 150mV at low duty cycleand is reduced to about 100mV at a duty cycle of 92% dueto slope compensation, as shown in Figure 8. The constant‘χ’ in the denominator represents the ripple current in theinductors relative to their maximum current. For example,if 30% ripple current is chosen, then χ = 0.30. The ρT termaccounts for the temperature coefficient of the RDS(ON) ofthe MOSFET, which is typically 0.4%/ °C. Figure 9 illus-trates the variation of normalized RDS(ON) over tempera-ture for a typical power MOSFET.

    Another method of choosing which power MOSFET to useis to check what the maximum output current is for a givenRDS(ON)  since MOSFET on-resistances are available indiscrete values.

    I  V

    R   V V

    V

    O MAXSENSE MAX

    DS ONT

      O D

    IN MIN

    ( )( )

    ( )

    ( )

    •≤+ 

        

        + 

      

       +

    1

    12

    1

    1χ ρ

    Calculating Power MOSFET Switching and ConductionLosses and Junction Temperatures

    In order to calculate the junction temperature of the powerMOSFET, the power dissipated by the device must beknown. This power dissipation is a function of the dutycycle, the load current and the junction temperature itself.As a result, some iterative calculation is normally requiredto determine a reasonably accurate value. Since the con-troller is using the MOSFET as both a switching and asensing element, care should be taken to ensure that theconverter is capable of delivering the required load current

    over all operating conditions (load, line and temperature)and for the worst-case specifications for VSENSE(MAX) andthe RDS(ON) of the MOSFET listed in the manufacturer’s

    data sheet.

    The power dissipated by the MOSFET in a SEPIC converteris:

     

    P I  D

    D  R D

    k V V I  D

    D  C f

    FET O MAXMAX

    MAXDS ON MAX T

    IN MIN O O MAXMAX

    MAXRSS

    =  

         

    + +( )

    ( ) ( )

    ( ).

    ( )

    •–

      • • •

    • • •–

      • •

    1

    1

    2

    1 85

    ρ

    The first term in the equation above represents the I2R

    losses in the device and the second term, the switchinglosses. The constant k = 1.7 is an empirical factor inverselyrelated to the gate drive current and has the dimension of1/current.

    From a known power dissipated in the power MOSFET, itsjunction temperature can be obtained using the followingformula:

    TJ = TA + PFET •RTH(JA)

    The RTH(JA) to be used in this equation normally includesthe RTH(JC) for the device plus the thermal resistance from

    the board to the ambient temperature in the enclosure.This value of TJ can then be used to check the originalassumption for the junction temperature in the iterativecalculation process.

    SEPIC Converter: Output Diode Selection

    To maximize efficiency, a fast-switching diode with lowforward drop and low reverse leakage is desired. Theoutput diode in a SEPIC converter conducts current duringthe switch off-time. The peak reverse voltage that the

    diode must withstand is equal to VIN(MAX)  + VO. Theaverage forward current in normal operation is equal to theoutput current, and the peak current is equal to:

    I I  V V

    VD PEAK O MAX

    O D

    IN MIN( ) ( )

    ( )• •= + 

        

        +

      

      1

    2  1

    χ

    The power dissipated by the diode is:

    PD = IO(MAX) • VD

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    and the diode junction temperature is:

    TJ = TA + PD • RTH(JA)

    The RTH(JA) to be used in this equation normally includesthe RTH(JC) for the device plus the thermal resistance fromthe board to the ambient temperature in the enclosure.

    SEPIC Converter: Output Capacitor Selection

    Because of the improved performance of today’s electro-lytic, tantalum and ceramic capacitors, engineers need toconsider the contributions of ESR (equivalent series resis-tance), ESL (equivalent series inductance) and the bulkcapacitance when choosing the correct component for agiven output ripple voltage. The effects of these threeparameters (ESR, ESL, and bulk C) on the output voltageripple waveform are illustrated in Figure 17 for a typicalcoupled-inductor SEPIC converter.

    The choice of component(s) begins with the maximumacceptable ripple voltage (expressed as a percentage ofthe output voltage), and how this ripple should be dividedbetween the ESR step and the charging/discharging ∆V.For the purpose of simplicity we will choose 2% for themaximum output ripple, to be divided equally between theESR step and the charging/discharging ∆V. This percent-

    age ripple will change, depending on the requirements ofthe application, and the equations provided below caneasily be modified.

    For a 1% contribution to the total ripple voltage, the ESRof the output capacitor can be determined using thefollowing equation:

    ESR  V

    ICOUT

    O

    D PEAK≤

     0 01. •

    ( )

    where:

    I I  V V

    VD PEAK O MAX

    O D

    IN MIN( ) ( )

    ( )• •= + 

        

        + +

     

      

      1

    2  1

    χ

    For the bulk C component, which also contributes 1% tothe total ripple:

    C  I

    V fOUT

    O MAX

    O≥   ( )

    . • •0 01

    For many designs it is possible to choose a single capaci-tor type that satisfies both the ESR and bulk C require-ments for the design. In certain demanding applications,

    however, the ripple voltage can be improved significantlyby connecting two or more types of capacitors in parallel.For example, using a low ESR ceramic capacitor canminimize the ESR step, while an electrolytic or tantalumcapacitor can be used to supply the required bulk C.

    Once the output capacitor ESR and bulk capacitance havebeen determined, the overall ripple voltage waveformshould be verified on a dedicated PC board (see BoardLayout section for more information on component place-ment). Lab breadboards generally suffer from excessive

    series inductance (due to inter-component wiring), andthese parasitics can make the switching waveforms looksignificantly worse than they would be on a properlydesigned PC board.

    The output capacitor in a SEPIC regulator experienceshigh RMS ripple currents, as shown in Figure 17. The RMSoutput capacitor ripple current is:

     I I  V

    VRMS COUT O MAX

    O

    IN MIN( ) ( )

    ( )•=

    Note that the ripple current ratings from capacitor manu-facturers are often based on only 2000 hours of life. Thismakes it advisable to further derate the capacitor or tochoose a capacitor rated at a higher temperature thanrequired. Several capacitors may also be placed in parallelto meet size or height requirements in the design.

    Manufacturers such as Nichicon, United Chemicon andSanyo should be considered for high performance through-hole capacitors. The OS-CON semiconductor dielectriccapacitor available from Sanyo has the lowest product of

    ESR and size of any aluminum electrolytic, at a somewhathigher price.

    In surface mount applications, multiple capacitors mayhave to be placed in parallel in order to meet the ESR orRMS current handling requirements of the application.Aluminum electrolytic and dry tantalum capacitors areboth available in surface mount packages. In the case oftantalum, it is critical that the capacitors have been surgetested for use in switching power supplies. An excellent

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    choice is AVX TPS series of surface mount tantalum. Also,ceramic capacitors are now available with extremely lowESR, ESL and high ripple current ratings.

    SEPIC Converter: Input Capacitor Selection

    The input capacitor of a SEPIC converter is less criticalthan the output capacitor due to the fact that an inductoris in series with the input and the input current waveformis triangular in shape. The input voltage source impedancedetermines the size of the input capacitor which is typicallyin the range of 10µF to 100µF. A low ESR capacitor isrecommended, although it is not as critical as for theoutput capacitor.

    The RMS input capacitor ripple current for a SEPIC con-verter is:

    I IRMS CIN L( )   •= ∆1

    12

    Please note that the input capacitor can see a very highsurge current when a battery is suddenly connected to theinput of the converter and solid tantalum capacitors canfail catastrophically under these conditions. Be sure tospecify surge-tested capacitors!

    SEPIC Converter: Selecting the DC Coupling Capacitor

    The coupling capacitor C1 in Figure 16 sees nearly arectangular current waveform as shown in Figure 17.During the switch off-time the current through C1 is IO(VO / VIN) while approximately –IO flows during the on-time.This current waveform creates a triangular ripple voltageon C1:

    ∆ =+ +

    −V  I

    C f

    V

    V V VC P P

    O MAX   O

    IN O D1

    1( )

    ( )

    ••

    The maximum voltage on C1 is then:

    V V  V

    C MAX INC P P

    11

    2( )

    ( )= + ∆   −

    which is typically close to VIN(MAX). The ripple currentthrough C1 is:

    I I   V VV

    RMS C O MAXO D

    IN MIN( ) ( )

    ( )•1  =   +

    The value chosen for the DC coupling capacitor normallystarts with the minimum value that will satisfy 1) the RMScurrent requirement and 2) the peak voltage requirement(typically close to VIN). Low ESR ceramic and tantalumcapacitors work well here.

    SEPIC Converter Design Example

    The design example given here will be for the circuit shownin Figure 18. The input voltage is 5V to 15V and the outputis 12V at a maximum load current of 1.5A (2A peak).

    1. The duty cycle range is:

    D  V V

    V V V  toO D

    IN O D=

      ++ +

      

          = 45 5 71 4. % . %

    2. The operating mode chosen is pulse skipping, so theMODE/SYNC pin is shorted to INTVCC.

    3. The operating frequency is chosen to be 300kHz to

    reduce the size of the inductors; the resistor from theFREQ pin to ground is 80k.

    4. An inductor ripple current of 40% is chosen, so the peakinput current (which is also the minimum saturationcurrent) is:

    I I  V V

    V

    A

    L PEAK O MAXO D

    IN MIN1   1

    2

    1  0 4

    2  1 5

      12 0 5

    5  4 5

    ( ) ( )( )

    • •

    .• . •

      ..

    = +  

         

      +

    = +  

         

      +=

    χ

    The inductor ripple current is:

    ∆ =

    = =

    I I  D

    D

    A

    L O MAXMAX

    MAXχ • •

    . • . •  .

    – .  .

    ( )1

    0 4 1 5  0 714

    1 0 714  1 5

    APPLICATIO S I FOR ATIO      W    U U    U

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    LTC1871

    RUN

    ITH

    FB

    FREQ

    MODE/SYNC

    SENSE

    VIN

    INTVCC

    GATE

    GND

    1

    2

    3

    4

    5

    10

    9

    8

    7

    6

    LTC1871

    RT80.6k

    1%

    R112.1k

    1%R2105k

    1%

    R31M

    CVCC4.7µFX5R

    CIN47µF

    M1

    CIN, COUT1: KEMET T495X476K020ASCDC, COUT2: TAIYO YUDEN TMK432BJ106MMD1: INTERNATIONAL RECTIFIER 30BQ040

    D1

    L1*

    L2*

    RC33k

    CC16.8nF

    CC247pF

    COUT147µF20V×2

    VIN4.5V to 15V

    VOUT12V1.5A(2A PEAK)

    GND1871 F018a

    +COUT210µF25VX5R×2

    L1, L2: BH ELECTRONICS BH510-1007 (*COUPLED INDUCTORS)M1: INTERNATIONAL RECTIFIER IRF7811W

    CDC10µF25VX5R

    +

    Figure 18a. 4.5V to 15V Input, 12V/2A Output SEPIC Converter

    OUTPUT CURRENT (A)

    50

        E    F    F    I    C    I    E    N    C    Y

        (    %    )

    55

    60

    90

    85

    80

    75

    70

    65

    95

    0.001 0.1 1 10

    1871 F18b

    450.01

    100

    VIN = 4.5V

    VIN

     = 15V

    VIN = 12V

    VO = 12VMODE = INTVCC

    Figure 18b. SEPIC Efficiency vs Output Current

    APPLICATIO S I FOR ATIO      W    U U    U

    And so the inductor value is:

    L  V

    I f

      D

    k

      HIN MIN

    LMAX=

    ∆  = = µ( )

    • •

      •

    • . •

      • .

    2

    5

    2 1 5 300

      0 714 4

    The component chosen is a BH Electronics BH510-1007, which has a saturation current of 8A.

    5. With an minimum input voltage of 5V, only logic-levelpower MOSFETs should be considered. Because themaximum duty cycle is 71.4%, the maximum SENSEpin threshold voltage is reduced from its low duty cycletypical value of 150mV to approximately 120mV.Assuming a MOSFET junction temperature of 125°C,the room temperature MOSFET RDS(ON) should be less

    than:

    R  V

    I   V V

    V

    m

    DS ONSENSE MAX

    O MAXT

      O D

    IN MIN

    ( )( )

    ( )

    ( )

    .

    .  •

    . • .  •

    .  .

    ≤+ 

     

       

     

        + 

     

     

       +

    =  

          +

    = Ω

    1

    1

    2

    1

    1

    0 12

    1 5

    1

    1 2 1 5

    1

    12 5

    5  1

    12 7

    χ ρ

    For a SEPIC converter, the switch BVDSS rating must begreater than VIN(MAX) + VO, or 27V. This comes close toan IRF7811W, which is rated to 30V, and has a maxi-mum room temperature RDS(ON) of 12mΩ at VGS = 4.5V.

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    LTC1871

    VOUT (AC)200mV/DIV

    IOUT0.5A/DIV

    Figure 19. LTC1871 SEPIC Converter Load Step Response

    VIN = 4.5VVOUT = 12V

    VOUT (AC)200mV/DIV

    IOUT0.5A/DIV

    VIN = 15VVOUT = 12V

    50µs/DIV 1871 F19a 50µs/DIV 1871 F19b

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    6. The diode for this design must handle a maximum DC

    output current of 2A and be rated for a minimumreverse voltage of VIN + VOUT, or 27V. A 3A, 40V diodefrom International Rectifier (30BQ040) is chosen for itssmall size, relatively low forward drop and acceptablereverse leakage at high temp.

    7. The output capacitor usually consists of a high valuedbulk C connected in parallel with a lower valued, lowESR ceramic. Based on a maximum output ripplevoltage of 1%, or 120mV, the bulk C needs to be greaterthan:

    C   IV f

    A

    V kHz  F

    OUT OUT MAX

    OUT≥ =

    = µ

    ( ). • •

    .

    . • •

    0 01

    1 5

    0 01 12 300  41

    The RMS ripple current rating for this capacitor needsto exceed:

    I I  V

    V

    A   VV

      A

    RMS COUT O MAXO

    IN MIN( ) ( )

    ( )•

    . • .

    ≥ =

    =1 5   125   2 3

    To satisfy this high RMS current demand, two 47µFKemet capacitors (T495X476K020AS) are required. Asa result, the output ripple voltage is a low 50mV to60mV. In parallel with these tantalums, two 10µF, lowESR (X5R) Taiyo Yuden ceramic capacitors(TMK432BJ106MM) are added for HF noise reduction.

    Check the output ripple with a single oscilloscope probe

    connected directly across the output capacitor termi-nals, where the HF switching currents flow.

    8. The choice of an input capacitor for a SEPIC converterdepends on the impedance of the source supply and theamount of input ripple the converter will safely tolerate.For this particular design and lab setup, a single 47µFKemet tantalum capacitor (T495X476K020AS) is ad-equate. As with the output node, check the input ripplewith