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December 8, 2008
LM5116Wide Range Synchronous Buck ControllerGeneral DescriptionThe LM5116 is a synchronous buck controller intended forstep-down regulator applications from a high voltage or widelyvarying input supply. The control method is based upon cur-rent mode control utilizing an emulated current ramp. Currentmode control provides inherent line feed-forward, cycle bycycle current limiting and ease of loop compensation. The useof an emulated control ramp reduces noise sensitivity of thepulse-width modulation circuit, allowing reliable control ofvery small duty cycles necessary in high input voltage appli-cations. The operating frequency is programmable from50kHz to 1MHz. The LM5116 drives external high-side andlow-side NMOS power switches with adaptive dead-time con-trol. A user-selectable diode emulation mode enables discon-tinuous mode operation for improved efficiency at light loadconditions. A low quiescent current shutdown disables thecontroller and consumes less than 10µA of total input current.Additional features include a high voltage bias regulator, au-tomatic switch-over to external bias for improved efficiency,thermal shutdown, frequency synchronization, cycle by cyclecurrent limit and adjustable line under-voltage lockout. Thedevice is available in a power enhanced TSSOP-20 packagefeaturing an exposed die attach pad to aid thermal dissipation.
DEMB Output Current DEMB = 0V, SS = 1.25V 1.6 2.7 3.8 µA
DEMB Output Current DEMB =0V, SS = 2.8V 28 38 48 µA
DEMB Output Current DEMB = 0V, SS = Regulated
45 65 85 µA
LO Gate Driver
VOLL LO Low-state Output Voltage ILO = 100mA 0.08 0.17 V
VOHL LO High-state Output Voltage ILO = -100mA, VOHL = VCC -
LO Rise Time C-load = 1000pF 18 ns
LO Fall Time C-load = 1000pF 12 ns
IOHL Peak LO Source Current VLO = 0V 1.8 A
IOLL Peak LO Sink Current VLO = VCC 3.5 A
Symbol Parameter Conditions Min Typ Max Units
HO Gate Driver
VOLH HO Low-state Output Voltage IHO = 100mA 0.17 0.27 V
VOHH HO High-state Output Voltage IHO = -100mA, VOHH = VHB –
HO Rise Time C-load = 1000pF 19 ns
HO High-side Fall Time C-load = 1000pF 13 ns
IOHH Peak HO Source Current VHO = 0V 1 A
IOLH Peak HO Sink Current VHO = VCC 2.2 A
HB to SW under-voltage 3 V
LO Fall to HO Rise Delay C-load = 0 75 ns
HO Fall to LO Rise Delay C-load = 0 70 ns
TSD Thermal Shutdown Rising 170 °C
Thermal Shutdown Hysteresis 15 °C
θJAJunction to Ambient 40 °C/W
θJCJunction to Case 4 °C/W
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operationof the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,see the Electrical Characteristics tables.
Note 2: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. LO, HO and HB are rated at 1kV. 2kV rating for all pinsexcept VIN which is rated for 1.5kV.
Note 3: These pins must not exceed VIN.
Typical Performance Characteristics
Typical Application Circuit Efficiency
Driver Source Current vs VCC
Driver Dead-time vs Temperature
HO High RDS(ON) vs VCC
Driver Sink Current vs VCC
HO Low RDS(ON) vs VCC
LO High RDS(ON) vs VCC
EN Input Threshold vs Temperature
LO Low RDS(ON) vs VCC
HB to SW UVLO vs Temperature
Forced HO Off-time vs TemperatureVCCX = 5V
HB DC Bias Current vs Temperature
Frequency vs RT
Error Amp Gain vs Frequency
Frequency vs Temperature
Error Amp Phase vs Frequency
Frequency vs Temperature
Current Limit Threshold vs Temperature
VIN Operating Current vs Temperature
VCC vs Temperature
VCC UVLO vs Temperature
VCC vs VIN
VCC vs ICC
VCCX Switch RDS(ON) vs VCCX
Block Diagram and Typical Application Circuit
Detailed Operating DescriptionThe LM5116 high voltage switching regulator features all ofthe functions necessary to implement an efficient high voltagebuck regulator using a minimum of external components. Thiseasy to use regulator integrates high-side and low-side MOS-FET drivers capable of supplying peak currents of 2 Amps.The regulator control method is based on current mode con-trol utilizing an emulated current ramp. Emulated peak currentmode control provides inherent line feed-forward, cycle bycycle current limiting and ease of loop compensation. The useof an emulated control ramp reduces noise sensitivity of thepulse-width modulation circuit, allowing reliable processing ofthe very small duty cycles necessary in high input voltage ap-plications. The operating frequency is user programmablefrom 50kHz to 1MHz. An oscillator/synchronization pin allowsthe operating frequency to be set by a single resistor or syn-chronized to an external clock. Fault protection features in-clude current limiting, thermal shutdown and remote shut-down capability. An under-voltage lockout input allowsregulator shutdown when the input voltage is below a userselected threshold, and an enable function will put the regu-lator into an extremely low current shutdown via the enableinput. The TSSOP-20EP package features an exposed padto aid in thermal dissipation.
High Voltage Start-Up RegulatorThe LM5116 contains a dual mode internal high voltage start-up regulator that provides the VCC bias supply for the PWMcontroller and a boot-strap gate drive for the high-side buckMOSFET. The input pin (VIN) can be connected directly to aninput voltage source as high as 100 volts. For input voltagesbelow 10.6V, a low dropout switch connects VCC directly toVIN. In this supply range, VCC is approximately equal to VIN.For VIN voltages greater than 10.6V, the low dropout switchis disabled and the VCC regulator is enabled to maintain VCCat approximately 7.4V. The wide operating range of 6V to100V is achieved through the use of this dual mode regulator.
Upon power-up, the regulator sources current into the capac-itor connected to the VCC pin. When the voltage at the VCCpin exceeds 4.5V and the UVLO pin is greater than 1.215V,the output switch is enabled and a soft-start sequence begins.The output switch remains enabled until VCC falls below4.5V, EN is pulled low, the UVLO pin falls below 1.215V orthe die temperature exceeds the thermal limit threshold.
FIGURE 2. VCCX Bias Supply with Additional InductorWinding
An output voltage derived bias supply can be applied to theVCCX pin to reduce the IC power dissipation. If the bias sup-ply voltage is greater than 4.5V, the internal regulator willessentially shut off, reducing the IC power dissipation. The
VCC regulator series pass transistor includes a diode be-tween VCC and VIN that should not be forward biased innormal operation. For an output voltage between 5V and 15V,VOUT can be connected directly to VCCX. For VOUT < 5V,a bias winding on the output inductor can be added to VOUT.If the bias winding can supply VCCX greater than VIN, anexternal blocking diode is required from the input power sup-ply to the VIN pin to prevent VCC from discharging into theinput supply.
The output of the VCC regulator is current limited to 15 mAminimum. The VCC current is determined by the MOSFETgate charge, switching frequency and quiescent current (seeMOSFETs section in the Application Information). To ensurestart-up, the VCC current should be less than 15 mA. TheVCC current may exceed 15 mA during normal run when VC-CX is used, as long as the start-up requirement is met.
FIGURE 3. Input Blocking Diode for VCCX > VIN
In high voltage applications extra care should be taken to en-sure the VIN pin does not exceed the absolute maximumvoltage rating of 100V. During line or load transients, voltageringing on the VIN line that exceeds the Absolute MaximumRatings can damage the IC. Both careful PC board layout andthe use of quality bypass capacitors located close to the VINand GND pins are essential.
EnableThe LM5116 contains an enable function allowing a very lowinput current shutdown. If the enable pin is pulled below 0.5V,the regulator enters shutdown, drawing less than 10µA fromthe VIN pin. Raising the EN input above 3.3V returns the reg-ulator to normal operation. The EN pin can be tied directly toVIN if this function is not needed. It must not be left floating.A 1MΩ pull-up resistor to VIN can be used to interface withan open collector control signal.
FIGURE 4. Enable Circuit
FIGURE 5. EN Bias Current vs Voltage
UVLOAn under-voltage lockout pin is provided to disable the regu-lator without entering shutdown. If the UVLO pin is pulledbelow 1.215V, the regulator enters a standby mode of oper-ation with the soft-start capacitor discharged and outputsdisabled, but with the VCC regulator running. If the UVLO in-put is pulled above 1.215V, the controller will resume normaloperation. A voltage divider from input to ground can be usedto set a VIN threshold to disable the supply in brown-out con-ditions or for low input faults. The UVLO pin has a 5 µA internalpull up current that allows this pin to left open if the input un-der-voltage lockout function is not needed. For applicationswhich require fast on/off cycling, the UVLO pin with an opencollector control signal may be used to ensure proper start-upsequencing.
The UVLO pin is also used to implement a “hiccup” currentlimit. If a current limit fault exists for more than 256 consecu-tive clock cycles, the UVLO pin will be internally pulled downto 200 mV and then released, and a new SS cycle initiated.A capacitor to ground connected to the UVLO pin will set thetiming for hiccup mode current limit. When this feature is usedin conjunction with the voltage divider, a diode across the topresistor may be used to discharge the capacitor in the eventof an input under-voltage condition. There is a 5 µs filter at theinput to the fault comparator. At higher switching frequency(greater than approximately 250 kHz) the hiccup timer maybe disabled if the fault capacitor is not used.
Oscillator and Sync CapabilityThe LM5116 oscillator frequency is set by a single externalresistor connected between the RT/SYNC pin and the AGNDpin. The resistor should be located very close to the deviceand connected directly to the pins of the IC (RT/SYNC andAGND). To set a desired oscillator frequency (fSW), the nec-essary value for the resistor can be calculated from the fol-lowing equation:
Where T = 1 / fSW and RT is in ohms. 450ns represents thefixed minimum off time.
The LM5116WG oscillator has a maximum programmablefrequency that is dependent on the VCC voltage. If VCC isabove 6V, the frequency can be programmed up to 1 MHz. IfVCCX is used to bias VCC and VCCX < 6V, the maximumprogrammable oscillator frequency is 750 kHz.
The RT/SYNC pin can be used to synchronize the internaloscillator to an external clock. The external clock must be ahigher frequency than the free-running frequency set by theRT resistor. The internal oscillator can be synchronized to anexternal clock by AC coupling a positive edge into the RT/SYNC pin. The voltage at the RT/SYNC pin is nominally1.215V and must exceed 4V to trip the internal synchroniza-tion pulse detection. A 5V amplitude signal and 100pF cou-pling capacitor are recommended. The free-running frequen-cy should be set nominally 15% below the external clock.Synchronizing above twice the free-running frequency mayresult in abnormal behavior of the pulse width modulator.
Error Amplifier and PWM
ComparatorThe internal high-gain error amplifier generates an error sig-nal proportional to the difference between the regulated out-put voltage and an internal precision reference (1.215V). Theoutput of the error amplifier is connected to the COMP pinallowing the user to provide loop compensation components,generally a type II network. This network creates a pole atvery low frequency, a mid-band zero, and a noise reducinghigh frequency pole. The PWM comparator compares theemulated current sense signal from the RAMP generator tothe error amplifier output voltage at the COMP pin.
Ramp GeneratorThe ramp signal used in the pulse width modulator for currentmode control is typically derived directly from the buck switchcurrent. This switch current corresponds to the positive slopeportion of the inductor current. Using this signal for the PWMramp simplifies the control loop transfer function to a singlepole response and provides inherent input voltage feed-for-ward compensation. The disadvantage of using the buckswitch current signal for PWM control is the large leadingedge spike due to circuit parasitics that must be filtered orblanked. Also, the current measurement may introduce sig-nificant propagation delays. The filtering, blanking time andpropagation delay limit the minimal achievable pulse width. Inapplications where the input voltage may be relatively largein comparison to the output voltage, controlling small pulsewidths and duty cycles is necessary for regulation. TheLM5116 utilizes a unique ramp generator which does not ac-tually measure the buck switch current but rather reconstructsthe signal. Representing or emulating the inductor currentprovides a ramp signal to the PWM comparator that is free ofleading edge spikes and measurement or filtering delays. Thecurrent reconstruction is comprised of two elements, a sam-ple-and-hold DC level and an emulated current ramp.
FIGURE 6. Composition of Current Sense Signal
The sample-and-hold DC level is derived from a measure-ment of the recirculating current through either the low-sideMOSFET or current sense resistor. The voltage level acrossthe MOSFET or sense resistor is sampled and held just priorto the onset of the next conduction interval of the buck switch.The current sensing and sample-and-hold provide the DClevel of the reconstructed current signal. The positive slopeinductor current ramp is emulated by an external capacitorconnected from the RAMP pin to the AGND and an internalvoltage controlled current source. The ramp current sourcethat emulates the inductor current is a function of the VIN andVOUT voltages per the following equation:
IR = 5µA/V x (VIN-VOUT) + 25µA
Proper selection of the RAMP capacitor (CRAMP) depends up-on the value of the output inductor (L) and the current senseresistor (RS). For proper current emulation, the DC sampleand hold value and the ramp amplitude must have the samedependence on the load current. That is:
Where gm is the ramp generator transconductance (5µA/V)and A is the current sense amplifier gain (10V/V). The rampcapacitor should be located very close to the device and con-nected directly to the pins of the IC (RAMP and AGND).
The difference between the average inductor current and theDC value of the sampled inductor current can cause instabilityfor certain operating conditions. This instability is known assub-harmonic oscillation, which occurs when the inductor rip-ple current does not return to its initial value by the start ofnext switching cycle. Sub-harmonic oscillation is normallycharacterized by observing alternating wide and narrow puls-es at the switch node. Adding a fixed slope voltage ramp(slope compensation) to the current sense signal preventsthis oscillation. The 25 µA of offset current provided from theemulated current source adds the optimal slope compensa-tion to the ramp signal for a 5V output. For higher outputvoltages, additional slope compensation may be required. In
these applications, a resistor is added between RAMP andVCC to increase the ramp slope compensation.
FIGURE 7. RDS(ON) Current Sensing without DiodeEmulation
The DC current sample is obtained using the CS and CSGpins connected to either a source sense resistor (RS) or theRDS(ON) of the low-side MOSFET. For RDS(ON) sensing, RS =RDS(ON) of the low-side MOSFET. In this case it is sometimeshelpful to adjust the current sense amplifier gain (A) to a lowervalue in order to obtain the desired current limit. Adding ex-ternal resistors RG in series with CS and CSG, the currentsense amplifier gain A becomes:
Current LimitThe LM5116 contains a current limit monitoring scheme toprotect the circuit from possible over-current conditions.When set correctly, the emulated current sense signal is pro-portional to the buck switch current with a scale factor deter-mined by the current limit sense resistor. The emulated rampsignal is applied to the current limit comparator. If the emu-lated ramp signal exceeds 1.6V, the current cycle is termi-nated (cycle-by-cycle current limiting). Since the rampamplitude is proportional to VIN - VOUT, if VOUT is shorted, there
is an immediate reduction in duty cycle. To further protect theexternal switches during prolonged current limit conditions,an internal counter counts clock pulses when in current limit.When the counter detects 256 consecutive clock cycles, theregulator enters a low power dissipation hiccup mode of cur-rent limit. The regulator is shut down by momentarily pullingUVLO low, and the soft-start capacitor discharged. The reg-ulator is restarted with a full soft-start cycle once UVLOcharges back to 1.215V. This process is repeated until thefault is removed. The hiccup off-time can be controlled by acapacitor to ground on the UVLO pin. In applications with low
output inductance and high input voltage, the switch currentmay overshoot due to the propagation delay of the currentlimit comparator. If an overshoot should occur, the sample-and-hold circuit will detect the excess recirculating current. Ifthe sample-and-hold DC level exceeds the internal currentlimit threshold, the buck switch will be disabled and skip puls-es until the current has decayed below the current limit thresh-old. This approach prevents current runaway conditions dueto propagation delays or inductor saturation since the inductorcurrent is forced to decay following any current overshoot.
FIGURE 8. Current Limit and Ramp Circuit
Using a current sense resistor in the source of the low-sideMOSFET provides superior current limit accuracy comparedto RDS(ON) sensing. RDS(ON) sensing is far less accurate dueto the large variation of MOSFET RDS(ON) with temperatureand part-to-part variation. The CS and CSG pins should beKelvin connected to the current sense resistor or MOSFETdrain and source.
The peak current which triggers the current limit comparatoris:
Where tON is the on-time of the high-side MOSFET. The 1.1Vthreshold is the difference between the 1.6V reference at thecurrent limit comparator and the 0.5V offset at the currentsense amplifier. This offset at the current sense amplifier al-lows the inductor ripple current to go negative by 0.5V / (A xRS) when running full synchronous operation.
Current limit hysteresis prevents chatter around the thresholdwhen VCCX is powered from VOUT. When 4.5V < VCC <5.8V, the 1.6V reference is increased to 1.72V. The peak cur-rent which triggers the current limit comparator becomes:
This has the effect of a 10% fold-back of the peak currentduring a short circuit when VCCX is powered from a 5V out-put.
Soft-Start and Diode EmulationThe soft-start feature allows the regulator to gradually reachthe initial steady state operating point, thus reducing start-upstresses and surges. The LM5116 will regulate the FB pin tothe SS pin voltage or the internal 1.215V reference, whicheveris lower. At the beginning of the soft-start sequence when SS= 0V, the internal 10µA soft-start current source gradually in-creases the voltage of an external soft-start capacitor (CSS)connected to the SS pin resulting in a gradual rise of FB andthe output voltage.
FIGURE 9. Diode Emulation Control
During this initial charging of CSS to the internal referencevoltage, the LM5116 will force diode emulation. That is, thelow-side MOSFET will turn off for the remainder of a cycle ifthe sensed inductor current becomes negative. The inductorcurrent is sensed by monitoring the voltage between SW andDEMB. As the SS capacitor continues to charge beyond1.215V to 3V, the DEMB bias current will increase from 0µAup to 40µA. With the use of an external DEMB resistor(RDEMB), the current sense threshold for diode emulation willincrease resulting in the gradual transition to synchronousoperation. Forcing diode emulation during soft-start allowsthe LM5116 to start up into a pre-biased output without un-necessarily discharging the output capacitor. Full syn-chronous operation is obtained if the DEMB pin is alwaysbiased to a higher potential than the SW pin when LO is high.RDEMB = 10kΩ will bias the DEMB pin to 0.45V minimum,which is adequate for most applications. The DEMB bias po-tential should always be kept below 2V. At very light loadswith larger values of output inductance and MOSFET capac-itance, the switch voltage may fall slowly. If the SW voltagedoes not fall below the DEMB threshold before the end of theHO fall to LO rise dead-time, switching will default to diodeemulation mode. When RDEMB = 0Ω, the LM5116 will alwaysrun in diode emulation.
Once SS charges to 3V the SS latch is set, increasing theDEMB bias current to 65µA. An amplifier is enabled that reg-ulates SS to 160mV above the FB voltage. This feature canprevent overshoot of the output voltage in the event the outputvoltage momentarily dips out of regulation. When a fault isdetected (VCC under-voltage, UVLO pin < 1.215, or EN = 0V)the soft-start capacitor is discharged. Once the fault conditionis no longer present, a new soft-start sequence begins.
HO OuputThe LM5116 contains a high current, high-side driver and as-sociated high voltage level shift. This gate driver circuit worksin conjunction with an external diode and bootstrap capacitor.A 1 µF ceramic capacitor, connected with short traces be-tween the HB pin and SW pin, is recommended. During theoff-time of the high-side MOSFET, the SW pin voltage is ap-proximately -0.5V and the bootstrap capacitor charges fromVCC through the external bootstrap diode. When operatingwith a high PWM duty cycle, the buck switch will be forced offeach cycle for 450 ns to ensure that the bootstrap capacitoris recharged.
The LO and HO outputs are controlled with an adaptive dead-time methodology which insures that both outputs are neverenabled at the same time. When the controller commands HOto be enabled, the adaptive block first disables LO and waitsfor the LO voltage to drop below approximately 25% of VCC.HO is then enabled after a small delay. Similarly, when HOturns off, LO waits until the SW voltage has fallen to ½ of VCC.LO is then enabled after a small delay. In the event that SWdoes not fall within approximately 150 ns, LO is asserted high.This methodology insures adequate dead-time for any sizeMOSFET.
Thermal ProtectionInternal thermal shutdown circuitry is provided to protect theintegrated circuit in the event the maximum junction temper-ature is exceeded. When activated, typically at 170°C, thecontroller is forced into a low power reset state, disabling theoutput driver and the bias regulator. This is designed to pre-vent catastrophic failures from accidental device overheating.
The procedure for calculating the external components is il-lustrated with the following design example. The Bill of Mate-rials for this design is listed in Table 1. The circuit shown inFigure 16 is configured for the following specifications:
• Output voltage = 5V
• Input voltage = 7V to 60V
• Maximum load current = 7A
• Switching frequency = 250kHz
Simplified equations are used as a general guideline for thedesign method. Comprehensive equations are provided atthe end of this section.
RT sets the oscillator switching frequency. Generally, higherfrequency applications are smaller but have higher losses.Operation at 250kHz was selected for this example as a rea-sonable compromise for both small size and high efficiency.The value of RT for 250kHz switching frequency can be cal-culated as follows:
The nearest standard value of 12.4kΩ was chosen for RT.
The inductor value is determined based on the operating fre-quency, load current, ripple current and the input and outputvoltages.
FIGURE 10. Inductor Current
Knowing the switching frequency (fSW), maximum ripple cur-rent (IPP), maximum input voltage (VIN(MAX)) and the nominaloutput voltage (VOUT), the inductor value can be calculated:
The maximum ripple current occurs at the maximum inputvoltage. Typically, IPP is 20% to 40% of the full load current.When running diode emulation mode, the maximum ripplecurrent should be less than twice the minimum load current.For full synchronous operation, higher ripple current is ac-
ceptable. Higher ripple current allows for a smaller inductorsize, but places more of a burden on the output capacitor tosmooth the ripple current for low output ripple voltage. For thisexample, 40% ripple current was chosen for a smaller sizedinductor.
The nearest standard value of 6µH will be used. The inductormust be rated for the peak current to prevent saturation. Dur-ing normal operation, the peak current occurs at maximumload current plus maximum ripple. During overload conditionswith properly scaled component values, the peak current islimited to VCS(TH) / RS (See next section). At the maximuminput voltage with a shorted output, the valley current must fallbelow VCS(TH) / RS before the high-side MOSFET is allowedto turn on. The peak current in steady state will increase toVIN(MAX) x tON(min) / L above this level. The chosen inductormust be evaluated for this condition, especially at elevatedtemperature where the saturation current rating may drop sig-nificantly.
CURRENT SENSE RESISTOR
The current limit is set by the current sense resistor value(RS).
For a 5V output, the maximum current sense signal occurs atthe minimum input voltage, so RS is calculated from:
For this example VCCX = 0V, so VCS(TH) = 0.11V. The currentsense resistor is calculated as:
The next lowest standard value of 10mΩ was chosen for RS.
With the inductor and sense resistor value selected, the valueof the ramp capacitor (CRAMP) necessary for the emulationramp circuit is:
Where L is the value of the output inductor in Henrys, gm isthe ramp generator transconductance (5µA/V), and A is thecurrent sense amplifier gain (10V/V). For the 5V output designexample, the ramp capacitor is calculated as:
The next lowest standard value of 270pF was selected forCRAMP. A COG type capacitor with 5% or better tolerance isrecommended.
The output capacitors smooth the inductor ripple current andprovide a source of charge for transient loading conditions.For this design example, five 100µF ceramic capacitorswhere selected. Ceramic capacitors provide very low equiv-alent series resistance (ESR), but can exhibit a significantreduction in capacitance with DC bias. From themanufacturer’s data, the ESR at 250kHz is 2mΩ / 5 =0.4mΩ, with a 36% reduction in capacitance at 5V. This isverified by measuring the output ripple voltage and frequencyresponse of the circuit. The fundamental component of theoutput ripple voltage is calculated as:
With typical values for the 5V design example:
The regulator supply voltage has a large source impedanceat the switching frequency. Good quality input capacitors arenecessary to limit the ripple voltage at the VIN pin while sup-plying most of the switch current during the on-time. When thebuck switch turns on, the current into the switch steps to thevalley of the inductor current waveform, ramps up to the peakvalue, and then drops to zero at turn-off. The input capacitorsshould be selected for RMS current rating and minimum ripplevoltage. A good approximation for the required ripple currentrating is IRMS > IOUT / 2.
Quality ceramic capacitors with a low ESR were selected forthe input filter. To allow for capacitor tolerances and voltagerating, four 2.2µF, 100V ceramic capacitors were used for thetypical application circuit. With ceramic capacitors, the inputripple voltage will be triangular and peak at 50% duty cycle.Taking into account the capacitance change with DC bias, theinput ripple voltage is approximated as:
When the converter is connected to an input power source, aresonant circuit is formed by the line impedance and the inputcapacitors. If step input voltage transients are expected nearthe maximum rating of the LM5116, a careful evaluation of theringing and possible overshoot at the device VIN pin shouldbe completed. To minimize overshoot make CIN > 10 x LIN.The characteristic source impedance and resonant frequencyare:
The converter exhibits a negative input impedance which islowest at the minimum input voltage:
The damping factor for the input filter is given by:
Where RIN is the input wiring resistance and ESR is the seriesresistance of the input capacitors. The term ZS / ZIN will alwaysbe negative due to ZIN.
When δ = 1, the input filter is critically damped. This may bedifficult to achieve with practical component values. With δ <0.2, the input filter will exhibit significant ringing. If δ is zero ornegative, there is not enough resistance in the circuit and theinput filter will sustain an oscillation. When operating near theminimum input voltage, an aluminum electrolytic capacitoracross CIN may be needed to damp the input for a typicalbench test setup. Any parallel capacitor should be evaluatedfor its RMS current rating. The current will split between theceramic and aluminum capacitors based on the relativeimpedance at the switching frequency.
The primary purpose of the VCC capacitor (CVCC) is to supplythe peak transient currents of the LO driver and bootstrapdiode (D1) as well as provide stability for the VCC regulator.These current peaks can be several amperes. The recom-mended value of CVCC should be no smaller than 0.47µF, andshould be a good quality, low ESR, ceramic capacitor locatedat the pins of the IC to minimize potentially damaging voltagetransients caused by trace inductance. A value of 1µF wasselected for this design.
The bootstrap capacitor (CHB) between the HB and SW pinssupplies the gate current to charge the high-side MOSFETgate at each cycle’s turn-on as well as supplying the recoverycharge for the bootstrap diode (D1). These current peaks canbe several amperes. The recommended value of the boot-strap capacitor is at least 0.1µF, and should be a good quality,low ESR, ceramic capacitor located at the pins of the IC tominimize potentially damaging voltage transients caused bytrace inductance. The absolute minimum value for the boot-strap capacitor is calculated as:
Where Qg is the high-side MOSFET gate charge and ΔVHB isthe tolerable voltage droop on CHB, which is typically less than5% of VCC. A value of 1µF was selected for this design.
SOFT START CAPACITOR
The capacitor at the SS pin (CSS) determines the soft-starttime, which is the time for the reference voltage and the outputvoltage to reach the final regulated value. The soft-start timetSS should be substantially longer than the time required tocharge COUT to VOUT at the maximum output current. To meetthis requirement:
tSS > VOUT x COUT / (ICURRENT LIMIT – IOUT)
The value of CSS for a given time is determined from:
For this application, a value of 0.01µF was chosen for a soft-start time of 1.2ms.
OUTPUT VOLTAGE DIVIDER
RFB1 and RFB2 set the output voltage level, the ratio of theseresistors is calculated from:
RFB1 is typically 1.21kΩ for a divider current of 1mA. The di-vider current can be reduced to 100µA with RFB1=12.1kΩ. Forthe 5V output design example used here, RFB1 = 1.21kΩ andRFB2 = 3.74kΩ.
A voltage divider and filter can be connected to the UVLO pinto set a minimum operating voltage VIN(MIN) for the regulator.If this feature is required, the following procedure can be usedto determine appropriate resistor values for RUV2, RUV1 andCFT.
1. RUV2 must be large enough such that in the event of acurrent limit, the internal UVLO switch can pull UVLO <200mV. This can be guaranteed if:
RUV2 > 500 x VIN(MAX)
Where VIN(MAX) is the maximum input voltage and RUV2is in ohms.
2. 2. With an appropriate value for RUV2, RUV1 can beselected using the following equation:
Where VIN(MIN) is the desired shutdown voltage.
3. Capacitor CFT provides filtering for the divider anddetermines the off-time of the “hiccup” duty cycle duringcurrent limit. When CFT is used in conjunction with thevoltage divider, a diode across the top resistor should beused to discharge CFT in the event of an input under-voltage condition.
If under-voltage shutdown is not required, RUV1 and RUV2 canbe eliminated and the off-time becomes:
The voltage at the UVLO pin should never exceed 16V whenusing an external set-point divider. It may be necessary toclamp the UVLO pin at high input voltages. For the designexample, RUV2 = 102kΩ and RUV1 = 21kΩ for a shut-downvoltage of 6.6V. If sustained short circuit protection is re-quired, CFT ≥ 1µF will limit the short circuit power dissipation.D2 may be installed when using CFT with RUV1 and RUV2.
Selection of the power MOSFETs is governed by the sametradeoffs as switching frequency. Breaking down the lossesin the high-side and low-side MOSFETs is one way to deter-mine relative efficiencies between different devices. Whenusing discrete SO-8 MOSFETs the LM5116 is most efficientfor output currents of 2A to 10A. Losses in the power MOS-FETs can be broken down into conduction loss, gate chargingloss, and switching loss. Conduction, or I2R loss PDC, is ap-proximately:
PDC(HO-MOSFET) = D x (IO2 x RDS(ON) x 1.3)
PDC(LO-MOSFET) = (1 - D) x (IO2 x RDS(ON) x 1.3)
Where D is the duty cycle. The factor 1.3 accounts for theincrease in MOSFET on-resistance due to heating. Alterna-tively, the factor of 1.3 can be ignored and the on-resistanceof the MOSFET can be estimated using the RDS(ON) vs Tem-perature curves in the MOSFET datasheet. Gate chargingloss, PGC, results from the current driving the gate capaci-tance of the power MOSFETs and is approximated as:
PGC = n x VCC x Qg x fSW
Qg refer to the total gate charge of an individual MOSFET,and ‘n’ is the number of MOSFETs. If different types of MOS-FETs are used, the ‘n’ term can be ignored and their gatecharges summed to form a cumulative Qg. Gate charge lossdiffers from conduction and switching losses in that the actualdissipation occurs in the LM5116 and not in the MOSFET it-self. Further loss in the LM5116 is incurred as the gate drivingcurrent is supplied by the internal linear regulator. The gatedrive current supplied by the VCC regulator is calculated as:
IGC = VCC x (Qgh + Qgl) x fSW
Where Qgh + Qgl represent the gate charge of the HO and LOMOSFETs at VGS = VCC. To ensure start-up, IGC should beless than the VCC current limit rating of 15mA minimum whenpowered by the internal 7.4V regulator. Failure to observe thisrating may result in excessive MOSFET heating and potentialdamage. The IGC run current may exceed 15 mA when VCCis powered by VCCX.
PSW = 0.5 x VIN x IO x (tR + tF) x fSW
Where tR and tF are the rise and fall times of the MOSFET.Switching loss is calculated for the high-side MOSFET only.Switching loss in the low-side MOSFET is negligible becausethe body diode of the low-side MOSFET turns on before theMOSFET itself, minimizing the voltage from drain to sourcebefore turn-on. For this example, the maximum drain-to-source voltage applied to either MOSFET is 60V. VCC pro-vides the drive voltage at the gate of the MOSFETs. Theselected MOSFETs must be able to withstand 60V plus anyringing from drain to source, and be able to handle at leastVCC plus ringing from gate to source. A good choice of MOS-FET for the 60V input design example is the Si7850DP. It hasan RDS(ON) of 20 mΩ, total gate charge of 14nC, and rise and
fall times of 10ns and 12ns respectively. In applications wherea high step-down ratio is maintained for normal operation, ef-ficiency may be optimized by choosing a high-side MOSFETwith lower Qg, and low-side MOSFET with lower RDS(ON).
For higher voltage MOSFETs which are not true logic level, itis important to use the UVLO feature. Choose a minimum op-erating voltage which is high enough for VCC and the boot-strap (HB) supply to fully enhance the MOSFET gates. Thiswill prevent operation in the linear region during power-on orpower-off which can result in MOSFET failure. Similar con-sideration must be made when powering VCCX from theoutput voltage. For the high-side MOSFET, the gate thresholdshould be considered and careful evaluation made if the gatethreshold voltage exceeds the HO driver UVLO.
A resistor-capacitor snubber network across the low-sideMOSFET reduces ringing and spikes at the switching node.Excessive ringing and spikes can cause erratic operation andcouple spikes and noise to the output. Selecting the valuesfor the snubber is best accomplished through empirical meth-ods. First, make sure the lead lengths for the snubber con-nections are very short. Start with a resistor value between5Ω and 50Ω. Increasing the value of the snubber capacitorresults in more damping, but higher snubber losses. Select aminimum value for the snubber capacitor that provides ade-quate damping of the spikes on the switch waveform at highload.
ERROR AMPLIFIER COMPENSATION
RCOMP, CCOMP and CHF configure the error amplifier gaincharacteristics to accomplish a stable voltage loop gain. Oneadvantage of current mode control is the ability to close theloop with only two feedback components, RCOMP and CCOMP.The voltage loop gain is the product of the modulator gain andthe error amplifier gain. For the 5V output design example,the modulator is treated as an ideal voltage-to-current con-verter. The DC modulator gain of the LM5116 can be modeledas:
DC Gain(MOD) = RLOAD / (A x RS)
The dominant low frequency pole of the modulator is deter-mined by the load resistance (RLOAD) and output capacitance(COUT). The corner frequency of this pole is:
fP(MOD) = 1 / (2π x RLOAD x COUT)
For RLOAD = 5V / 7A = 0.714Ω and COUT = 320µF (effective)then fP(MOD) = 700Hz
DC Gain(MOD) = 0.714Ω / (10 x 10mΩ) = 7.14 = 17dB
For the 5V design example the modulator gain vs. frequencycharacteristic was measured as shown in Figure 11.
FIGURE 11. Modulator Gain and Phase
Components RCOMP and CCOMP configure the error amplifieras a type II configuration. The DC gain of the amplifier is 80dBwhich has a pole at low frequency and a zero at fZEA = 1 /(2π x RCOMP x CCOMP). The error amplifier zero cancels themodulator pole leaving a single pole response at thecrossover frequency of the voltage loop. A single pole re-sponse at the crossover frequency yields a very stable loopwith 90° of phase margin. For the design example, a targetloop bandwidth (crossover frequency) of one-tenth theswitching frequency or 25kHz was selected. The compensa-tion network zero (fZEA) should be selected at least an orderof magnitude less than the target crossover frequency. Thisconstrains the product of RCOMP and CCOMP for a desiredcompensation network zero 1 / (2π x RCOMP x CCOMP) to be2.5kHz. Increasing RCOMP, while proportionally decreasingCCOMP, increases the error amp gain. Conversely, decreasingRCOMP while proportionally increasing CCOMP, decreases theerror amp gain. For the design example CCOMP was selectedas 3300pF and RCOMP was selected as 18kΩ. These valuesconfigure the compensation network zero at 2.7kHz. The er-ror amp gain at frequencies greater than fZEA is: RCOMP /RFB2, which is approximately 4.8 (13.6dB).
FIGURE 12. Error Amplifier Gain and Phase
The overall voltage loop gain can be predicted as the sum (indB) of the modulator gain and the error amp gain.
FIGURE 13. Overall Voltage Loop Gain and Phase
If a network analyzer is available, the modulator gain can bemeasured and the error amplifier gain can be configured forthe desired loop transfer function. If a network analyzer is notavailable, the error amplifier compensation components canbe designed with the guidelines given. Step load transienttests can be performed to verify acceptable performance. Thestep load goal is minimum overshoot with a damped re-sponse. CHF can be added to the compensation network todecrease noise susceptibility of the error amplifier. The valueof CHF must be sufficiently small since the addition of this ca-pacitor adds a pole in the error amplifier transfer function. Thispole must be well beyond the loop crossover frequency. Agood approximation of the location of the pole added by CHFis: fP2 = fZEA x CCOMP / CHF. The value of CHF was selected as100pF for the design example.
PCB LAYOUT AND THERMAL CONSIDERATIONS
In a buck regulator the primary switching loop consists of theinput capacitor, MOSFETs and current sense resistor. Mini-mizing the area of this loop reduces the stray inductance andminimizes noise and possible erratic operation. The input ca-pacitor should be placed as close as possible to the MOS-FETs, with the VIN side of the capacitor connected directly tothe high-side MOSFET drain, and the GND side of the ca-pacitor connected as close as possible to the low-side sourceor current sense resistor ground connection. A ground planein the PC board is recommended as a means to connect thequiet end (input voltage ground side) of the input filter capac-itors to the output filter capacitors and the PGND pin of theregulator. Connect all of the low power ground connections(CSS, RT, CRAMP) directly to the regulator AGND pin. Connectthe AGND and PGND pins together through to a topside cop-per area covering the entire underside of the device. Placeseveral vias in this underside copper area to the ground plane.
The highest power dissipating components are the two powerMOSFETs. The easiest way to determine the power dissipat-ed in the MOSFETs is to measure the total conversion losses(PIN - POUT), then subtract the power losses in the output in-ductor and any snubber resistors. The resulting power lossesare primarily in the switching MOSFETs.
If a snubber is used, the power loss can be estimated with anoscilloscope by observation of the resistor voltage drop atboth turn-on and turn-off transitions. Assuming that the RCtime constant is << 1 / fSW.
P = C x V2 x fSW
The regulator has an exposed thermal pad to aid power dis-sipation. Selecting MOSFETs with exposed pads will aid thepower dissipation of these devices. Careful attention to RDS
(ON) at high temperature should be observed. Also, at 250 kHz,a MOSFET with low gate capacitance will result in lowerswitching losses.
CURRENT SENSE RESISTOR AND RAMP CAPACITOR
T = 1 / fSW, gm = 5µA/V, A = 10V/V. IOUT is the maximum outputcurrent at current limit.
General Method for VOUT < 5V:
General Method for 5V < VOUT < 7.5V:
Best Performance Method:
This minimizes the current limit deviation due to changes inline voltage, while maintaining near optimal slope compen-sation.
Calculate optimal slope current, IOS = (VOUT / 3) x 10µA/V. Forexample, at VOUT = 7.5V, IOS = 25µA.
Calculate VRAMP at the nominal input voltage.
For VOUT > 7.5V, install a resistor from the RAMP pin to VCC.
FIGURE 14. RRAMP to VCC for VOUT > 7.5V
For VOUT < 7.5V, a negative VCC is required. This can bemade with a simple charge pump from the LO gate output.Install a resistor from the RAMP pin to the negative VCC.
FIGURE 15. RRAMP to -VCC for VOUT < 7.5V
If a large variation is expected in VCC, say for VIN < 11V, aZener regulator may be added to supply a constant voltagefor RRAMP.
MODULATOR TRANSFER FUNCTION
The following equations can be used to calculate the control-to-output transfer function:
Km is the effective DC gain of the modulating comparator. Theduty cycle D = VOUT / VIN. KSL is the proportional slope com-pensation term. VSL is the fixed slope compensation term.Slope compensation is set by mc, which is the ratio of the ex-ternal ramp to the natural ramp. The switching frequency
sampling gain is characterized by ωn and Q, which accountsfor the high frequency inductor pole.
For VSL without RRAMP, use IOS = 25 µA
For VSL with RRAMP to VCC, use IOS = 25 µA + VCC/RRAMP
For VSL with RRAMP to -VCC, use IOS = 25 µA - VCC/RRAMP
ERROR AMPLIFIER TRANSFER FUNCTION
The following equations are used to calculate the error am-plifier transfer function:
Where AOL = 10,000 (80dB) and ωBW = 2π x fBW. GEA(S) is theideal error amplifier gain, which is modified at DC and highfrequency by the open loop gain of the amplifier and the feed-back divider ratio.
TABLE 1. Bill of Materials for 7V-60V Input, 5V 7A Output, 250kHz
Serial Digital Interface (SDI) www.national.com/sdi Mil/Aero www.national.com/milaero
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