LAV firmware status

LAV firmware

LAV firmware statusFrancesco Gonnella Mauro Raggi23rd May 2012TDAQ Working Group MeetingLAV PP firmwareHigh and Low threshold crossing associationand Time correction (PP)Constant offset (done)Event reconstruction (done)Slewing (done, thanks to A. Bellotta)Deliver data to SL on a 32-bit bus23 May 2012Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy2OffsetCh. SelectorFIFO LFIFO HFIFO LFIFO HFIFO LFIFO HEvent FinderRAMData formatter & threshold retrieverRAMSlewing calculatorData transmitterto SLFrom TDCb64 blocks(128 FIFOs)OK2New channel modulesReduced logic utilizationDifferent High and Low modulesDifferent High and Low FIFO depth: 8 and 16 words23 May 2012Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy3Fine TimeTime StampData: 00112345TS: 00112344Data: 00112346Data: 00112347Data: 00112348TS: 00112345MegaWizard Fifo (8/16 words)Push FifoOutputFSMReady40-bit data22-bitdataEmptyfinire3Threshold retriever moduleParse 2x 32-bit input words:

Retrieve proper threshold values from RAM

Produce a formatted 72-bit word:

23 May 2012Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy432-bit Data inData formatter&Thresholdretriever72-bit Data outaddressoffsetclockStrobe inRead enableThresholdRAMaddressThrWEECSStrobe out31 3029 Block 2423 2019 Risetime 1211 87 Time(39:32) 0

31 Time(31:0) 071 Low Threshold 6059 High Threshold 4847 Risetime 4039 Time 0ok4High Level Synthesis Calculator23 May 2012Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy5Module realised using High Level Synthesis software by Antonio BellottaHLS calculator performing slewing calculation:

Working frequency: 160 MHzInput-output latency: 9 clkThroughput: 1 clkReasonable resources utilization

72-bit Data inHLSSlewing correction calculator 40-bit data outStrobe inStrobe outclock

Megawizard divider:Finire5Test benchData-stream has been generated through a Toy MC codePhysical muon-hit generation with proper rate (~1 MHz)H&L threshold (7 and 25 mV) crossing-time evaluationTDCB-like data stream production dumped to an ASCII filePost-synthesis simulation (within HDL designer)Successful integration of EDF from A. Bellotta Successful detection of all eventsSlewing corrected data match MC truth within 2 LSB (~200 ps)23 May 2012Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy6Simulation results (1/2)23 May 2012Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy7Global test of LAV firmwareA ~3.5s data stream corresponds to 100s of muon flux on LAVIt contains ~60 detectable events (with chosen threshold values)2.2 s additional time is needed to process data

Configuration 3.1s (511 clk)Data 3.5s (563 clk)

Output 2,2s (358 clk)

ok7Simulation results (2/2)23 May 2012Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy8Input-output latencyInput-output latency strongly depends on FIFO occupancyUncorrected-corrected latency is fixed to 9 clock cycles

Uncorrected outputCorrected outputEvent106.25 ns (17 clk)56ns (9 clk)ok8Resources utilizationOldWithout HLS and Full ErrorWith HLS and Full Error Family Stratix III Stratix III Device EP3SL110F1152C4 EP3SL110F1152C4 Logic utilization 28%18%20% Combinational ALUTs 20%10,353 / 86,000 ( 12% )11,141 / 86,000 ( 13% ) Memory ALUTs 0%0 / 43,000 ( 0% )40 / 43,000 ( < 1% ) Dedicated logic registers 24%14,008 / 86,000 ( 16% )14,413 / 86,000 ( 17% ) Total registers 14,00814,413 Total block memory bits 1%40,448 / 4,303,872 ( < 1% ) 41,984 / 4,303,872 ( < 1% ) DSP block 18-bit elements 0%0 / 288 ( 0 % ) 6 / 288 ( 2 % ) Total PLLs 0 / 8 ( 0 % ) 0 / 8 ( 0 % ) Total DLLs 0 / 4 ( 0 % ) 0 / 4 ( 0 % ) 23 May 2012Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy9OK932SL= FIFO32PP data Formatter4x (256x32) PP FIFOs2 copies of output FIFO

Communicate with PPs (at 120 MHz ?) Check errors Merge PP data for same event160 MHz32Data Write Formatterwrite data FIFO

Prepare single events Merge events into MEPs Write data FIFO160 MHz32QDR arbiter

Handle ECS R/W requests Handle MEP write requests Handle MEP read requests Handle other write (and read?) requests

160 MHz3232160 MHzData monitor log data FIFO

Monitor PP data and errors and prepare histograms Monitor SL primitives and prepare histograms Monitor received triggers and prepare histograms

Inter-TEL62 controllerInput/output data FIFOs

?3232ECS QDR interface323240 MHz120 MHzTTC Handler2 copies of trigger FIFO

Set/store timestamp Adjust timestamp (?) Decode trigger word Send triggers to PP40 MHzEither one or the other323232323232PP trigger primitive formatter[SD dependent]4x (256x32) PP FIFOs2 copies of output primitive FIFO

Communicate with PPs (at 120 MHz ?) Check errors Merge PP primitives160 MHzL0 Primitive Merger[SD dependent]output primitive FIFO

160 MHz3232L0 Primitive formatteroutput primitive FIFO Prepare MTP Prepare Ethernet frames Handle timeout Handle LEMO triggers

160 MHzData Read Formatter

Read data from QDR Prepare ethernet frames160 MHzTTCGbE controller

Handle data and trigger flows Handle test data flows Handle ARPECSGbE= 2012= 201332323232328PPAUX1616PPPPSL Firmware10OK10SL LAV Firmware Receive data from the 4 PP-FPGA;Sort dataGroup data into eventsCalculate trigger primitive fine time as the average of the times belonging to the same eventProduce properly formatted trigger primitives

1123 May 2012Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - ItalyPPPPPPPPFIFOFSMFSMSLsortgroupTrig. PrimitiveConclusionsStatus:We have a first version of the PP firmware,including computational partWe reduced the FPGA occupancy (from 28% to 20%)Firmware has been adapted to be integrated into TEL62 firmware

Things to do:Write PP-to-SL data transfer modules for LAV trigger primitiveWrite the trigger primitive generation HDL on SL FPGAIntegrate LAV sub-detector lib into main TEL62 firmwareMake some parameter programmable by CCPC on TEL62:Time Stamp resolution (overlap with Fine Time)Channel mappingHigh an Low threshold matching window23 May 2012Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy12OLD12Thank you for your attention23 May 201213OK13