Laboratoire de lIntégration du Matériau au Système CNRS UMR 5218 1 ICECS 2010 A 65nm CMOS Fully Integrated 31.5dBm Triple SFDS Power Amplifier dedicated.

Laboratoire de l’Intégration du Matériau au Système CNRS UMR 5218

1ICECS 2010

A 65nm CMOS Fully Integrated 31.5dBm Triple SFDS Power Amplifier

dedicated to W‑CDMA Application

Y. Luque1, N. Deltimple1, E. Kerherve1, D. Belot2

1IMS Laboratory, University of Bordeaux, IPB/ENSEIRB-MATMECA, IMS laboratory, 33405 Talence cedex, Fance

2STMicroelectronics, Minatec, Grenoble, France

[email protected]


2ICECS 2010

Outline• Introduction

– Context– State of the art– Targeted standard

• Triple Stacked Folded pseudo-Differential Structure (SFDS) PA– Triple SFDS circuit– Triple SFDS behavior

• 65 nm CMOS Triple SFDS PA– Overall PA– CW simulation– HPSK simulation

• Conclusion and future works


3ICECS 2010







4ICECS 2010

Telecommunication market • Increase the interactive services in mobile phones while limiting the

fabrication cost and the phone size.

– Reduce die area of circuits in order to implement new services– Reduce the cost of each chip– To level the eventual disappearance of old CMOS technologies

WWAN

WMAN

WLAN

WPAN

GSM (2G)EDGE (2.5G)UMTS (3G)HSPA (3.5G)LTE (4G)

WiFiGPS

Bluetooth

Zigbee

WiMAX, UWBMBWA

Proposition :

Design a PA using 65 nm CMOS technology dedicated to UMTS standard


5ICECS 2010

UMTS (3G)

• UMTS (Universal Mobile Telecommunication System)– Pout(max) = 24 dBm (the most widespread)

– Freq = 1.92-1.98 GHz Tx (2Mbps)

– Modulation schemes (QPSK, HPSK)

High output power for long distance communication with 65 nm CMOS technology

Power challenge


6ICECS 2010

W-CDMA • W-CDMA (Wideband Code Division Multiple Access)

– HPSK Modulation (Hybrid Phase-Shift Keying) non constant modulation envelope

– Requirement on Pout From -20dBm to 24dBm

– Requirements on linearity :

• ACPR1=-33dBc at +/- 5MHz

• ACPR2=-43dBc at +/- 10MHz• HD3<40dBc

Linearity challenge

optimize the linearity-efficiency trade-off

use a structure allowing to high gain to avoid a third stage (linearity-gain trade-off)


7ICECS 2010

65 nm CMOS technology

65 nm130 nm

130 nm MW250 nm

Low backend

More resistive

Reduction of back-end leads to: - decrease the quality factor of passive devices

- increase electro-migration matters

- increase capacitive parasitic and resistive issues

- RF signal losses through the bulk

BiCMOS backend CMOS backend


8ICECS 2010

Ref CMOS (nm)Pout

(dBm)Gain(dB)

PAE (%) structure

*[FRI08]65

(BVDS=3.3V)Max: NC

OCP1: 19,618

Max: NC@ OCP1: 5,8

Diff Cascode

*[WAN08]65

(BVDS=6.2V)Max: 27

OCP1: 25,335

Max: 14@ OCP1: 10

Diff Cascode (self-biased)

[AFS10] 65Max:31,5

OCP1: 27,532

Max: 25@ OCP1:

Diff Cascode PA + DAT (Two stages)

with PPA

65 nm CMOS PA state of the art

high BVDS transistors

Distributed Active Transformer (DAT) High die area

Process option (cost)

Proposition :

Design of elementary topology with low BVDS transistors and without DAT


9ICECS 2010







10ICECS 2010

Triple SFDS overview

L

C1

VDD

Bias1

RFin+

RFout+

Bias2

M1

M2

C2

Bias3

M3

C3

L

C1

VDD

Bias1

RFin-

RFout-

Bias2 C2

Bias3

M3'C3

M2'

M1'

D3

D2 S3

D1 S2

S1

D3

D2

D1 S2

S1

G1

G2

G3

G1

G2

G3

Triple SFDS schematic

-2.0T

ensi

on (

V)

-1.0

0.0

1.0

2.0

3.0

9.0n 9.5n 10n

Temps (s)

InputOutput

VDSM1

VDSM2

VDSM3

gm1.vgs1

r ds1

vds1

gm2.vgs2

r ds2

vds2

G1, G2, G3

D2

S1

vgs1

vgs2 D1 S2

gm3.vgs3

r ds3 vds3

D3

S3vgs3

gm1.vgs1rds1

vds1

gm2.vgs2rds2

vds2

G1, G2, G3

D2

vgs1

vgs2D1 S2

gm3.vgs3rds3vds3

D3

S3vgs3

RFin+

RFout+

RFin-

RFout-

3323

2

32

23

112331 ....2//.

..2..

...2 dsmmmdsdsL

dsmdsmm

mmmdsmmmtripleSFDS rgggrrR

rgrgg

gggrgggA

Small signal equivalent circuit


11ICECS 2010

SFDS increases simultaneously the OCP1, the PAE and the

Pmax

SFDS versus differential cascode

@ 1,95 GHz SFDS Diff cascode

Pmax 30.7 dBm 29.2 dBm

OCP1 28 dBm 24 dBm

PAEmax 33 % 31 %

PAEOCP1 21 % 10 %

Gain 14.8 dB 15.2dB

L

C

VDD

Bias1

RFin+

RFout+Bias2

M1

M2

L

C

VDD

Bias1

RFin-

RFout- Bias2

M1

M2

L

C1

VDD

Pola1RFin+

RFout+Pola2

M1

M2

C2

L

C1'

VDD

Pola1RFin-

RFoutPola2

M1'

M2'

C2'

SFDS

Diff cascode


12ICECS 2010







13ICECS 2010

Overall PA

L

C8

VDD

Bias3

RFout+

Bias4

M1

M2

C7

Bias5

M3

C6L

VDD

Bias1

M2

C4

Bias2

M3

C3

L1

C1 C2

L2

C5

RFin+

L

C8

VDD

Bias3

RFout-

Bias4

M1

M2

C7

Bias5

M3C6L

VDD

Bias1

M2

C4

Bias2

M3C3

L1

C1 C2

L2

C5

RFin-

100Ω

100Ω

Triple SFDS

Differential Cascode

- GainDifferential Cascode

Triple SFDS

- Linearity, power

Requirements:- OCP1 = 27 dBm to be linear until 24dBm (back-off = 3dB)- BVDS = 1.8V

Matching Match

ing

Match

ing

S11 @ 1.95GHz

C1

L1 L2

C250Ω

PA

f1=1.75 GHz

f2=2.2 GHz


14ICECS 2010

CW simulation results@ 1.95 GHz

S11 - 25 dB

S12 - 56 dB

S22 - 12 dB

S21 35 dB

@ 1.95 GHz

Pout(max) 31.5 dBm

OCP1 27.5 dBm

PAE(max) 19.5 %

PAE@OCP1 10 %

BW_3dB= 25%


15ICECS 2010

ACLR respected until 23 dBm with an EVM of 5%

HPSK simulation resultsHSPK simulation with ADS analogRF

ACLR1 results according to Pout

Constelation


16ICECS 2010

Ref CMOS (nm)Freq

(GHz)Vsupply

(V)Pout

(dBm)Gain(dB)

PAE (%) Standard structureFOM - ITRS

(W.GHz²)

[SEO06]RFIC06

180 2.4 3.3Max: 23

OCP1: 20.219

Max: 35@ OCP1:

30,2NC Triple cascode 32

[REY07]JSSC07

130 2.45 1.5Max: 23

OCP1: NC15

Max: 35@ OCP1: NC

Bluetooth PAs+DAT 13

[LIU08]JSSC08

130 2.4 1.2Max: 27

OCP1: 24NC

Max: 32@ OCP1: 25

NC Diff PAs + DAT 37

[HAL07]RFIC07

90 5.8 1Max: 24,3

OCP1: 20.58

Max: 27@ OCP1: 15

NC Diff PAs +DAT 16

[CHO09]ISSCC09

90 2.3 3.3Max: 30

OCP1: 27.728

Max: 33@ OCP1: 23

WiMAXDiff Cascode PA

+ DAT (Two stage)

1101

*[FRI08]EuMC08

65(BVDS=3.3V)

2.4 3.3Max: NC

OCP1: 19.618

Max: NC@ OCP1: 5.8

802.11n Diff Cascode NC

*[WAN08]ESSCIRC0

8

65 (BVDS=6.2V)

2.4 3.3Max: 27

OCP1: 25.335

Max: 14@ OCP1: 10

NCDiff Cascode (self-biased)

1280

[AFS10]ISSCC10

65 2.45 3.3Max:31.5

OCP1: 27.532

Max: 25@ OCP1: 19

WLANDiff Cascode PA

+ DAT (Two stage) with PPA

3359

This work 65 1.95 4Max:31,5

OCP1: 27,535

Max: 19.5@ OCP1: 10

UMTS Triple SFDS 3312

Comparative table

Without DATWith DAT* High BVDS transistors [FRI08]-3.3V [WAN08]-6.2V


17ICECS 2010







18ICECS 2010

Conclusion• Challenge to design a CMOS PA dedicated to UMTS application.

• Demonstration of a simulated PA constrained by stringent restrictions on low BVDS active device.

• Validation of a new topology using low BVDS transistors & without DAT.

• Achievement of a Pmax= 31.5dBm OCP1=27.5dBm at 1.9GHz with simulated 65nm CMOS technology provided by STMicrolectronics DK.

• ACLR is respected until 23 dBm (EVM=10%)

• Efficiency enhancement technique (dynamic biasing)

• Layout achievement and measurements

Future works


19ICECS 2010

Thanks for your attention

Laboratoire de lIntégration du Matériau au Système CNRS UMR 5218 1 ICECS 2010 A 65nm CMOS Fully Integrated 31.5dBm Triple SFDS Power Amplifier dedicated.

Documents

matriau au systme cnrs

umts standard page

art targeted standard

g edge

g hspa

future works page

dbm requirements

w cdma application