L34_ProcessVariation

Process variation

Process variations

• Arise due to perturbations in the fabrication process

• Resulting in variations in the nominal values of parameters– Gate length– Gate oxide thickness– Dopant concentration– Interlevel dielectric thickness– Interconnect height and width.

Variation – wafer level

Variations – reticle and local

Variations –Environmental – power supply voltage

Variations –Environmental – temperature

Power 4 server chip: 2 cpu on a chipCPUs can be much hotter than cache

Causes larger frequency distribution

Frequency and Source-drain leakage

Interdie variations

• Die-to-die variations• wafer-to-wafer variations• lot-to-lot variations• Affect all the devices on the same die in the

same way• For example, they may result in the gate lengths

of all the transistors on any die to be larger than or smaller than the nominal value

• Same variation is assumed for the devices in the same circuit– So the interdie device variation has little influence on

the circuit behavior of some analog circuits such as a current mirror with a constant current bias as long as all transistors can still be biased in the saturation region.

Intradie variations/Mismatch

• Variability within a single die• Affect the different transistors differently on the

same die• For example they may result in some transistors

having smaller oxide thickness, while others may have larger oxide thickness than the nominal

• Also known as local process variation and mismatch (LPVM)

Classification of Intradie variations

Random variations: • Exhibit random behaviour which can be characterized in

terms of a distribution that may be either explicit, in the form of experimentally measured data, or implicit, in the form of a known probability density function that has been fitted to the measurements

Systematic variations: • They show predictable variations across a die, and are

caused by known physical phenomena during manufacturing in processes such as oxidation, deposition

Impact of variations on chip (analog ICs)

• Mismatch - biggest concern in analog circuits• Operational-amplifier - parameters like input/output

current/voltage offsets, gain, bandwidth, etc., • Variation in the values of unit current sources used

in the Digital to Analog Converter can impact the precision

• Variation in the matched transistors of the comparator used in flash Analog to Digital Converter will impose a tradeoff between yield and precision

Impact of variations on chip (Digital ICs)

• More significant in sub-100nm technology• Voltage, at which the aggressively scaled devices operate, is

also scaled down, causing reduction in the signal swing– Impacts the noise margin of the circuit– Fluctuation in the device parameters like threshold voltage, and drive

currents translates to fluctuation in noise margins

• Clock skew comparable to clock period, for the chips operating at GHz range

• Variations in data setup and hold times in flip-flops and registers

• Mismatch effects are imposing a stringent tradeoff between the speed and yield of high performance digital ICs

What about @ short channel lengths?

• Problem is amplified in scaled CMOS technologies

• Signal swing decreases with scaling but the standard deviation in mismatch increases with scaling

Process variations1

Draw a line in betweenthem?

Process variations2

Draw a line in betweenthem?

Nano-scale MOSFETs

• When the conventional MOSFET is being taken into nano dimensional world many new techniques are being added in order to realize the MOSFET with significant performance improvement

• Currently various stress enhancements are considered by semiconductor industries

• Dual stress Laser annealing is the feasible option to get ultra low junction depths

• As new techniques are getting added the sources of variations are also increasing

LPVM affects…

• ICs• And ICs have transistors, resistors and

capacitors– Influence of LPVM on resistor– Influence of LPVM on capacitors– Influence of LPVM on MOSFETs

Influence of LPVM on resistors

CMOS resistors

• Resistors– Well resistors– Metal resistors– Diffused resistors– Poly resistors

Resistor value

• Formula for resistance (R)= L/A = L/(W.t) = Rsh.(L/W)

Where Rsh = (/t)

• R depends on dimensions → variations in dimensions changes R

• Differential amplifiers – we need two similar resistors (R1 and R2)

• LPVM makes R1 and R2 different– Common mode gain etc changes

Variation in sheet resistance

• Film thickness• Doping concentration• Doping profile• Annealing conditions

• Modern process maintain Rsh variation within

20 % or 25 %

Classifications of sources of variations

Dimensionchanges

Doping concentration, doping profile,

annealing changes

Variation in dimensions

• Photolithographic inaccuracies - – Line width control: A measure of dimensional variation

introduced by photolithographic process– Scenario improves for feature sizes more than 5 m

• Non-uniform etching rate

Resistor value including Process variation

• Assumption: L >> W → ignore variation in L• Line width control – measure of dimensional

variation due to photolithograpgy• Less impact on more feature sizes i.e. larger widths

• R = R + (CL/W) + Rsh

where R – tolerance of the resistor

CL – line width control of the applicable layer

W –width

Rsh- variability in sheet resistance

Example

• R = R + (CL/W) + Rsh

• Given width – 2 m, CL - 0.25 m, variation in Rsh - 25%

• Variation in R is 37.5%• If width is 10 m then variation R is 27.5%

Consider a 99% quality level

• 5000 incorrect surgical operations per week!• 200,000 wrong drug prescriptions per year!• 2 crash landings at most major airports each

day!• 20,000 lost articles of mail per hour!

Mean and standard deviation• Mean - a measure of the systematic mismatch

between the matched devices, caused by mechanisms that influence all of the samples in the same way

where δi is the parameter value of the i-th sample unit

• Standard deviation - describes random mismatch caused by statistical fluctuations in process parameters or material properties

• Lesser the better

Mean and variation

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• Variation means that a process does not produce the same result every time

• Some variation will exist in all processes

μ

σ

• Sigma is a measure of variation (the data spread)

Measuring Process PerformanceThe idli-vadai shop delivery example. . .

• Customers want their idli-vadai delivered fast!

• Guarantee = “30 minutes or less”

• What if we measured performance and found an average delivery time of 23.5 minutes?– On-time performance is

great, right?– Our customers must be

happy with us, right?

How often are we delivering on time?Answer: Look at the variation!

• Managing by the average doesn’t tell the whole story. The average and the variation together show what’s happening.

s

x

30 min. or less

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Reduce Variation to Improve Performance

• Sigma level measures how often we meet (or fail to meet) the requirement(s) of our customer(s).

s

x

30 min. or less

0 10 20 30 40 50

Managing Up the Sigma Scale

Sigma % Good % Bad

1 30.9% 69.1%

2 69.1% 30.9%

3 93.3% 6.7%

4 99.38% 0.62%

5 99.977% 0.023%

6 99.9997% 0.00034%

Measured 3-sigma mismatch of Poly resistors

Observations

• Lower widths → larger variations• Higher resistance → larger variations• Use larger width → Use smaller resistances?!

– Common practice is that a resistor with long length (for high resistance) is broken into shorter resistors in series

Influence of LPVM on capacitors

Capacitors in CMOS

• Current CMOS technology provides various capacitance options– poly-to-poly capacitors, metal-to-metal capacitors,

MOS capacitors, and junction capacitors

• Popular ones are– metal-to-metal capacitors– junction capacitors– MOS capacitors

Process variation and capacitance

• MIM capacitor variation– Both the capacitance value and matching property

are sensitive to the 1. Variation in the thickness of dielectric2. Geometry of metal plates

– Variation < 20 %• MOS capacitor

– the capacitance values are strongly dependent on 1. Changes in oxide thickness2. Doping profile in the channel3. Variation in geometries

– Variation > 20 %

Measured 3-sigma mismatch of a MIM capacitor

Influence of LPVM on MOS transistors

Process variations in MOSFET

• MOSFETs are the most complex components in a CMOS technology fabrication

• Variations in many process parameters can result in the variations in device characteristics

• More important ones are variation in – Oxide thickness– Doping concentration,– Profiles in both the channel region and the

source/drain region– Variation in annealing condition– Device channel length/width

• Larger dimensions

• Fewer process steps

• impact of process variations - less

•Nanometer dimensions

•More number of complicated processing steps

•Process variations - no more negligible

Variation versus year

Measured data for 3-sigma mismatching of ID in PMOSFETs

Process Impact to Electrical Properties

Process variables and distributions Resulting electrical

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Optimum process

Process parameters

Device performance

• Determine the most stable process condition• The aim is to quantify the amount of variations at the device taking into

account the individual process variations• The process condition leading to the least amount of variation at the

device is the most stable process

VariabilityYield

Each candidate is examined with respect to variability/yield