Analysis of Diode Models ESc201 : Introduc:on to Electronics L12 rhegde Dept. of Electrical Engineering IIT Kanpur 1
Nov 01, 2014
Analysis of Diode Models
ESc201 : Introduc:on to Electronics L12
rhegde Dept. of Electrical Engineering
IIT Kanpur
1
Diode Anode
Cathode
2
PN Junction Diode
P N
Inside a PN junction at equilibrium (zero applied voltage), there is built-in voltage with N region being positive and P-region negative.
The built-in voltage (also called potential barrier) prevents electrons and holes to give rise to current.
-‐
-‐
-‐
-‐
-‐ -‐
+
+
+
+
+ +
P N
3
Simplified Picture
4
Extrinsic Semiconductors
Adding small amounts of suitable impurity atom can drastically alter number of electrons and holes in a semiconductor !
Addition of a group V element impurity to Silicon should increase electrons while addition of group III element impurity should increase number of holes
5
Doping
6
B
7
N-type : n > p
A Semiconductor such as Silicon doped with a donor impurity such as Phosphorous or Arsenic from group V of periodic table. The donor impurity donates an electron to conduction band thereby increasing their concentration
P-type : p > n
A Semiconductor such as Silicon doped with a Acceptor impurity such as Boron from group III of periodic table. The acceptor impurity increases number of holes in valence band.
N and P-type Semiconductors
8
No. of silicon atoms per unit volume 22 34 10 cm−×;
17 310AN cm−=Impurity concentration :
1 in 400,000 Silicon atoms is replaced by Boron
Very small amounts of impurity atoms can cause a drastic change in electrical property of a semiconductor.
9
PN Junction Diode
P N
Inside a PN junction at equilibrium (zero applied voltage), there is built-in voltage with N region being positive and P-region negative.
The built-in voltage (also called potential barrier) prevents electrons and holes to give rise to current.
-‐
-‐
-‐
-‐
-‐ -‐
+
+
+
+
+ +
P N
10
V
Forward and Reverse Bias P N
vd
Forward Bias: P is biased at a higher voltage compared to N. It lowers the built-in potential and allows current to flow.
V
P N
vdReverse Bias: N is biased at a higher voltage compared to P. This increases built-in potential and very little current flows. 11
Forward Bias Reverse Bias
The p-n junction only conducts significant current in the forward-bias region.
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
Cur
rent
(A)
Voltage (V)
Diode : 1N4001
VV
12
Breakdown
13
Diode : I-V Characteristics
{exp( ) 1}dD S
T
vi InV
= × −
Vd
n is called ideality factor and is equal to 1 for ideal diodes / 26 at T 300KTV kT q mV= ≅ =
Is : Reverse Saturation Current id:diode current; vd: applied voltage
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Forward Bias
{exp( ) 1}dD S
T
vi IV
= × −
26d Tv V mV>> =
exp( )dD ST
vi IV
≅ ×
P N
vd
15
Reverse Bias
{exp( ) 1}dD S
T
vi IV
= × −
d Rv v= −
{exp( ) 1}RD S S
T
vi I IV
= × − − ≅−
P N
vd
R Tv V>>16
17
18
Analysis using non-linear diode model is not easy
VS
R
D
VO = ? (1)S OV I R V= × +
{exp( ) 1} (2)OS
T
VI InV
= × −
S
I ln( 1) (4)IS TV IR nV⇒ = + × +
S
I ln( 1) (3)IO TV nV⇒ = × +
I
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Iterative Method:
Assume 0.6V =OV
S OV VIR−
=Calculate
1)IIln( S +×= TO nVVRe-calculate
ε≤Δ
IIConvergence:
(1) OS VIRV +=S
I ln( 1) (3)IO TV nV= × +
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Assume OV
S OV VIR−
=
1)IIln( S +×= TO nVV
D
VO = ?1K
2V
VO = 0.5
I = 1.5 x 10-3
VO = 0.711
VO = 0.707
I = 1.293 x 10-3
VO = 0.707
VO = 0.711
I = 1.289 x 10-3
VO = 0.707
CONVERGENCE
15
{exp( ) 1}
2 10/ 26
D ST
S
T
Vi IV
I AV kT q mV
−
= × −
= ×
= ≅at T 300K=
21
15
{exp( ) 1}
2 10/ 26 at T 300K
D ST
S
T
Vi IV
I AV kT q mV
−
= × −
= ×
= ≅ =
Assume OV
S OV VIR−
=
1)IIln( S +×= TO nVV
D
VO = ?1K
2V
VO = 1.0
I = 1.0 x 10-3
VO = 0.7
VO = 0.707
I = 1.293 x 10-3
VO = 0.707
VO = 0.7
I = 1.3 x 10-3
VO = 0.707
CONVERGENCE to the same Result 22
Graphical Method: Method of Load Line
S O
S O
V I R VV VIR
= × +
−⇒ =
VS
R
D
VO
{exp( ) 1}OS
T
VI InV
= × −
I
VO VS
VS/R solution
23
How about something that is
simple & easy to work with
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Simple Models
DESIGN
SIMULATE
Accurate but complex Models
Design meets Specs.
Implement
Role of simple model in design cycle
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• Analysis using a non-linear diode model is relatively difficult and time consuming. • It also does not give a symbolic expression that can provide insight and help in the design of the circuit. Need SIMPLER and LINEAR Device Models
Vγ
open circuit
rf
V > Vγ
V < Vγ
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I
V Vγ
Slope = 1/rf
Vγ
open circuit
rf
V > Vγ
V < Vγ
Piece-Wise Linear Model
Vγ is called cut-in or turn-on voltage and depends on nature of diode and range of current considered
10f f
I r V V I rV V γ
γ
−−= ⇒ = + ×
−
For most of our analysis, we will take Vγ = 0.7V and rf ~10Ω
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Even Simpler Diode Models
open circuit
V > Vγ
V < Vγ
Vγ
Vγ
open circuit
rf
V > Vγ
V < Vγ
Constant voltage drop model
Vγ V
I
Vγ
I
V 28
open circuit
V > 0
V < 0
Even Simpler Diode Models
Ideal diode model
Vγ=0
I
V
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Diode Models
open circuit
V > Vγ
V < Vγ
Vγ
open circuit
V > 0
V < 0
Vγ
open circuit
rf
V > Vγ
V < Vγ
+ vd -
I
{exp( ) 1}dD S
T
vi IV
= × −
Simplicity
Accuracy
30
D
1K
10V
Analysis using ideal diode model
open circuit
V > 0
V < 0
1K
10V D
mAk
I 10110
==31
Analysis with a constant voltage diode model
D
1K
10V open circuit
0.7V
V > 0.7
V < 0.7
1K
10V 0.7V
mAk
I 3.917.010=
−=
32
Vγ
open circuit
rf
V > Vγ
V < Vγ
Analysis with a constant voltage plus resistor diode model
D
1K
10V
mAI 208.91010007.010=
+
−=
33
D 5K
10V
5K2mA
Example
Find the current through the diode using ideal diode model
Is the diode forward biased? – Not Sure!! Assume that it is forward biased J Carry out analysis and then check if current through the diode is in appropriate direction. If not, diode is reverse biased and we carry out the analysis again!! 34
Example
D 5K
10V
5K2mA
102 05 DmA iK
−− + + =
10V
5K2mAiD
4Di mA=
Current is positive, so our assumption is correct
Assume forward bias
35
Example Find the current through the 5K resistor using ideal diode model
Assume forward bias
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D 5K
10V
2mA 4K5K
D 5K
10V
2mA 4K5K
D 5K
10V
2mA 4K5K
102 05 DmA iK
−− + − =
10V
2mA 4K iD
4Di mA= −
This is not possible. Therefore, our assumption is incorrect
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5K
D 5K
10V
2mA 4K
5K
10V
2mA 4K
Assume reverse bias
1 1
1
2
102 05 5
010
V VmAk k
VV V
+− + + =
=
=
V1 V2
38
5K
5K