Introduction to Microprocessorsebooks.lpude.in/computer_application/ad/DCAP210_INTRODUCTION… · Interfacing I/O Devices: Basic interfacing Concepts, Interfacing output displays,

Introduction to MicroprocessorsDCAP210

INTRODUCTION TOMICROPROCESSORS

Copyright © 2013, Suneet GuptaAll rights reserved

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forLovely Professional University

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CONTENTS

Unit 1: Microprocessors and Microcomputers 1

Unit 2: Introduction to Assembly Language 18

Unit 3: Assembly Language Programming of 8085 40

Unit 4: Microprocessor Architecture 55

Unit 5: Microcomputer System 67

Unit 6: 8085 Microprocessor Architecture 79

Unit 7: Memory Interfacing 94

Unit 8: Interfacing I/O Devices 108

Unit 9: Introduction to 8085 Instructions 144

Unit 10: Programming Techniques with Additional Instructions 181

Unit 11: Counters and Time Delays 194

Unit 12: Stacks 204

Unit 13: Subroutines 215

Unit 14: Interrupts 229

SYLLABUS

Introduction to Microprocessors

Objectives: To develop the hardware skills required for the complete understanding of the architecture and programming ofthe microprocessor used in computing world.

Sr. No. Description

1. Microprocessors, Microcomputers and Assembly Language: Microprocessors, microprocessor Instruction Set and Computer Languages, Application

2. Introduction to 8085 Assembly Language Programming: 8085 programming model, Instruction Classification, How to write a simple program?

3. Microprocessor Architecture and Microcomputer Systems: Microprocessor architecture and its operation, Memory, I/O devices, Example of Microcomputer system

4. 8085 Microprocessor Architecture and Memory Interfacing: 8085 MPU, Memory Interfacing, How does an 8085- Based Single board Microcomputer work?

5. Interfacing I/O Devices: Basic interfacing Concepts, Interfacing output displays, Interfacing input devices, Memory Mapped I/O

6. Introduction to 8085 Instructions: Data transfer operations, Arithmetic operations, Logic operations, branch operations

7. Programming Techniques with Additional Instructions: Programming techniques: Looping, Counting and Indexing, Additional Data transfer instructions

8. Counters and Time Delays: Counter and time delays, Illustrative program: Hexadecimal counter

9. Stack and Subroutines: Stack, Subroutine, Restart, Conditional call and Return Instruction

10. Interrupts: 8085 interrupts

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Unit 1: Microprocessors and Microcomputers

NotesUnit 1: Microprocessors and Microcomputers

CONTENTS

Objectives

Introduction

1.1 Microprocessor

1.2 Microcomputer

1.2.1 Automobile Analogy

1.2.2 Intel MCS-4 4-B Chip Set

1.2.3 Intel 8008 Microprocessor

1.2.4 8080 More and No More

1.3 Historical Perspective

1.3.1 Moore’s Law

1.4 Microprocessor Instruction Set

1.4.1 Implied Addressing

1.4.2 Register Addressing

1.4.3 Immediate Addressing

1.4.4 Direct Addressing

1.4.5 Register Indirect Addressing

1.4.6 Combined Addressing Modes

1.4.7 Timing Effects of Addressing Modes

1.4.8 Decoding

1.5 Summary

1.6 Keywords

1.7 Review Questions

1.8 Further Readings

Objectives

After studying this unit, you will be able to:

� Discuss the concept of microprocessor

� Analyse the important areas of microprocessor

� Elaborate on the concept of about microcomputer

� Explain the microprocessor instruction set

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Notes Introduction

The microprocessor was developed in the late 1970s because of Large-Scale Integration (LSI),which made it possible to pack thousands of transistors, diodes, and resistors onto a silicon chipless than 0.2 inch (5 mm) square. During the early 1980s Very-Large-Scale Integration (VLSI)increased the circuit density of microprocessors by a large gap. A single VLSI circuit holdsmultiple electronic components on a chip identical in size to the LSI circuit.

The production of low cost microprocessors enabled computer engineers to developmicrocomputers. Such computer systems are smaller than portable television sets but haveenough computing power to perform many business, industrial and scientific tasks. Theintelligent terminals such as automatic teller machines and point-of-sale terminals employed inretail stores were developed due to the introduction of the microprocessor. The microprocessoralso provides automatic control of industrial robots, surveying instruments, and various kindsof hospital equipment. It has brought about the computerization of a wide array of consumerproducts, including programmable microwave ovens, self-tuning television sets, and electronicgames. In addition, some automobiles feature microprocessor-controlled ignition and fuelsystems designed to improve performance and fuel economy.

1.1 Microprocessor

The microprocessor or the Central Processing Unit (CPU) is the brain of all computers and manyhousehold and electronic devices. Multiple microprocessors, work together, and help in thedevelopment of datacentres, super-computers, communications products, and other digitaldevices.

Did u know? The first microprocessor was the Intel 4004, introduced in 1971. The 4004 wasnot very powerful; it was primarily used to perform simple mathematical operations in acalculator called “Busicom.”

Just like microwaves or telephones, devices with microprocessors have become so integratedinto our daily lives, that we cannot imagine a life without them.

It’s sometimes hard to believe that only 60 years ago, computers were rare and were not availablefor the wider public. It wasn’t until the ’80s that computers entered our homes and – thanks to themicroprocessor – really made an impact on the average person’s life.

Nowadays, modern microprocessors can perform extremely complex operations in areas suchas meteorology, aviation, nuclear physics and engineering, and take up much less space as wellas delivering superior performance. Over the past 40 years, microprocessors have become fasterand more powerful, yet increasingly smaller and more affordable. The manufacturing of a CPUis a highly complex and demanding process involving multiple hundreds of steps in“cleanrooms.” Cleanrooms or manufacturing plants, contain air which is 1,000 times cleanerthan a hospital’s operation theatre. The building of one plant costs approximately $5bn.

Self Assessment

State whether the following statements are true or false:

1. A single VLSI circuit holds hundreds of thousands of electronic components on a chip.

2. The microprocessor permitted the development of so-called intelligent terminals.

3. The microprocessor is different from a CPU.



Notes1.2 Microcomputer

A microcomputer is a small, low cost computer with a microprocessor as its Central ProcessingUnit. It includes a microprocessor, memory, and input/output (I/O) facilities. Microcomputersbecame popular in the 1970s and 80s with the advent of increasingly powerful microprocessors.The predecessors to these computers, mainframes and minicomputers, were comparativelymuch larger and more expensive. Many microcomputers (when equipped with a keyboard andscreen for input and output) are also personal computers.

Did u know? The abbreviation micro was common during the 1970s and 1980s.

1.2.1 Automobile Analogy

Microprocessors are also applicable in areas like automobiles. Microprocessors find applicationsin engine and driveline control, instrumentation, ride control, antilock braking and other safetydevices, entertainment, heating/air conditioning control, automatic seat position control, andmany other systems. In each of these applications, the microprocessor serves as the functionalcore of what can properly be called a special-purpose microcomputer.

Although these applications are widely varied in operation, the essential configuration (orarchitecture) has much in common for all applications. The figure below depicts a simplifiedblock diagram depicting the various components of each of the automotive systems having theapplications listed previously. In this block diagram, the microprocessor is denoted MPU. It isconnected to the other components by means of three buses: Address Bus (AB), Data Bus (DB),and Control Bus (CB). Each bus consists of a set of wires over which binary electrical signals aretransmitted. By way of illustration, in early automotive application, the DB consists of 8 wires,the AB is typically 8 to 16 wires, and the control bus is a set of 3 or 4 wires.

DATA IN

16 BIT AB

MPU ROM RAM I/OTIMING

8 BIT DB

CB

OUTPUT

Source: http://www.globalspec.com/reference/27440/203279/microcomputer-applications-in-automotive-systems

The operation of each special-purpose microcomputer system is controlled by a program storedin ROM. The MPU generates addresses for the ROM in sequence to obtain each instruction incorresponding sequence. The operation of each microprocessor based automotive subsystem.

Figure 1.1: Architecture for Typical Automotive Computer



Notes 1.2.2 Intel MCS-4 4-B Chip Set

Intel MCS4 system or the Microcomputer System 4-bit was the first single-chip microprocessorsystem in history. Despite the complicated memory architecture with separate program- anddata-memories, and despite the somewhat incomplete instruction set, the processor and systemarchitecture provide a very interesting engineering solution. Combined with innovativemarketing and a complete set of development tools, including an EPROM-based prototypesystem, the MCS4 became an instant commercial success. While the MCS4 was soon replaced bymuch better 8-bit systems, it still paved the way for the microprocessor revolution.

The MCS-4 is a micro programmable computer set designed for applications such as testsystems, peripherals, terminals, billing machines, measuring systems, numeric and processcontrol. The 4004 CPU, 4003 SR, and 4002 RAM are standard building blocks. The 4001 ROMcontains the custom micro program and is implemented using a metal mask according to customerspecifications. MCS-4 systems interface easily with switches, keyboards, displays, teletypewriters,printers, readers, A-O converters and other popular peripherals. A system built with the MCS-4 microcomputer set can have up to 4K x 0 bit R OM words, 1200 x 4 bit RAM characters and 120I/O lines without requiring any interface logic. By adding a few simple gates the MCS-4 canhave up to 40 RAM and ROM packages in any combination, and 102 I/O lines. The minimumsystem configuration consists of one CPU and one 250 x 0 bit ROM. The MCS-4 has a verypowerful instruction set that allows both binary and decimal arithmetic. It includes conditionalbranching, jump to subroutine, and provides for the efficient use of ROM look-up tables byindirect fetching.

The Intel MCS-4 microcomputer set (4001/2/3/4) is fabricated with Silicon Gate Technology.This low threshold technology allows the design and production of higher performance MOScircuits and provides a higher functional density on a monolithic chip than conventional MOStechnologies.

ROM Chip (4001)

The 4001 is a 2048 Bit metal mask programmable ROM providing custom microprogrammingcapability for the MCS-4 microcomputer set. Each chip is organized as 256 x 8 bit words whichcan be used for storing programs or data tables. Each chip also has a 4 bit input-output (I/0) portwhich is used to route information to and from the data bus lines in and out of the system.

Source: http://www.computermuseum.li/Testpage/Chip-IntelP4001.htm

Figure 1.2: ROM Chip



NotesRAM Chip (4002)

The 4002 performs two functions. It stores 320 bits arranged as 4 registers of twenty 4-bit characterseach and as a vehicle of communication with peripheral devices, it is provided with 4 outputlines and associated control logic to perform output operations.

Input/Output Ports

The i4003 chip is a simple 10-bit serial-input parallel-output shift-register. Manufactured in thesame PMOS process technology as the other MCS4 chips, it provided an easy means to addoutput-ports to a MCS4 system. Typical applications were the control of multiplexed keypadsand displays, and the control of general peripheral devices.

Microprocessor—CPU Chip (4004)

Intel 4004 was the first commercially available single-chip microprocessor in history. It was a 4-bit CPU designed for usage in calculators, or, as we say now, designed for “embeddedapplications”. Clocked at 740 KHz, the 4004 executed up to 92,000 single word instructions persecond, could access 4 KB of program memory and 640 bytes of RAM. The Intel 4004 was a partof MCS-4 chipset, which included the following chips:

� 4001 – 256-bit mask ROM and 4-bit I/O device,

� 4002 – 320-bit RAM and 4-bit I/O device,

� 4003 – 10-bit shift register,

� 4008 and 4009 – standard memory and I/O interface set.

Although the Intel 4004 was a perfect fit for calculators and similar applications it was not verysuitable for microcomputer use due to its somewhat limited architecture. The 4004 lacked interruptsupport, had only 3-level deep stack, and used complicated method of accessing the RAM. Someof these shortcomings were fixed in the 4004 successor – Intel 4040.

The Intel 4004 is very popular with CPU collectors and non-collectors. Earlier Intel C4004 CPUsin white ceramic package are sought-after by beginner and intermediate collectors, and areusually sold for hundreds of dollars.

Did u know? The only known second source manufacturer of 4004 microprocessors wasNational Semiconductor.

Distributed Logic Architecture

MCS 4 comprises of a 4 bit data bus, dynamic random access memory and address stack of theCentral Processing Unit. It also supports distributed decoding of instructions in which theROM/RAM chips watch the bus, and decode port instructions to appear as if they were sent fromthe ROM. This eliminated the need for separate signal lines to the I/O ports

MCS-4 Applications

The MCS-4 chips were used in toys, automobiles, and appliances as they were of a small size andinexpensive.



Notes

Did u know? Ted Hoff made gave the idea for the MCS-4 and did the feasibility study forthe first calculator.

1.2.3 Intel 8008 Microprocessor

The 8008 was available in two speed grades – 500 KHz and 800 KHz. As it took the CPU from5 to 8 cycles to execute each instruction, the effective rate of instruction execution was:

� From 45,000 to 100,000 instructions per second for Intel 8008

� From 72,000 to 160,000 instruction per second for Intel 8088-1

These numbers assume that the CPU uses fast memory and doesn’t require wait states to accessthe memory. Although the effective speed in instructions per second of the 8008 microprocessorsometimes is lower than the effective speed of the 4004 CPU, overall performance of the i8008was greater due to faster effective speed of some instructions, 8-bit architecture and more efficientinstruction set. The 8008 had other advantages over the 4004:

� The processor supported of 16 KB of memory (ROM and RAM combined).

� The size of internal CPU stack was 7 levels in contrast to 3 level-stack for the i4004.

� The Intel 8008 could handle interrupts.

One of the disadvantages of the Intel 8008 was the lack of direct memory addressing. To accessdata in memory the memory address had to be stored in H and L registers, and only then theprocessor could indirectly access the memory. This limitation was eliminated in Intel 8080.

Intel 8008 microprocessor was used in Mark-8 computer, which is considered to be the firstpersonal computer.

The architecture of Intel 8008 included:

Memory

Program and data memories occupy the same memory space. The total addressable memorysize is 16 KB.

� Program memory is a program that can be located anywhere in memory. Jump, branchand call instructions use 14-bit addresses (16-bit addresses with 2 the most significant bitsignored), i.e. they can be used to jump/branch anywhere within 16 KB. All jump/branchinstructions use absolute addressing.

� Data memory - the processor always uses 14-bit addresses so that data can be placedanywhere.

� Stack memory contains 7 14-bit registers. The size of stack memory is sufficient to nestsubroutines 7-levels deep.

First 64 bytes in a zero memory page should be reserved for vectors used by RST instructions.

Interrupts

The processor support non-maskable interrupts. When an interrupt occurs the processor fetchesfrom the bus one instruction, usually one of these instructions:

� One of the 8 RST instructions (RST0 - RST7).



NotesThe processor saves current program counter into stack and branches to memory locationN * 8 (where N is a 3-bit number from 0 to 7 supplied with the RST instruction).

� CALL instruction (3 byte instruction). The processor calls the subroutine, address of whichis specified in the second and third bytes of the instruction.

I/O ports

They are responsible for the input and output of the microprocessor.

Registers

� Accumulator or A register is an 8-bit register used for arithmetic, logic, I/O and load/store operations.

� Data registers – Six 8-bit registers:

� Four 8-bit registers B, C, D and E are used for temporary storage.

� 8-bit H and 8-bit L registers can be used as one 16-bit HL register pair. HL registerusually contains a data pointer used to reference memory addresses. In this case theL register contains low-order byte, and 2 most significant bits in the register H areignored.

� Flag register contains 4 flag bits: Sign, Zero, Parity and Carry.

� Program counter is a 14-bit register.

� Stack registers are 7 14-bit registers.

Instruction Set

8008 instruction set consists of 48 instructions:

� Data moving instructions.

� Arithmetic – add, subtract, increment and decrement.

� Logic – AND, OR, XOR, compare and rotate.

� Control transfer – conditional, unconditional, call subroutine, return from subroutine andrestarts.

� Input/Output instructions.

� Other – Halt instruction.

Instruction length can range from 1 to 3 bytes.

Addressing Modes

� Register – references the data in a register.

� Register indirect – instruction specifies HL register pair containing address, where thedata is located.

� Immediate.



Notes 1.2.4 8080 More and No More

The Intel 8080 was the second 8-bit microprocessor designed and manufactured by Intel and wasreleased in April 1974. It was an extended and improved variant of the previous 8008 design,although without binary compatibility. The initial specified clock frequency limit was 2 MHz,and with common instructions having execution times of 4, 5, 7, 10, or 11 cycles this meant thatit operated at an effective speed of a few hundred thousand instructions per second. The 8080has sometimes been labelled “the first truly usable microprocessor”, although earliermicroprocessors were used for calculators and other applications. The architecture of the 8080strongly influenced Intel’s 8086 CPU architecture, which spawned the x86 family of processors.

The 8080 was implemented using non-saturated enhancement-load NMOS, demanding an extra+12 volt and a “5 volt supply.

The Intel 8080 was the successor to the 8008. It used the same basic instruction set and registermodel as the 8008 even though it was not source code compatible nor binary compatible with itspredecessor. Every instruction in the 8008 has an equivalent instruction in the 8080 (even thoughthe actual opcodes differ between the two CPUs). The 8080 also added a few 16-bit operations toits instruction set as well. Whereas the 8008 required the use of the HL register pair to indirectlyaccess its 14-bit memory space, the 8080 added addressing modes to allow direct access to its full16-bit memory space. In addition, the internal 7-level push-down call stack of the 8008 wasreplaced by a dedicated 16-bit stack pointer (SP) register. The 8080’s large 40-pin DIP packagingpermitted it to provide a 16-bit address bus and an 8-bit data bus, allowing easy access to 64kilobytes of memory.

The 8080 was used in many early microcomputers, such as the MITS Altair 8800 Computer,Processor Technology SOL-20 Terminal Computer and IMSAI 8080 Microcomputer, forming thebasis for machines running the CP/M operating system (the latter, almost fully compatible andmore capable, Zilog Z80 processor would capitalize on this, with Z80 & CP/M becoming thedominant CPU & OS combination of the period circa 1976 to 1983 much as did the x86 & MS-DOSfor the PC a decade later). Even in 1979 after introduction of the Z80 and 8085 processors, fivemanufacturers of the 8080 were selling an estimated 500,000 units per month at a price around $3to $4 per unit. The first single-board microcomputers, such as MYCRO-1 and the dyna-micro werebased on the Intel 8080. One of the early uses of the 8080 was made in the late 1970s by Cubic-Western Data of San Diego, CA in its Automated Fare Collection Systems custom designed formass transit systems such as BART and others around the world. An early industrial use of the8080 was as the “brain” of the DatagraphiX Auto-COM (Computer Output Microfiche) line ofproducts which took large amounts of user data from reel-to-reel tape and imaged it ontomicrofiche. The Auto-COM instruments also included an entire automated film cutting, processing,washing, and drying sub-system – quite a feat, both then and in the 21st century, to all beaccomplished successfully with only an 8-bit microprocessor running at a clock speed of lessthan 1 MHz with a 64 KB memory limit. In addition, several early arcade video games were builtaround the 8080 microprocessor. Space Invaders was perhaps the most popular such title.

Shortly after the launch of the 8080, the Motorola 6800 competing design was introduced, andafter that, the MOS Technology 6502 variation of the 6800. Zilog introduced the Z80, which hada compatible machine-language instruction set and initially used the same assembly languageas the 8080, but for legal reasons, Zilog developed a syntactically-different (but code compatible)alternative assembly language for the Z80. At Intel, the 8080 was followed by the compatibleand electrically more elegant 8085, and later by the assembly language compatible 16-bit 8086and then the 8/16-bit 8088, which was selected by IBM for its new PC to be launched in 1981.Later NEC made an NEC V20 (an 8088 clone with Intel 80186 instruction set compatibility)which also supported an 8080 emulation mode. This was also supported by NEC’s V30 (a similarlyenhanced 8086 clone). Thus, the 8080, via its ISA, made a lasting impact on computer history.



NotesIn the Soviet Union, manufacturers cloned the 8080 microprocessor’s layout geometry andstarted to produce them under the name KP580ÈK80 (later marked as KP580BM80), where eventhe pins were placed identically. This processor was the base of the Radio86RK, probably themost popular amateur single-board computer in the Soviet Union. Radio86RK’s predecessorwas the Micro-80, and its successor the Orion-128 which had a graphical display. Both were builton the KP580 processor. According to some sources, the Soviet analog had two undocumentedinstructions, specific to itself; however, these were not widely known.

Another model compatible with Intel 8080A, named MMN8080, was produced at MicroelectronicaBucharest in Romania. There was also a compatible Polish CPU named MCY7880 and the Czech-made Tesla MHB 8080A.

Self Assessment

Fill in the blanks:

4. A …………………… is a small, relatively inexpensive computer with a microprocessor asits Central Processing Unit (CPU).

5. The operation of each special-purpose microcomputer system is controlled by a programstored in …………………….

6. The …………………… generates addresses for the ROM in sequence to obtain eachinstruction in corresponding sequence.

7. The 4001 ROM contains the custom …………………… program and is implemented usinga metal mask according to customer specifications.

8. The Intel 8080 was the second …………………… bit microprocessor designed andmanufactured by Intel and was released in April 1974.

1.3 Historical Perspective

Gordon Moore made his well-known observation in 1965, just four years after the first planarintegrated circuit was discovered. The press called it “Moore’s Law” and the name has stuck. Inhis original paper, Moore predicted that the number of transistors per integrated circuit woulddouble every 18 months. He predicted that this trend would continue through 1975. ThroughIntel’s technology, Moore’s Law has been maintained for far longer, and still holds true as weenter the new century. The mission of Intel’s technology development team is to continue tobreak down barriers to Moore’s Law.

1.3.1 Moore’s Law

Moore’s law is the observation that, over the history of computing hardware, the number oftransistors on integrated circuits doubles approximately every two years. The period oftenquoted as “18 months” is due to Intel executive David House, who predicted that period for adoubling in chip performance (being a combination of the effect of more transistors and theirbeing faster).

Intel co-founder Gordon E. Moore described the trend in his 1965 paper. The paper noted that thenumber of components in integrated circuits had doubled every year from the invention of theintegrated circuit in 1958 until 1965 and predicted that the trend would continue “for at least tenyears”. His prediction has proven to be uncannily accurate, in part because the law is now usedin the semiconductor industry to guide long-term planning and to set targets for research anddevelopment.



Notes The capabilities of many digital electronic devices are strongly linked to Moore’s law: processingspeed, memory capacity, sensors and even the number and size of pixels in digital cameras. Allof these are improving at (roughly) exponential rates as well (see other formulations and similarlaws). This exponential improvement has dramatically enhanced the impact of digital electronicsin nearly every segment of the world economy. Moore’s law describes a driving force oftechnological and social change in the late 20th and early 21st centuries.

Although this trend has continued for more than half a century, Moore’s law should be consideredan observation or conjecture and not a physical or natural law. Sources in 2005 expected it tocontinue until at least 2015 or 2020. However, the 2010 update to the International TechnologyRoadmap for Semiconductors has growth slowing at the end of 2013, after which time transistorcounts and densities are to double only every three years. Several measures of digital technologyare improving at exponential rates related to Moore’s law, including the size, cost, density andspeed of components. Moore himself wrote only about the density of components (or transistors)at minimum cost.

Transistors per Integrated Circuit: The most popular formulation is of the doubling of thenumber of transistors on integrated circuits every two years. At the end of the 1970s, Moore’slaw became known as the limit for the number of transistors on the most complex chips. Thegraph at the top shows this trend holds true today.

Density at Minimum Cost per Transistor: This is the formulation given in Moore’s 1965 paper.It is not just about the density of transistors that can be achieved, but about the density oftransistors at which the cost per transistor is the lowest. As more transistors are put on a chip, thecost to make each transistor decreases, but the chance that the chip will not work due to a defectincreases. In 1965, Moore examined the density of transistors at which cost is minimized, andobserved that, as transistors were made smaller through advances in photolithography, thisnumber would increase at “a rate of roughly a factor of two per year”. Current state-of-the-artphotolithography tools use Deep Ultraviolet (DUV) light from excimer lasers with wavelengthsof 248 and 193 nm—the dominant lithography technology today is thus also called “excimerlaser lithography” which has enabled minimum feature sizes in chip manufacturing to shrinkfrom 0.5 micrometer in 1990 to 45 nanometres and below in 2010. This trend is expectedto continue into this decade for even denser chips, with minimum features approaching10 nanometres. Excimer laser lithography has thus played a critical role in the continued advanceof Moore’s law for the last 20 years.

Source: http://en.wikipedia.org/wiki/Moore%27s_law

Figure 1.3: Pixels per Dollar-based on Australian Recommended RetailPrice of Kodak Digital Cameras



NotesHard Disk Storage Cost per Unit of Information: A similar law (sometimes called Kryder’sLaw) has held for hard disk storage cost per unit of information. The rate of progression in diskstorage over the past decades has actually sped up more than once, corresponding to the utilizationof error correcting codes, the magnetoresistive effect and the giant magnetoresistive effect. Thecurrent rate of increase in hard drive capacity is roughly similar to the rate of increase intransistor count. Recent trends show that this rate has been maintained into 2007.

Network Capacity: According to Gerry/Gerald Butters, the former head of Lucent’s OpticalNetworking Group at Bell Labs, there is another version, called Butters’ Law of Photonics, aformulation which deliberately parallels Moore’s law. Butter’s law says that the amount of datacoming out of an optical fibre is doubling every nine months. Thus, the cost of transmitting a bitover an optical network decreases by half every nine months. The availability of wavelength-division multiplexing (sometimes called “WDM”) increased the capacity that could be placed ona single fibre by as much as a factor of 100. Optical networking and dense Wavelength-DivisionMultiplexing (DWDM) is rapidly bringing down the cost of networking, and further progressseems assured. As a result, the wholesale price of data traffic collapsed in the dot-com bubble.Nielsen’s Law says that the bandwidth available to users increases by 50% annually.

Pixels per Dollar: Similarly, Barry Hendy of Kodak Australia has plotted the “pixels per dollar”as a basic measure of value for a digital camera, demonstrating the historical linearity (on a logscale) of this market and the opportunity to predict the future trend of digital camera price, LCDand LED screens and resolution.

The Great Moore’s Law Compensator (TGMLC): Generally referred to as bloat, and also knownas Wirth’s law, is the principle that successive generations of computer software acquire enoughbloat to offset the performance gains predicted by Moore’s law. In a 2008 article in InfoWorld,Randall C. Kennedy, formerly of Intel, introduces this term using successive versions of MicrosoftOffice between the year 2000 and 2007 as his premise. Despite the gains in computationalperformance during this time period according to Moore’s law, Office 2007 performed the sametask at half the speed on a prototypical year 2007 computer as compared to Office 2000 on a year2000 computer.

Library Expansion: It was calculated in 1945 by Fremont Rider to double in capacity every 16years, if sufficient space were made available. He advocated replacing bulky, decaying printedworks with miniaturized microform analog photographs, which could be duplicated on-demandfor library patrons or other institutions. He did not foresee the digital technology that wouldfollow decades later to replace analog microform with digital imaging, storage, and transmissionmediums. Automated, potentially lossless digital technologies allowed vast increases in therapidity of information growth in an era that is now sometimes called an “Information Age”.

The Carlson Curve: It is a term coined by The Economist to describe the biotechnologicalequivalent of Moore’s law, and is named after author Rob Carlson. Carlson accurately predictedthat the doubling time of DNA sequencing technologies (measured by cost and performance)would be at least as fast as Moore’s law Carlson Curves illustrate the rapid (in some caseshyperexponential) decreases in cost, and increases in performance, of a variety of technologies,including DNA sequencing, DNA synthesis and a range of physical and computational toolsused in protein expression and in determining protein structures.

Self Assessment

Fill in the blanks:

9. Moore predicted that the number of …………………… per integrated circuit would doubleevery 18 months.

10. Moore himself wrote only about the …………………… of components (or transistors) atminimum cost.



Notes 11. …………………… law says that the amount of data coming out of an optical fibre isdoubling every nine months.


The ways by which a microprocessor specifies the data for the instructions called “addressingmodes”. To execute any operation, we have to give the corresponding instructions to themicroprocessor. In each instruction, programmer has to specify three things:

� Operation to be performed.

� Address of source of data.

� Address of destination of result.

Let us discuss some of these modes in detail.


In this type of addressing mode, No operand (register or data) is specified in the instruction. Theoperand is inherent to the instruction.

Example: CMA (Complement Accumulator), SIM, RIM, etc.


In register indirect addressing mode, the instruction specifies the name of the register in whichthe address of the data is available. Here the data will be in memory and the address will be inthe register pair.

Example: MOV A, M – The memory data addressed by H L pair is moved to A register.LDAX B.


In immediate addressing mode, the data is specified in the instruction itself. The data will be apart of the program instruction.

Example: MVI B, 3EH - Move the data 3EH given in the instruction to B register; LXI SP,2700H.


In this mode, the address of the operand is given in the instruction itself.

Source: http://www.eazynotes.com/notes/microprocessor/Slides/addressing-modes-of-8085.pdf

Figure 1.4: Direct Addressing



Notes� LDA is the operation.

� 2500 H is the address of source.

� Accumulator is the destination.


In this mode, the address of operand is specified by a register pair.


� MOV is the operation.

� M is the memory location specified by H-L register pair.

� A is the destination.

1.4.6 Combined Addressing Modes

Instructions like CALL use multiple addressing modes. This phenomenon is known as CombinedAddressing Modes.

1.4.7 Timing Effects of Addressing Modes

The time needed and storage memory depends on the addressing mode.

Example: Register addressing is faster than the other modes as they access the processordirectly.

1.4.8 Decoding

In CPU design, the instruction decoder is the part of the CPU that converts the bits stored in theinstruction register – or, in CPUs that have microcode, the microinstruction – into the controlsignals that control the other parts of the CPU.

A simple CPU with 8 registers may use 3-to-8 logic decoders inside the instruction decoder toselect two source registers of the register file to feed into the ALU as well as the destinationregister to accept the output of the ALU. A typical CPU instruction decoder also includes severalother things.

�Case Study History and Evolution of Microprocessors

A microprocessor is the chip containing some control and logic circuits that iscapable of making arithmetic and logical decisions based on input data and producethe corresponding arithmetic or logical output. The word ‘processor’ is the

Figure 1.5: Register Indirect Addressing

Contd...



Notes derivative of the word ‘process’ that means to carry out systematic operations on data. Thecomputer we are using to write this page of the manuscript uses a microprocessor to do itswork. The microprocessor is the heart of any computer, whether it is a desktop machine,a server or a laptop.

The microprocessor we are using might be a Pentium, a K6, a PowerPC, a Sparc or any ofthe many other brands and types of microprocessors, but they all do approximately thesame thing in approximately the same way.

No logically enabled device can do anything without it. The microprocessor not onlyforms the very basis of computers, but also many other devices such as cell phones,satellites, and many other hand held devices. They are also present in modern day cars inthe form of microcontrollers.

A microprocessor is also known as a CPU or central processing unit, which is a completecomputational engine that is fabricated on a single chip. Here we will discuss the historyof the 80x86 CPU family and the major improvements occurring along the line. Thehistorical background will help us to better understand the design compromises theymade as well as to understand the legacy issues surrounding the CPU’s design. We arediscussing the major advances in computer architecture that Intel employed whileimproving the x86.

Historical Development of the Microprocessors

Intel developed and delivered the first commercially viable microprocessor way back inthe early 1970’s: the 4004 and 4040 devices. The 4004 was not very powerful and all it coulddo was add and subtract with 4-bit data only at a time. But it was amazing those days thateverything was on one chip. Prior to the 4004, engineers built computers either fromcollections of chips or from discrete components (Transistor wired one at a time). Themachines then, were not portable and were very bulky, and power hungry. The 4004changed the scene with all its circuitry on a single chip. The 4004 powered one of the firstportable electronic calculators named ‘Busicom’.

These 4-bit microprocessors, intended for use in calculators, required very little power.Nevertheless they demonstrated the future potential of the microprocessor – an entireCPU on a single piece of silicon. Intel rapidly followed their 4-bit offerings with their 8008and 8080 eight-bit CPUs. A small outfit in Santa Fe, New Mexico, incorporated the 8080CPU into a box they called the Altair 8800. Although this was not the world’s first “personalcomputer” (there were some limited distribution machines built around the 8008 prior tothis), the Altair was the device that sparked the imaginations of hobbyists of the worldand the personal computer revolution was born.

The trends in processor design had impact of historical development of microprocessorsfrom different manufacturers. Intel started facing competition from Motorola, MOSTechnology, and an upstart company formed by disgruntled Intel employees, Zilog. Tocompete, Intel produced the 8085 microprocessor. To the software engineer, the 8085 wasessentially the same as the 8080. However, the 8085 had lots of hardware improvementsthat made it easier to design into a circuit.

Unfortunately, from software perspective the other manufacturer’s offerings were better.Motorola’s 6800 series was easier to program, MOS Technologies’ 65xx family was alsoeasier to program but very inexpensive, and Zilog’s Z80 chip was upward compatiblewith the 8080 with lots of additional instructions and other features. By 1978 most personalcomputers were using the 6502 or Z80 chips, not the Intel offerings.

The first microprocessor to make a real splash in the market was the Intel 8088, introducedin 1979 and incorporated into the IBM PC (which appeared around 1982 for the first time).

Contd...



NotesIf we are familiar with the PC market and its history, we know that the PC market movedfrom the 8088 to the 80286 to the 80386 to the 80486 to the Pentium to the Pentium II to thePentium III to the Pentium 4. Intel makes all of these microprocessors and all of them areimprovements of design base of the 8088. The Pentium 4 can execute any piece of code thatran on the original 8088, but it does it about 5,000 times faster!

Sometime between 1976 and 1978 Intel decided that they needed to leap-frog the competitionand produced a 16-bit microprocessor that offered substantially more power than theircompetitor’s eight-bit offerings. This initiative led to the design of the 8086 microprocessor.The 8086 microprocessor was not the world’s first 16-bit microprocessor (there were someoddball 16-bit microprocessors prior to this point) but it was certainly the highestperformance single-chip 16-bit microprocessor when it was first introduced.

During the design timeframe of the 8086 memory was very expensive. Sixteen Kilobytes ofRAM was selling above $200 at the time. One problem with a 16-bit CPU is that programstend to consume more memory than their counterparts on an 8-bit CPU. Intel, evercogniscent of the fact that designers would reject their CPU if the total system cost was toohigh, made a special effort to design an instruction set that had a high memory density(that is, packed as many instructions into as little RAM as possible). Intel achieved theirdesign goal and programs written for the 8086 were comparable in size to code runningon 8-bit microprocessors. However, those design decisions still haunt us today.

Questions:

1. Study and analyse the case.

2. Write down the case facts.

3. What do you infer from it?

Source: http://www.newagepublishers.com/samplechapter/000030.pdf

Self Assessment


12. The microprocessor has different ways of specifying the data for the instruction. These arecalled data modes.

13. In an instruction the programmer doesn’t specify the address of source of data.

14. In Register Addressing, the address of operand is specified by a register pair.

15. Instructions like CALL use multiple addressing modes

1.5 Summary

� The microprocessor, also known as the Central Processing Unit (CPU), is the brain of allcomputers and many household and electronic devices.

� A microcomputer is a small, relatively inexpensive computer with a microprocessor as itsCentral Processing Unit (CPU).

� It includes a microprocessor, memory, and input/output (I/O) facilities.

� The operation of each special-purpose microcomputer system is controlled by a programstored in ROM.

� The MPU generates addresses for the ROM in sequence to obtain each instruction incorresponding sequence.



Notes � The first 8-bit microprocessor, Intel 8008 (i8008) was released 5 months after Intel 4004.

� Moore predicted that the number of transistors per integrated circuit would double every18 months.

� Butter’s law says that the amount of data coming out of an optical fibre is doubling everynine months.

� The microprocessor has different ways of specifying the data for the instruction. These arecalled “addressing mode”.

� In each instruction, programmer has to specify three things: Operation to be performed,Address of source of data and Address of destination of result.

1.6 Keywords

Addressing Modes: The way a microprocessor specifies the data for the instruction.

Butter’s Law: It says that the amount of data coming out of an optical fibre is doubling everynine months.

MCS-4: It is a micro programmable computer set designed for applications.

Microcomputer: It is a small, relatively inexpensive computer with a microprocessor as itsCentral Processing Unit (CPU).

Microprocessor: It is the brain of all computers and many household and electronic devices.

Moore’s Law: It predicted that the number of transistors per integrated circuit would doubleevery 18 months.

MPU: It generates addresses for the ROM in sequence to obtain each instruction in correspondingsequence.

4001 ROM: It contains the custom micro program and is implemented using a metal maskaccording to customer specifications.


1. What is a microprocessor?

2. Explain a microcomputer.

3. Discuss the use of a microprocessor in the automobile industry.

4. Write a short note on MCS-4 Chipset.

5. What are the basic functions of a RAM chip?

6. Discuss the architecture of MCS-4.

7. What is the Intel 8008?

8. Explain the problems of the 8008 microprocessor.

9. Define Moore’s law.

10. Discuss the various addressing types used in microprocessors.



NotesAnswers: Self Assessment

1. True 2. True

3. False 4. Microcomputer

5. ROM 6. MPU

7. Micro 8. 8

9. Transistor 10. Density

11. Butter 12. False

13. False 14. False

15. True


Books N.K. Srinath, 8085 Microprocessor: Programming and Interfacing.

Ramesh S. Gaonkar, Microprocessor Architecture, Programming, and Applications withthe 8085.

Sunil Mathur, Microprocessor 8085 and Its Interfacing.

Udaya Kumar K. and Umashankar B.S., The 8085 Microprocessor: Architecture,Programming and Interfacing. Pearson Education India.

Online links http://courses.engr.illinois.edu/ece511/papers/Mazor.1995.IEEEXplore.pdf

http://en.wikipedia.org/wiki/Microcomputer

http://www.eazynotes.com/notes/microprocessor/Slides/instruction-set-of-8085.pdf

http://www.mcamafia.de/pdf/ibm_hitrc02.pdf

http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/80-mcs4/zaehler/lauflicht.html

http://www.xnumber.com/xnumber/Microcomputer_invention.htm



Notes Unit 2: Introduction to Assembly Language

CONTENTS

Objectives

Introduction

2.1 Assembly Language

2.1.1 Running the Program

2.1.2 Opcodes and Operands

2.1.3 Labels

2.1.4 Comments

2.1.5 Pseudo-ops (Assembler Directives)

2.2 The Assembly Process

2.3 Assembly Language Statements

2.4 Computer Languages

2.5 Summary

2.6 Keywords



Objectives


� Understand Assembly Language

� Explain the Assembler Directives

� Describe Assessment Directives

� Discuss the Assembly Process and Its Types

� Elaborate upon the Assembly Language Statements

� Discuss the various Computer Languages

� Classify the Application Software

Introduction

Assembly language is a low-level programming language for a computer, or other programmabledevice specific to particular computer architecture. High-level programming languages aregenerally portable across multiple systems. Assembly language is converted into executablemachine code by a utility program called assembler like NASM, MASM, etc.

2.1 Assembly Language

Every personal computer has a microprocessor that manages the computer’s arithmetical, logicaland control activities. Each family of processors has its own set of instructions for handling


Unit 2: Introduction to Assembly Language

Notesvarious operations like getting input from keyboard, displaying information on screen andperforming various other jobs. These set of instructions are called ‘machine language instruction’.Processor understands only machine language instructions which are combination of 1s and 0s.However machine language is too vague and complex for using in software development. Sothe low level assembly language is designed for a specific family of processors that representsvarious instructions in symbolic code and a more understandable form.

An understanding of assembly language provides knowledge of:

� Interface of programs with OS, processor and BIOS;

� Representation of data in memory and other external devices;

� How processor accesses and executes instruction;

� How instructions accesses and process data;

� How a program access external devices.

Other advantages of using assembly language are:

� It requires less memory and execution time;

� It allows hardware-specific complex jobs in an easier way;

� It is suitable for time-critical jobs;

� It is most suitable for writing interrupt service routines and other memory residentprograms.

Source: http://www.webopedia.com/TERM/A/assembly_language.html

2.1.1 Running the Program

Let us explain the entire coding and execution of an assembly language program with an example.

Step 1: Copy the assembly language program below to your H drive.

; Program: TEST.ASM

; AL Program to display the letter X on the screen

.model small.stack 256

.code

start:

Figure 2.1: Level of Hierarchy



Notes mov dl, 'X'mov ah, 2hint 21h

; All programs use the following 3 lines to terminate

mov ax, 4c00hint 21h

end start

Step 2: Assembling and Running Assembly Language Programs

An assembly language program must be assembled and linked before it can be executed. Theassembler produces an object file with the extension .OBJ. This file is taken as an input by thelinker and an executable program (extension .EXE) is produced, assuming there were no errorsin the program. We use the assembler and the linker. When you choose the assembler and clickon it, NAL will install both assembler and linker in your home directory in a folder calledMASM. You only need to do this ONCE.

The full name for this folder is H:\MASM. Create a program called TEST.ASM by copying theprogram text above and using Notepad (or Edit) save the file is in your home directory on theH:\ drive in the MASM folder. The file name will be: H:\MASM\TEST.ASM.

When saving the file with Notepad, you MUST save it with the “File Type” set to “All Files”. Youshould now select the MS-DOS Prompt (Command PROMPT) from the Start button menu(sometimes under Programs option). You now get an MS-DOS window where you have to entercommands by typing the name of the command you wish to use. Common commands are

� TYPE filename to display the file filename on the screen;

� DEL filename to delete the file called filename

� COPY filename newname: to make a copy of filename called newname

To view your program, you may use the TYPE program:

H:\> type H:TEST.ASM

Step 3: Running your program

First: Assemble it using MASM

H:\> masm test

Object filename [H:TEST.OBJ]: Press Return

Source listing [NUL.LST]: Press Return

Cross-reference [NUL.CRF]: Press Return

48928 + 432619 Bytes symbol space free

0 Warning Errors

0 Severe Errors

Notes The file test.asm MUST be in the same folder as MASM for the above to work.

Having successfully assembled your program, as above, you now link it in a similar fashion:

H:\> link test



NotesMicrosoft (R) Overlay Linker Version 3.64

Copyright (C) Microsoft Corp 1983-1988. All rights reserved.

Run File [H:TEST.EXE]: Press Return

List File [NUL.MAP]: Press Return

Libraries [.LIB]: Press Return

Notes The file test.obj MUST be in the same folder as LINK for the above to work.

To run your program, simply enter its name:

H:\> test

X

In the event of errors, you must edit your program and correct the errors. Then you repeat theabove steps to assemble and link your program, before running it.

Similarly, if you modify your program, you must assemble and link it before running it again.

2.1.2 Opcodes and Operands

An instruction in assembly language has the following format:

Source: www.cs.nccu.edu/~jmoney/comp2620/COMP2620-18.pptý

Opcodes are reserved words that correspond to machine instructions. Some examples include:

� dec: It will decrease the value with 1

� inc: increase the value with 1

� sub: subtract the second operand from the first,

Example: sub [ebx+00000310],4 would mean “decrease the value on ebx+0310 with 4”.

� add: will add the second operand from the first,

Example: add [ebx+00000310],4 would mean “increase the value on ebx+0310 with 4”.

� mov: copy the second operand to the first,

Example: mov [ebx+00000310],4 would mean “change the value on ebx+0310 to 4”.

Figure 2.2: Instruction Format



Notes � lea: copy the result of the second operand to the first operand

Example: lea eax,[esi+30] would mean copy esi+30 to eax.

� cmp: compare, 2 registers, or a number and a register.

Example: cmp esi,2//compare esi to 2

� jmp: jump to and address

Example: jmp +0000000A//this instruction would mean to jump forward 10 bytes in thecode.

Operands are the part of an instruction on which an operator acts upon. They can be:

� Registers – specified by Rn, where n is the number of the register(0-7)

� Numbers – indicated by # (decimal) or x(hexadecimal)

� Label – symbolic name of the memory location

� Operands are separated by commas

� Number, type, and order correspond to the machine instruction

Example: Create a simple 68K program called ADDER. Your program should addtogether the numbers: 6, 4, 12, 16, 17 and 50. The program is to be assembled with the 68K cross-assembler and then run on the 68K simulator (either Easy68K or the Teesside assembler/simulator). Run the binary file you have created in the simulation mode.

A very simple program that does not use complex addressing modes and only uses very simpleinstructions is

ORG $1000 Location of the program

MOVE.B Nmb1,D0 Get first number

ADD.B Numb2,D0 Add in second number





STOP #$2700 Stop execution

ORG $2000 Location of the data

Nmb1 DC.B 6

Nmb2 DC.B 4

Nmb3 DC.B 12

Nmb4 DC.B 16

Nmb5 DC.B 17

Nmb6 DC.B 50

END $1000 End of program (and address of first instruction)



Notes2.1.3 Labels

It is the first field of a source statement. The label field can take one of the following three forms:

1. An asterisk (*) or semicolon (;) as the first character in the label field indicates that the restof the source statement is a comment. Comments are ignored by the Assembler, and areprinted on the source listing only for the programmer’s information.

Examples:

* This line is a comment; This line is also a comment

2. A white-space character (blank or tab) as the first character indicates that the label field isempty. The line has no label and is not a comment. These assembly lines have no labels:

Examples:

ldaa 0rmb 10

3. A symbol character as the first character indicates that the line has a label. Symbol charactersare the upper or lower case letters a- z, digits 0-9, and the special characters, period (.),dollar sign ($), and underscore (_). Symbols consist of one to 15 characters, the first ofwhich must be alphabetic or the special characters period (.) or underscore (_). All charactersare significant and upper and lower case letters are distinct.

A symbol may occur only once in the label field. If a symbol does occur more than once in a labelfield, then each reference to that symbol will be flagged with an error. The exception to this ruleis the set pseudo-op that allows you to define and redefine the same symbol. We typically use setto define the stack offsets for the local variables in a subroutine. With the exception of the equ =and set directives, a label is assigned the value of the program counter of the first byte of theinstruction or data being assembled. The value assigned to the label is absolute. Labels mayoptionally be ended with a colon (:). If the colon is used it is not part of the label but merely actsto set the label off from the rest of the source line. Thus the following code fragments areequivalent:

here: decabne here

here decabne here

A label may appear on a line by itself. The assembler interprets this as set the value of the labelequal to the current value of the program counter. A label may occur on a line with a pseudo-op.

The symbol table has room for at least 2000 symbols of length 8 characters or less. Additionalcharacters up to 15 are permissible at the expense of decreasing the maximum number of symbolspossible in the table.

2.1.4 Comments

Comments are messages added to help the users. They have no effect on the translation processand are not assembled by the LC-3b Assembler. They are identified in the program by semicolons.A semicolon signifies that the rest of the line is a comment and is to be ignored by the assembler.If the semicolon is the first non-blank character on the line, the entire line is ignored. If the



Notes semicolon follows the operands of an instruction, then only the comment is ignored by theassembler. The purpose of comments is to make the program more comprehensible to thehuman reader. They help explain a non-intuitive aspect of an instruction or a set of instructions.In line 0A, the comment “Clear R3; it will contain the product” lets the reader know that theinstruction on line 0A is initializing R3 prior to accumulating the product of the two numbers.While the purpose of line 0A may be obvious to the programmer today, it may not be the casetwo years from now, after the programmer has written an additional 30,000 lines of code andcannot remember why he/she wrote AND R3,R3,#0. It may also be the case that two years fromnow, the programmer no longer works for the company and the company needs to modify theprogram in response to a product update. If the task is assigned to someone who has never seenthe code before, comments go a long way to helping comprehension. It is important to makecomments that provide additional insight and not just restate the obvious. There are two reasonsfor this. First, comments that restate the obvious are a waste of everyone’s time. Second, theytend to obscure the comments that say something important because they add clutter to theprogram. For example, in line 0F, the comment “Decrement R1” would be a bad idea. It wouldprovide no additional insight to the instruction, and it would add clutter to the page.

Another purpose of comments, and also the judicious use of extra blank spaces to a line, is tomake the visual presentation of a program easier to understand. So, for example, comments areused to separate pieces of the program from each other to make the program more readable.That is, lines of code that work together to compute a single result are placed on successive lines,while pieces of a program that produce separate results are separated from each other. Forexample, note that lines 0E through 10 are separated from the rest of the code by lines 0D and 11.There is nothing on lines 0D and 11 other than the semicolons. Extra spaces that are ignored bythe assembler provide an opportunity to align elements of a program for easier readability.

For example, all the opcodes start in the same column on the page.

2.1.5 Pseudo-ops (Assembler Directives)

A pseudo-operation or a pseudo-op, is an instruction to the assembler that does not generate anymachine code. The assembler resolves pseudo-ops during assembly, unlike machine instructions,which are resolved only at runtime. Pseudo-ops are sometimes called assembler instructions,assembler operators, or assembler directives.

In general, pseudo-ops give the assembler information about data alignment, block and segmentdefinition, and base register assignment. The assembler also supports pseudo-ops that give theassembler information about floating point constants and symbolic debugger information (dbx).

While they do not generate machine code, the following pseudo-ops can change the contents ofthe assembler’s location counter:

� .align

� .byte

� .comm

� .csect

� .double

� .dsect

� .float

� .lcomm

� .long



Notes� .org

� .short

� .space

� .string

� .vbyte

Self Assessment

Fill in the blanks:

1. Assembly language is a …………………… level programming language for a computer.

2. Assembly language is converted into executable machine code by a utility program referredto as an …………………….

3. The assembler produces an …………………… file.

4. …………………… are reserved words that correspond to machine instructions.

5. …………………… are the part of an instruction on which an operator acts upon.

6. The …………………… field occurs as the first field of a source statement.

7. …………………… are messages intended only for human consumption. They have noeffect on the translation process.

8. A …………………… is an instruction to the assembler that does not generate any machinecode.

2.2 The Assembly Process

Let us explain the process via an example.

Example: We shall focus on a fragment of assembly language code for the single high –level line of code that adds three variables and places the result in a fourth variable.

W = X + Y + Z

Before giving the assembly language equivalent of this code fragment, we note that addition isbasically a dyadic instruction; it takes two arguments and produces a single result. Due to thelack of a primitive three – input addition instruction, the above code fragment will be processedsomewhat as if it were the following lines of high – level code.

W = X

W = W + Y

W = W + Z

Here is a fragment of assembly language code that includes a translation of the above high-level code. This discussion focuses on allocation of addresses to items in the assembly language;thus it will use a number of concepts without sufficient explanation.

BALR 12,0 LOAD REGISTER 12 WITH CURRENT ADDRESS

USING *,12 AND USE IT AS A BASE FOR ADDRESSING.

L 5,X VALUE OF X INTO REGISTER 3



Notes A 5,Y ADD VALUE OF Y TO REGISTER 5

A 5,Z ADD VALUE OF Z TO REGISTER

ST 5,W STORE SUM INTO W

W DC F‘0’ W HAS AN INITIAL VALUE OF 0

X DC F‘1’ X HAS AN INITIAL VALUE OF 1

Y DC F‘2’ Y HAS AN INITIAL VALUE OF 2

Z DC F‘3’ Z HAS AN INITIAL VALUE OF 3

At this point, we must notice a major flaw in the code. Every line of the code is correct, andformatted in the standard style. Every instruction will execute correctly. The difficulty will ariseafter the “ST 5,W” has been executed, placing a value of 6 into location W.

The program has no STOP or branch statement, so it will start executing the data.

The Two-Pass Assembler

We now examine the action of a two-pass assembler on the above code fragment. Roughlyspeaking, the functions of the passes are as follows.

Pass 1: This associates addresses with the various labels used. The code fragment above usesfour labels: W, X, Y, and Z.

Pass 2: Uses these addresses to generate the machine language code for each line of assemblylanguage.

The assembler assigns addresses by use of the location counter, here abbreviated LC, to track thesize of the address space already allocated.

The first two lines of the code above should be viewed almost as non-executable. These are usedto “establish addressability” in the standard parlance. In effect, they tell the assembler how toset an initial value for the location counter.



Recalling that addresses issued by the assembler may be adjusted when the program is loadedinto memory, we note that the effect of this pair of lines is to set the LC.

Pass 1 processes the third line.

L 5, X VALUE OF X INTO REGISTER 3

At this point, we have LC = 0, as it was just initialized. The instruction will be assigned to address0. The instruction is a type RX, requiring four bytes for its storage.

Pass 1 processes line 4

A 5,Y ADD VALUE OF Y TO REGISTER 5

Since the previous instruction requires 4 bytes, the location counter has been incremented, sothat LC = 4 and this instruction will be placed at address 4. This instruction is also a type RX, andalso required four bytes. The next instruction will be at address 8.



NotesPass 1 processes line 5

A 5,Z ADD VALUE OF Z TO REGISTER 5

Since the previous instruction requires 4 bytes, the location counter has been incremented, sothat LC = 8 and this instruction will be placed at address 8. This instruction is also a type RX, andalso required four bytes. The next instruction will be at address 12 (decimal).


ST 5,W STORE SUM INTO W

Since the previous instruction requires 4 bytes, the location counter has been incremented, sothat LC = 12 and this instruction will be placed at address 12. This instruction is also a type RX,and also required four bytes. The next instruction will be at address 16 (decimal).


W DC F‘0’ W HAS AN INITIAL VALUE OF 0

Since the previous instruction requires 4 bytes, the location counter has been incremented, sothat LC = 16. This line is not an instruction, but is a declarative, used to define a label and allocatestorage space for a value to be associated with that label.

This line declares space to store a 32-bit full word, so it allocates four bytes for storage. The nextline will be associated with address 20 (decimal). This line defines the symbol W as beingassociated with address 16 (decimal).


X DC F‘1’ X HAS AN INITIAL VALUE OF 1

Since the previous declarative requires 4 bytes, the location counter has been incremented, sothat LC = 20, and the label X will be associated with address 20 (decimal).

This line also declares space to store a 32-bit full word, so it allocates four bytes for storage. Thenext line will be associated with address 24 (decimal).


Y DC F‘2’ Y HAS AN INITIAL VALUE OF 2

Since the previous declarative requires 4 bytes, the location counter has been incremented, sothat LC = 24, and the label Y will be associated with address 24 (decimal).

This line also declares space to store a 32-bit full word, so it allocates four bytes for storage. Thenext line will be associated with address 28 (decimal).


Z DC F‘3’ Z HAS AN INITIAL VALUE OF 3

Since the previous declarative requires 4 bytes, the location counter has been incremented, sothat LC = 28, and the label Z will be associated with address 28 (decimal).

One of the key outputs of pass 1 is a table associating each label with it address. Up to now, wehave been using decimal addresses. At this point, we must translate to hexadecimal.



Notes

Label Address

Decimal Hexadecimal

W 16 0x10

X 20 0x14

Y 24 0x18

Z 28 0x1C

Source: www.edwardbosworth.com/...DOC/MyText3121_Ch06_V02.docý

One should note that our simple code sample is a typical in one regard. All labels in thisfragment are associated with values to be processed. A more typical program would have labelsassociated with executable statements. The processing will be the same; as each line is processed,the value of the LC will be associated with any label found on the line.

Pass 2 of the assembler will generate the binary machine code associated with each line andprepare it for loading into the computer memory. At this point, we note another artificiality ofthe simple program fragment; each line corresponds to exactly four bytes. As we shall see later,this is rarely the case for IBM S/370 Assembler Language.

Loading the Machine Code

Before considering the actions of a loader, it would help to give a representation of the results ofpass 1 of the assembler. The following listing gives the essence of what was done.

Address Assembly Statement

0000 L 5,X

0004 A 5,Y

0008 A 5,Z

000C ST 5,W

0010 W DC F‘0’

0014 X DC F‘1’

0018 Y DC F‘2’

001C Z DC F‘3’

Notes That the addresses listed here are generated by the assembler and relative to theaddress assigned to the first one listed here. When the code is loaded into memory andmade ready to execute, each of these statements will be moved to another address. One ofthe jobs of the linking loader is to adjust these addresses.

Suppose that the program were loaded into address 0x1400 of real memory. Here is what thememory map, as seen by the operating system, would appear to be.

Address Assembly Statement

1400 L 5,X

1404 A 5,Y

Table 2.1: Address



Notes1408 A 5,Z

140C ST 5,W

1410 W DC F‘0’

1414 X DC F‘1’

1418 Y DC F‘2’

141C Z DC F‘3’

There are two approaches to handling this issue of addressing, which arises from the fact that theassembler addresses are different from those physical memory addresses into which the programis loaded. The first one relates to altering the machine code generated by pass 2 of the assembler.Since the System/370 does not use this approach, we shall not discuss it.

The second approach depends on the fact that relocating a fragment of code does not change theaddresses of any line in the fragment relative to the addresses of any other fragment. Considereach of the two fragments of code listed above. Simple subtraction will show that the address ofeach statement relative to the first one listed remains constant.

This observation forms the basis of the addressing modes used by the IBM System/370. Considernow the pair of code lines that we have not discussed.



The effect of these two lines is to load the absolute memory address of the line of code followingthe second statement into general purpose register 12, and make all address references relativeto that stored value.

Pass 2 of the Assembler

The primary function of the second pass of the assembler is to emit binary machine language.Here we shall jump ahead a bit and show the code generated. The student should be aware thatall of this will be explained in great detail in a later unit; the point now is just to see theassociation of machine code with addresses.

All of the instructions used in this program fragment are what is called “Type RX”. Instructionsin this format require four bytes, represented as eight hexadecimal digits. The format of such aninstruction is shown below.

Byte 1 Byte 2 Byte 3 Byte 4

OP R X B D D D

Source: www.edwardbosworth.com/...DOC/MyText3121_Ch06_V02.doc

The first byte is the opcode for the instruction, represented as two hexadecimal digits. For ourinstructions they are:

L Load Register 0x58A Add to Register 0x5AST Store Register 0x50

The second byte contains two hexadecimal digits. The first is for the affected register, here weare using 5. The second is for an index register. As this example does not use indexed addressing,the value placed in this digit is 0.

Table 2.2: Instruction Format



Notes The next two bytes contain the base register used, represented by a single hexadecimal digit.Here we specify 0xC, because register 12 is used as a base. The “DDD” represents a displacementaddress given as three hexadecimal digits.

Here is the output of pass 2 of the assembler.

Address Contents Assembly Statement

0000 58 50 C0 10 L 5,X

0004 5A 50 C0 14 A 5,Y

0008 5A 50 C0 18 A 5,Z

000C 50 50 C0 1C ST 5,W

0010 00 00 00 00 W DC F‘0’

0014 00 00 00 01 X DC F‘1’

0018 00 00 00 02 Y DC F‘2’

001C 00 00 00 03 Z DC F‘3’

Self Assessment


9. The second byte is the opcode for the instruction, represented as two hexadecimal digits.

10. The primary function of the second pass of the assembler is to emit binary machinelanguage.

2.3 Assembly Language Statements

The layout of a machine instruction is part of the architecture of a processor chip. Withoutknowing the layout you can’t tell what the instruction means. Even if you know the layout, it ishard to remember what the patterns mean and hard to write machine instructions.

A statement in pure assembly language corresponds to one machine instruction. Assemblylanguage is much easier to write than machine language. Here is the previous machine instructionand the assembly language that it corresponds to:

Machine Instruction Assembly Language Statement

0000 0001 0010 1011 1000 0000 0010 0000 add $t0,$t1,$t2

The instruction means: add the integers in registers $t1 and $t2 and put the result in register $t0.To create the machine instruction from the assembly language statement a translation programcalled an assembler is used.

Humans find assembly language much easier to use than machine language for many reasons.

� It is hard for humans to keep track of those ones and zeros.

� By using symbols programmers gain flexibility in describing the computation.

� Assembly language is a compact notation.

Enhanced assembly language includes additional convenience features. It has instructions (calledpseudo instructions) that correspond to several machine instructions.



NotesSelf Assessment

Fill in the blanks:

11. A …………………… in pure assembly language corresponds to one machine instruction.

12. Enhanced assembly language has instructions called …………………… that correspond toseveral machine instructions.

2.4 Computer Languages

Natural languages, such as English, are vague, fuzzily structured and have large (and changing)vocabularies. Computers have no common sense, so computer languages must be very precise –they have relatively few, exactly defined, rules for composition of programs, and strictly controlledvocabularies in which unknown words must be defined before they can be used. It is a majorgoal of research in Artificial Intelligence to find out how to make computers understand naturallanguages, and the more we learn, the harder it seems to be.

Sometimes we have to use assembly language (Low-Level Language, LLL) because there justisn’t any other sensible way of telling the computer what it must do. However, mostprogramming is done in High-Level Languages (HLLs), so what benefits does this bring? Themost important answer is productivity – it is usually easier, or more cost-effective, to use a HLL.Some of the reasons for this are:

� easy to write: useful concepts & facilities, relevant to application

� easy to read: computer, your future self, others – for reuse, maintenance, enhancement etc.

� portability: other compiler/toolset suppliers, users, computers – standards

� error detection & reporting

Different kinds of languages emphasize different things about the problem, and so are better atdescribing different aspects of the solution, or even different kinds of problems and solutions.Computer Science is ever-changing, so there is continual evolution of the concepts we need touse and the notations for describing these concepts.

Example: Operational languages express how something is achieved, and make thereader work out what is being achieved. Declarative languages express what must be achieved,and make the system work out how to achieve it.

The earliest languages had few restrictions, so they were very powerful, but turned out to bevery dangerous to use. After a while, people developed languages that were much safer to use,but there were complaints about their lack of power. Nowadays, we are starting to see languagesthat are both safe and powerful, but the process has a long way to go yet.

Imperative Paradigm

The very earliest languages had to be based on something, and that was probably simpleinstructions given to humans without much vocabulary or common sense, i.e. children. Thebasic ideas are about describing state (e.g. the current state, or a desired next state, of a particularset of things), the actions that modify the state, and the sequence of the actions. In a computation,state is represented by the values of registers (PC etc.) and memory (variables etc.).

Example: Process of making tea:



Notes declare kettle, teapot, water, tea_leaves;kettle= water;boil (kettle);teapot= tea_leaves;teapot= teapot + kettle;

However, although this is intuitive for simple problems, it became clear that this did not scalewell – i.e. it becomes disproportionately hard to use as problem size increases. To determinewhether a program will work correctly, we must examine, e.g. all possible combinations ofactions on all of the state.

To reduce the number of possible combinations, we can control: which actions are permitted ondifferent parts of the state – type checking and whereabouts in the program particular actionscan be used or parts of the state accessed – scope

Increasing awareness of scope and type checking carried language design in two directions. Themain stream of language design included these ideas in most programming languages, andgave rise to new programming paradigms which maximized the control over state (objects), orminimized the use of state (functional, logic). However, as the problem became better understood,it became clear that in some situations it could be an advantage to avoid scopes and typesaltogether (scripting).

Object Oriented Paradigm

This is similar to Imperative but with maximum use of types & scopes – keep state in objects,each type of object (class) having its own set of actions (methods). Furthermore, the state in anobject can often only be accessed or modified via its associated methods.

Functional Paradigm

Functional languages emphasize the transformations of values (so the notation usually makes iteasy to describe & examine values):

let boiling_water = boil (put_in (kettle, [water]))in put_in (teapot, [tea_leaves, boiling_water])end

In particular, values don’t have state, so they can be substituted freely:put_in (teapot, [tea_leaves, boil (put_in (kettle, [water]))])

Logic Paradigm

Define a problem by describing its facts and properties, and then solve it by giving the systema goal to prove using those facts and properties.

make(Con,tea):-water_proof(Con),heat_resistant(Con),contains(Con,tea_leaves),contains(Con,boiling_water).

source(tea_caddy,tea_leaves).source(tap,water).source(Con,boiling_water):-canboil(Con),contains(Con,water).contains(Con,Item):-source(Con,Item).contains(Con,Item):-source(Con2,Item),move(Item,Con,Con2).canboil(kettle).water_proof(teapot).heat_resistant(teapot).move(Item,Con,Con2).



NotesIf we ask “can we make tea in a teapot’’ by typing make(teapot, tea). the system answers yes, orif we ask “what can we make tea in’’ by typing make (X, tea). we get X = teapot We can even getthe system to tell us how to make tea:

move(Item,Con,Con2):- write(‘ move ‘), write(Item),write(‘ from ‘), write(Con2), write(‘ to ‘), write(Con), nl.

canboil(kettle):- write(‘boil kettle’), nl.

and make(teapot, tea). will output:

move tea_leaves from tea_caddy to teapotmove water from tap to kettleboil kettlemove boiling_water from kettle to teapot

Parallel Paradigm

Another difficulty with Imperative programming was the concept of sequence - there are manycircumstances where the exact order of some actions does not matter, as long as they are all donebefore we progress to the next step. In parallel languages, if actions don’t interact, work on themin any order (non-determinism), or even simultaneously (multi-processing).

CHAN OF ANY to_pot, to_kettle, kettle_to_pot, to_cup:declare boiling_water:PAR

declare water:SEQ – kettle

to_kettle ? waterboil ()kettle_to_pot ! boiling_water

declare tea_leaves:SEQ – teapot

PARto_pot ? tea_leaveskettle_to_pot ? boiling_water

to_cup ! tea

Scripting Paradigm

So far, we have been thinking about languages suitable for solving very large problems, wherethe resulting programs are tens of thousands or more lines long, written and maintained bymore than one person. However, not all problems require industrial-strength solutions, anddifferent requirements have given rise to different kinds of languages. The situations wherethey are applicable are:

� building applications by “gluing together” existing components

� controlling applications that have a programmable interface

� writing programs where ease of development is more important than anything else (suchas run-time efficiency, or maintainability)

The resulting languages are greatly simplified from the programmers point of view, so that“scripting languages make programmers of us all”. A major design pressure is to minimise theamount that users have to write, and therefore that they can get wrong. In particular, theyminimise the use of declarations, and thus the use of types or scopes - they often only have onetype, the string (so numbers are held as a series of digit characters). This reduces the usefulness



Notes of compilation, and means that more work must be done at run-time, so these languages areoften interpreted (and thus run much more slowly). They are often used to write simple littleprograms that are unlikely to ever be run again.

The earliest such languages were precursors to what we now know as CLIs or shells. Many of thethousands of existing programming languages are scripting languages designed to controlspecific applications. Widely-used scripting languages include AWK, Bash, JavaScript, Perl,Python, Rexx, and Tcl. Some of the ideas behind scripting languages are also relevant to moremain-stream languages, such as Visual Basic.

There is a big danger lurking in all of this – the very simplicity of scripting languages makesthem easy to overuse, and there is a new generation of users busy reinventing the mistakes ofthe previous generations, writing programs that no-one understands or can maintain.

�Case Study For and Against Assembly Language

Broadly speaking, you can divide the history of computers into four periods: themainframe, the mini, the microprocessor, and the modern post-microprocessor.The mainframe era was characterized by computers that required large buildings

and teams of technicians and operators to keep them going. More often than not, bothacademics and students had little direct contact with the mainframe—you handed a deckof punched cards to an operator and waited for the output to appear hours later. Duringthe mainframe era, academics concentrated on languages and compilers, algorithmic, andoperating systems.

The minicomputer era put computers in the hands of students and academics, becauseuniversity departments could now buy their own minis. As minicomputers were not ascomplex as mainframes and because students could get direct hands-on experience, manydepartments of computer science and electronic engineering taught students how toprogram in the native language of the computer—assembly language. In those days, themid 1970’s, assembly language programming was used to teach both the control of I/Odevices, and the writing of programs (i.e., assembly language was taught rather like highlevel languages). The explosion of computer software had not taken place, and if youwanted software you had to write it yourself.

The late 1970’s saw the introduction of the microprocessor. For the first time, each studentwas able to access a real computer. Unfortunately, microprocessors appeared before theintroduction of low-cost memory (both primary and secondary). Students had to programmicroprocessors in assembly language because the only storage mechanism was often aROM with just enough capacity to hold a simple single-pass assembler.

The advent of the low-cost microprocessor system (usually on a single board) ensured thatvirtually every EE or CS student took a course on assembly language. Even today, mostcourses in computer science include a module on computer architecture and organization,and teaching students to write programs in assembly language forces them to understandthe computer’s architecture. However, some computer scientists who had been educatedduring the mainframe era were unhappy with the microprocessor, because they felt thatthe 8-bit microprocessor was a retrograde step—its architecture was far more primitivethan the mainframes they had studied in the 1960’s.

The 1990’s is the post-microprocessor era. Today’s personal computers—the PCs, Apples,and PowerPCs—have more power and storage capacity than many of yesterday’s

Contd...



Notesmainframes, and they have a range of powerful software tools that were undreamed of inthe 1970’s. Moreover, the computer science curriculum of the 1990’s has exploded. In 1970a student could be expected to be familiar with all field of computer science. Today, astudent can be expected only to browse through the highlights.

The availability of high-performance hardware and the drive to include more and morenew material in the CS curriculum, has put pressure on academics to justify what theyteach. In particular, many are questioning the need for courses on assembly language.

If you regard computer science as being primarily concerned with the use of the computer,you can argue that assembly language is an irrelevance. Does the surgeon study metallurgyin order to understand how a scalpel operates? Does the pilot study thermodynamics tounderstand how a jet engine operates? Does the newsreader study electronics to understandhow the camera operates? The answer to all these questions is “no”. So why should weinflict assembly language and computer architecture on the student?

First, education is not the same as training. The student of computer science is not simplybeing trained to use a number of computer packages. A university course leading to adegree should also cover the history and the theoretical basis for the subject. Without knowledgeof computer architecture, the computer scientist cannot understand how computers havedeveloped and what they are capable of.

Is Assembly Language Today the same as Assembly Language Yesterday?

Two factors have influenced the way in which we teach assembly language—one is theway in which microprocessors have changed, and the other is the use to which assemblylanguage teaching is put. Over the years microprocessors have become more and morecomplex, with the result that the architecture and assembly language of a modern state-of-the-art microprocessor is radically different to that of an 8-bit machine of the late 1970’s.When we first taught assembly language in the 1970’s and early 1980’s, we did it todemonstrate how computers operated and to give students hands-on experience of acomputer. Since all students either have their own computer or have access to a computerlab, this role of the single-board computer is now obsolete. Moreover, assembly languageprogramming once attempted to ape high-level language programming—students weretaught algorithms such as sorting and searching in assembly language, as if assemblylanguage were no more than the (desperately) poor person’s C.

The argument for teaching assembly language programming today can be divided intotwo components: the underpinning of computer architecture and the underpinning ofcomputer software.

Assembly language teaches how a computer works at the machine (i.e., register) level. Itis therefore necessary to teach assembly language to all those who might later be involvedin computer architecture—either by specifying computers for a particular application, orby designing new architectures. Moreover, the von Neumann machine’s sequential natureteaches students the limitation of conventional architectures and, indirectly, leads themon to unconventional architectures (parallel processors, Harvard architectures, dataflowcomputers, and even neural networks).

It is probably in the realm of software that you can most easily build a case for the teachingof assembly language. During a student’s career, he or she will encounter a lot of abstractconcepts in subjects ranging from programming languages, to operating systems, to real-time programming, to AI. The foundation of many of these concepts lies in assemblylanguage programming and computer architecture. You might even say that assemblylanguage provides bottom-up support for the top-down methodology we teach in high-level

Contd...



Notes languages. Consider some of the following examples (taken from the teaching of Motorola’s68000-series assembly language).

� Data Types: Students come across data types in high-level languages and the effectsof strong and weak data typing. Teaching an assembly language that can operate onbit, byte, word and long word operands helps students understand data types.Moreover, the ability to perform any type of assembly language operation on anytype of data structure demonstrates the need for strong typing.

� Addressing Modes: A vital component of assembly language teaching is addressingmodes (literal, direct and indirect). The student learns how pointers function andhow pointers are manipulated. This aspect is particularly important if the student isto become a C programmer. Because an assembly language is unencumbered bydata types, the students’ view of pointers is much simplified by an assembly language.The 68020 has complex addressing modes that support double indirection and themanipulation of tables of pointers.

� The Stack and Subroutines: In my teaching I now emphasize how procedures arecalled, and parameters passed and returned from procedures. By using an assemblylanguage you can readily teach the passing of parameters by value and by reference.The use of local variables and re-entrant programming can also be taught. This supportsthe teaching of task switching kernels in both operating systems and real-timeprogramming.

� Recursion: The recursive calling of subroutines often causes student problems. Youcan use an assembly language, together with a suitable system with a tracing facility,to demonstrate how recursion operates. The student can actually observe how thestack grows as procedures are called.

� Run-time Support for High-level Languages: A high-performance processor like the68020 provides facilities that support run-time checking in high-level languages.For example, the CHK2 instruction provides automatic checking of array bounds atrun-time (if an array element is out of bounds, an operating system call is made).The 68000 also provides run-time checking for errors such as an attempt to divide anumber by zero.

� Protected-mode Operation: Members of the 68000 family operate in either a supervisormode or a user mode. The operating system operates in the supervisor mode and alluser (applications) programs run in the user mode. This mechanism can be used toconstruct secure or protected environments in which the effects of an error in oneapplication can be prevented from harming the operating system (or otherapplications).

� Input-output: Many high-level languages make it difficult to access I/O ports anddevices directly. By using an assembly language we can teach students how to writedevice drivers and how to control interfaces. Most real interfaces are still programmedat the machine level by accessing registers within them.

All these topics can, of course, be taught in the appropriate courses (e.g. high-levellanguages, operating systems). However, by teaching them in an assembly languagecourse, they pave the way for future studies, and also show the student exactly what ishappening within the machine.

Conclusion

A strong case can be made for the continued teaching of assembly language within thecomputer science curriculum. However, an assembly language cannot be taught just as if

Contd...



Notesit were another general-purpose programming language as it was once taught ten yearsago. Perhaps more than any other component of the computer science curriculum, teachingan assembly language supports a wide range of topics at the heart of computer science. Anassembly language should not be used just to illustrate algorithms, but to demonstratewhat is actually happening inside the computer.

Questions:




Source: http://www.scm.tees.ac.uk/users/u0000408/CaseFor.htm

Self Assessment


13. Imperative paradigm deals with classes and methods

14. Functional languages emphasize the transformations of values

15. Define a problem by describing its facts and properties, and then solve it by giving thesystem a goal to prove using those facts and properties is a fact followed by Imperativeparadigm.

2.5 Summary

� Processor understands only machine language instructions which are strings of 1s and 0s.

� Assembly language is a low-level programming language for a computer.

� Assembly language is converted into executable machine code by a utility program referredto as an assembler like NASM, MASM.

� The assembler produces an object file.

� Opcodes are reserved words that correspond to machine instructions.

� Operands are the part of an instruction on which an operator acts upon.

� The label field occurs as the first field of a source statement. It can be a space, * or symbol.

� Comments are messages intended only for human consumption. They have no effect onthe translation process.

� A pseudo-operation, commonly called a pseudo-op, is an instruction to the assembler thatdoes not generate any machine code.

� A statement in pure assembly language corresponds to one machine instruction.

� Object Oriented Paradigm deals with classes and methods.

� Functional languages emphasize the transformations of values.

2.6 Keywords

Assembler: It is used to convert Assembly language into executable machine code.

Assembly Language: It is a low-level programming language for a computer.



Notes Logic paradigm: It defines a problem by describing its facts and properties, and then solves it bygiving the system a goal to prove using those facts and properties.

Object File: The file given as an output by the assembler.

Opcodes: They are reserved words that correspond to machine instructions.

Operands: They are the part of an instruction on which an operator acts upon.

Parallel Languages: If actions don’t interact, work on them in any order (non-determinism), oreven simultaneously (multi-processing).

Pseudo-op: It is an instruction to the assembler that does not generate any machine code.


1. What is assembly language?

2. List the advantages of assembly language.

3. What are the steps followed to run a program written in assembly language?

4. Differentiate between an opcode and an operand.

5. Define labels. Explain its use.

6. What is a comment? Does it affect the translation process?

7. Write a note on pseudo-ops.

8. Discuss the assembly process.

9. What are assembly language statements?

10. Explain the various programming paradigms used in programming languages.

Answers: Self Assessment

1. Low Level 2. Assembler

3. Object 4. Opcode

5. Operand 6. Label

7. Comments 8. Pseudo-op

9. False 10. True

11. Statement 12. Pseudo Instructions

13. False 14. True

15. False



Ramesh S. Gaonkar, Microprocessor Architecture, Programming and Applications withthe 8085.



NotesSunil Mathur, Microprocessor 8085 and Its Interfacing.


Online links http://cs.smith.edu/~thiebaut/ArtOfAssembly/CH01/CH01-1.html#HEADING1-30

http://www.swansontec.com/sprogram.html

http://en.wikipedia.org/wiki/Assembly_language

http://www.tutorialspoint.com/assembly_programming/index.htm



Notes Unit 3: Assembly Language Programming of 8085

CONTENTS

Objectives

Introduction

3.1 The 8085 Programming Model

3.1.1 Control Unit

3.1.2 Registers

3.1.3 Accumulator

3.1.4 Flags

3.1.5 Program Counter (PC)

3.1.6 Stack Pointer (SP)

3.1.7 Instruction Register/Decoder

3.1.8 Memory Address Register

3.1.9 Control Generator

3.1.10 Register Selector

3.1.11 General Purpose Registers

3.1.12 Microprogramming

3.2 Instruction Set Classification

3.2.1 Data Transfer (Copy) Operations

3.2.2 Logical Operations

3.2.3 Branching Operations

3.2.4 Machine Control Operations







3.4 Instruction Format

3.4.1 One-byte Instruction

3.4.2 Two-byte Instruction

3.4.3 Three-byte Instruction

3.5 Sample Program

3.6 SummaryContd...


Unit 3: Assembly Language Programming of 8085

Notes3.7 Keywords



Objectives


� Understand the 8085 Programming Model

� Explain the 8085 Addressing Modes

� Discuss the Instruction Set Classification

� Describe Instruction Format

� Understand how to program

Introduction

One of the first microprocessors was the Intel 8085 microprocessor released in the late 1970s. TheIntel 8085 microprocessor was the successor to Intel’s 8080 processing unit, whose most prominentfeatures were that of increased compatibility and a much simpler voltage requirement. The Intel8085 microprocessor saw its greatest use not as a system processor, but rather as a microcontrollerfor many other hardware applications.

3.1 The 8085 Programming Model

The structure of an 8085 microprocessor is given below:

Source: http://www.phy.davidson.edu/fachome/dmb/py310/8085.pdf

Figure 3.1: 8085 Programming Model



Notes 3.1.1 Control Unit

It generates signals within uP to carry out the instruction, which has been decoded. In realitycauses certain connections between blocks of the uP to be opened or closed, so that data goeswhere it is required, and so that ALU operations occur. The ALU performs the actual numericaland logic operation such as ‘add’, ‘subtract’, ‘AND’, ‘OR’, etc. It uses data from memory andAccumulator to perform arithmetic and stores result of operation in Accumulator.

3.1.2 Registers

The 8085/8080A-programming model includes six registers, one accumulator, and one flagregister, as shown in Figure 3.1. In addition, it has two 16-bit registers: the stack pointer and theprogram counter. They are described briefly as follows. The 8085/8080A has six general-purposeregisters to store 8-bit data; these are identified as B, C, D, E, H, and L as shown in the figure 3.1.They can be combined as register pairs – BC, DE, and HL – to perform some 16-bit operations.The registers can be used to store or copy data into the registers by using data copy instructions.

3.1.3 Accumulator

The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This register isused to store 8-bit data and to perform arithmetic and logical operations. The result of anoperation is stored in the accumulator. The accumulator is also identified as register A.

3.1.4 Flags

The ALU includes five flip-flops, which are set or reset after an operation according to dataconditions of the result in the accumulator and other registers. They are called Zero (Z), Carry(CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags. The most commonly used flags areZero, Carry, and Sign. The microprocessor uses these flags to test data conditions.

Example: After an addition of two numbers, if the sum in the accumulator id larger thaneight bits, the flip-flop uses to indicate a carry – called the Carry flag (CY) – is set to one. Whenan arithmetic operation results in zero, the flip-flop called the Zero (Z) flag is set to one. The firstfigure shows an 8-bit register, called the flag register, adjacent to the accumulator. However, itis not used as a register; five bit positions out of eight are used to store the outputs of the fiveflip-flops. The flags are stored in the 8-bit register so that the programmer can examine theseflags (data conditions) by accessing the register through an instruction.

These flags have critical importance in the decision-making process of the microprocessor. Theconditions (set or reset) of the flags are tested through the software instructions. For example,the instruction JC (Jump on Carry) is implemented to change the sequence of a program whenCY flag is set. The thorough understanding of flag is essential in writing assembly languageprograms.

3.1.5 Program Counter (PC)

The instructions are sequenced and the executed using this 16-bit register. This register is amemory pointer. Memory locations have 16-bit addresses, and that is why this is a 16-bit register.The microprocessor uses this register to sequence the execution of the instructions. The functionof the program counter is to point to the memory address from which the next byte is to befetched. When a byte (machine code) is being fetched, the program counter is incremented byone to point to the next memory location.



Notes3.1.6 Stack Pointer (SP)

The stack pointer is also a 16-bit register that points to a memory location in R/W memory,called the stack. The beginning of the stack is defined by loading 16-bit address in the stackpointer.

3.1.7 Instruction Register/Decoder

It is temporary store for the current instruction of a program. Latest instruction is sent here frommemory prior for execution. The decoder then takes in the instruction and ‘decodes’ or interpretsit Decoded instruction then passed to next stage.

3.1.8 Memory Address Register

It holds address that is received from the PCof next program instruction. It then inputs theaddress bus with addresses of location of the program under execution.

3.1.9 Control Generator

Generates signals within uP to carry out the instruction which has been decoded. In reality itcauses certain connections between blocks of the uP to be opened or closed, so that data goeswhere it is required, and so that ALU operations occur.

3.1.10 Register Selector

This block controls the use of the register stack in the example. Just a logic circuit which switchesbetween different registers in the set will receive instructions from Control Unit.

3.1.11 General Purpose Registers

uP requires extra registers for versatility. Can be used to store additional data during a program?More complex processors may have a variety of differently named registers.

3.1.12 Microprogramming

How does the μP know what an instruction means, especially when it is only a binary number?The micro program in a uP/uC is written by the chip designer and tells the uP/uC the meaningof each instruction uP/uC can then carry out operation.

Self Assessment

Fill in the blanks:

1. …………………… generates signals within uP to carry out the instruction, which has beendecoded.

2. The accumulator is an ………………… bit register that is a part of arithmetic/logic unit(ALU).

3. …………………… is a temporary store for the current instruction of a program.

4. …………………… holds address, received from PC, of next program instruction.

5. …………………… generates signals within uP to carry out the instruction which has beendecoded.



Notes 3.2 Instruction Set Classification

An instruction is a binary pattern designed inside a microprocessor to perform a specific function.These instructions are grouped to form a call instruction set. They determine what functions themicroprocessor can perform. These instructions can be classified into the following five functionalcategories: data transfer (copy) operations, arithmetic operations, logical operations, branchingoperations and machine-control operations.

3.2.1 Data Transfer (Copy) Operations

This group of instructions copy data from a location called a source to another location called adestination, without modifying the contents of the source. In technical manuals, the term datatransfer is used for this copying function. However, the term transfer is misleading; it creates theimpression that the contents of the source are destroyed when, in fact, the contents are retainedwithout any modification. The various types of data transfer (copy) are listed below togetherwith examples of each type:

3.2.2 Logical Operations

These instructions perform various logical operations with the contents of the accumulator.

� AND, OR Exclusive-OR: Any 8-bit number, or the contents of a register, or of a memorylocation can be logically ANDed, Ored, or Exclusive-ORed with the contents of theaccumulator. The results are stored in the accumulator.

� Rotate: Each bit in the accumulator can be left or right shifted to the next position.

� Compare: Any 8-bit number, register contents, or a memory location can be compared forequality, greater than, or less than, with the contents of the accumulator.

� Complement: The contents of the accumulator can be complemented. All 0s are replacedby 1s and all 1s are replaced by 0s.

3.2.3 Branching Operations

This group of instructions alters the sequence of program execution either conditionally orunconditionally.

� Jump: Conditional jumps are an important aspect of the decision-making process in theprogramming. These instructions test for a certain conditions (e.g., Zero or Carry flag)and alter the program sequence when the condition is met. The instruction set also includesan instruction called unconditional jump.



Notes� Call, Return, and Restart: These instructions change the sequence of a program either bycalling a subroutine or returning from a subroutine. The conditional Call and Returninstructions also can test condition flags.

3.2.4 Machine Control Operations

These instructions control machine functions such as Halt, Interrupt, or do nothing. Themicroprocessor operations related to data manipulation can be summarized in four functions:

1. Data Copy

2. Perform arithmetic operations

3. Perform logical operations

4. Test for a given condition and alerting the program sequence

Self Assessment


6. The entire group of instructions determine what functions the microprocessor can perform.

7. Data Transfer (Copy) Operations modify the contents of the source.

8. Logical Operations perform various logical operations with the contents of the programcounter.

9. Branching Operations alters the sequence of program execution either conditionally orunconditionally.


The microprocessor has different ways of specifying the data for the instruction. These are called“addressing modes”. To perform any operation, we have to give the corresponding instructionsto the microprocessor. In each instruction, programmer has to specify the following:

� Operation to be performed.

� Address of source of data.

� Address of destination of result.

Let us discuss some of these modes in detail.


In this type of addressing mode, No operand (register or data) is specified in the instruction. Theoperand is inherent to the instruction.

Example: CMA (Complement Accumulator), SIM, RIM, etc.


In register indirect addressing mode, the instruction specifies the name of the register in whichthe address of the data is available. Here the data will be in memory and the address will be inthe register pair.



NotesExample: MOV A, M – The memory data addressed by H L pair is moved to

A register, LDAX B.


In immediate addressing mode, the data is specified in the instruction itself. The data will be apart of the program instruction.

Example: MVI B, 3EH – Move the data 3EH given in the instruction to B register;LXI SP, 2700H.


In this mode, the address of the operand is given in the instruction itself.


� LDA is the operation.

� 2500 H is the address of source.

� Accumulator is the destination.


In this mode, the address of operand is specified by a register pair.


� MOV is the operation.

� M is the memory location specified by H-L register pair.

� A is the destination

Self Assessment

Fill in the blanks:

10. The way of the microprocessor to specify the data for the instruction is called…………………….

11. In …………………… addressing no operand (register or data) is specified in the instruction.

12. In …………………… addressing mode, the instruction specifies the name of the register inwhich the address of the data is available.

Figure 3.2: Direct Addressing

Figure 3.3: Register Indirect Addressing



Notes13. In …………………… addressing mode, the data is specified in the instruction itself.

14. In …………………… addressing mode, the address of the operand is given in the instructionitself.

15. In …………………… addressing mode, the address of operand is specified by a registerpair.


A command sent to the microprocessor in order to perform a given task on specific data is aninstruction. It comprises of: the task to be performed, called the operation code (op-code), andthe data to be operated on, called the operand. The operand (or data) can be specified in variousways. It may include 8-bit (or 16-bit) address. Sometimes the operand is implicit. As per the sizeof the word the 8085 instruction set can be divided as three groups. In the 8085, “byte” and“word” are synonymous because it is an 8-bit microprocessor. However, instructions arecommonly referred to in terms of bytes rather than words.

� 1-byte instruction



3.4.1 One-byte Instruction

They use 8 bits of memory and include the op-code and the operand in the same byte. Theop-code and operand will be default in this case.

Example:

(i) MOV Z,X

(ii) ADD A

(iii) CMA

Here, the above instructions are 1-byte instructions performing three different tasks. In the firstinstruction, the content of the accumulator is copied in the register Z. In this instruction, MOV isthe op-code and register Z and accumulator are operand.

In the second instruction, the content of register A is added to the content of the accumulator. Inthis instruction, ADD is the op-code and register X is the operand.

In the third instruction, each bit of the accumulator is inverted (complemented). In this instruction,CMA is the op-code and the operand is assumed to be the implicit operand. These instructionsare stored in 8-bit binary format in the memory.

3.4.2 Two-byte Instruction

Here the first byte gives the op-code and the second byte the operand. The total memory used isof two bytes.

Example:

(i) MVI C, 32H

(ii) MOV D, F2H



Notes Here, the first instruction loads an 8-bit data byte in the accumulator. In this instruction, MVI isthe op-code and C, 32H are the operand. Similarly, the second instruction loads an 8-bit databyte in the register B an in this instruction, D, F2 are the operand. Hence, these instructionswould require two memory locations each to store the binary codes. The data bytes 32H andF2H are selected arbitrarily.

3.4.3 Three-byte Instruction

They take up three bytes where the first byte specifies the op-code, and the following two bytesspecify the 16-bit address. That is, the second byte is the low-order address and the third byte isthe high-order address.

Example:

(i) LDA 2050H,

(ii) JMP 2085H.

Here, in the first instruction, the contents of the memory location 2050H is the operand. And inthe second instruction, the sequence of the program is transferred to the memory location2085H. In this instruction, JMP is the op-code and 2085H is the operand. Hence, these instructionswould require there memory locations each to store the binary codes.

3.5 Sample Program

Probably the most famous of all beginning programs, at least for C language programmers, isone that prints “Hello World!”. Example below is a simple program doing just that.

The sample program in the above code has several parts. The listing you see is called the .LSTfile and is produced by the HC12 assembler to use when debugging and documenting your



Noteswork. It shows, from left to right in columns, (1) Abs., the absolute line number for the sourcecode including all include files and macro lines; (2) Rel., the relative line number showing eachline in the current source file; (3) Loc, the address in memory in which the assembled code isfound; (4) Obj. code, the assembled code bytes and finally (5) Source line, the source code withlabel, opcode, operand and comment fields. In this program lines 1 - 4 are comments that introducethe program. Line 7 uses an assembler directive, called an equate or EQU, to define the value usedfor the symbol.

EOS: This defines the code-byte that signifies the end of the message to be printed on theterminal (such as the null byte at the end of a string in a C program). Line 8 - 14 defines symbolsto be used by the linker including the Entry point and a subroutine, printf which is to do theactual printing. The actual program code appears in lines 17 to 24. The stack pointer register isinitialized (line 18), the message is printed (lines 20 - 21) and the program terminates by enteringa spin loop where it stays until the microcontroller is reset. At the bottom of the program (line36), an assembler directive, DC.B, defines the message Hello World!

�Case Study The Assembly Language Development System

(ALDS)

The Genesis of ALDS

In the earliest days of software development at Tandy, the Z80 assembly languagedevelopment for the TRS-80 and Tandy brands of personal computers work was doneusing a few different packages, including EDTASM, and one or more Z80 cross-assemblers(probably commercial products) that ran on a Tandem mainframe.

The Tandem mainframe was owned and operated by the Tandy Data Processing department,known internally simply as “DP”, and the main functions of DP was to print pay checks,key-punch data from stores and tally store sales. In the first few years of the TRS-80product line, the DP department had some spare computer time, so the early TRS-80developers were allowed to use these systems. In addition, some smaller products weredeveloped and assembled using the TRS-80s themselves, but at the time these were allfloppy-based systems, and that greatly limited how large of a product could be producedusing such a small development system.

At this time, the Z80-based computers being used had between 100K and 500K of storageavailable on each floppy diskette, and you really only had three disk drives you could usefor software development at any moment (with the fourth drive consumed with theoperating system and maybe the assembler itself). Therefore, the small amount of diskettestorage was the main restriction, and anything that could be done to divide that up was agreat help.

Around 1980, the TRS-80 software developers were ordered to get off the mainframecomputers in DP because they were using too much of the available resources. To replacethe development platform that was still needed for assembling large programs, a DigitalEquipment Corporation VAX 11/780 was purchased in 1980 or early 1981 specifically forTandy Software Design (TSD). The VAX system ran the VMS operating system up until thefall of 1982, when it was converted to BSD 4.1 UNIX. The VAX, known as “trsvax” and laterknown as “trsvax.tandy.com” was upgraded to BSD 4.3 in the mid-1980s and continuedto run BSD UNIX until it left service in 1990. (The functions of trsvax were migrated to a386-based PC running SCO UNIX, which continued in service until 1996.)

Contd...



Notes Initially, commercial third-party assemblers were used on the VAX. In addition, a few Ccompilers were tried that the early developers experimented with and used for writingin-house tools.

(Despite there being a number of C compilers purchased by TSD during the VMS period,there is no evidence that any software developed and sold by Tandy was written in C priorto the end of 1982. The first known program written in “C” that was sold by Tandy was thetx file transfer utility. It was originally developed for UNOS, but was eventually ported toand bundled with XENIX for the Model 16.)

At some point, Ron Light (who was one of the programmers in TSD) developed a Z80-assembler and linker for use on the VAX. It remains unclear whether this was a sanctionedproject or one or the numerous “black projects” developed outside official channels thatwere common within TSD.

Ron’s assembler and linker were known simply as “ALDS”, and gradually grew into afairly sophisticated system, complete with a full-featured assembler macro and relocationcapabilities, as well as a linker for building even more complex programs. Notably, thelinker was very useful in creating the overlays common to the operating systems of thatperiod.

ALDS was written in C, and was initially used on the VAX VMS platform. Later it wasported again with minimal changes to the BSD UNIX operating system running on thesame VAX 11/780. Years later, a small port of the BSD UNIX version allowed ALDS to berun on the Tandy 68000 XENIX operating systems, and finally ported to compile on GCCunder the FreeBSD UNIX environment.

Most of what became known as TRSDOS-II (Tandy’s operating system for the Model II/12family) and the Z80 components of TRSDOS-16 were written using the “ALDS” assemblerand linker on the VAX server, and for a few more years, most Tandy Z80 programs wereassembled using this platform. There were even some unexpected products, like a mini-telephone PBX system (known internally as Project 20) which relied on the ALDS cross-platform development capabilities. Because of this continued use of ALDS within Tandythrough the mid-1980s, additional features and support for new processors were added,along with bug fixes.

Sadly, Ron Light was killed in a traffic accident in May of 1989. He was one of threeprogrammers from the early Tandy Computers days to die in separate traffic accidentsover the years.

ALDS becomes a Consumer Product

In late 1981, Tandy began selling an 8 Megabyte hard disk system that could be connectedto the Model II system, using TRSDOS-II. This now made it somewhat practical to assemblelarge programs on the Model II systems, and it was eventually decided to do a port of theALDS assembler to these Z80-based systems.

Initially, the plan was to find a “C” compiler suitable for the TRSDOS environment, butafter much searching, none could be found that would meet all the demands placed on it.So the decision was made to have programmers write Z80 assembly language code thatwould mimic each function of the original “C” ALDS assembler and linker. Some featureswere clearly unnecessary (like having the assembler is able to send e-mail once the assemblywas complete), so a number of the existing ALDS assembly options were not included inthe Z80 implementation.

Exactly who this development was originally meant for is not clear. There was a desire tobe able to do assembly on the desktops, without having to deal with the user limits

Contd...



Notesimposed by the VAX VMS operating system (another reason for the subsequent switch toBSD UNIX), and it was also thought some third party developers might benefit fromhaving a native assembler available.

Based on the realization that now the TRS-80 themselves could finally be used to puttogether fairly complex assembly-language packages (particularly if developers boughtsome of those 8 Megabyte hard disk drives that Tandy was selling for $5,999 US), Tandydecided to package, expand and sell the Z80 assembler and linker, plus develop someadditional tools to round out the package. The combined package was also called “ALDS”,and around 1982, Tandy began to market ALDS for the Model II environment through theRadio Shack stores. Versions of ALDS for the Model III, and Model 4 were eventuallyprepared and sold.

The consumer ALDS package included the ALDS assembler (now coded in Z80 assemblylanguage and now named ALASM), the Z80-assembly language version of the linker (nownamed ALLINK), a screen-based debugging system (ALDEBUG), a screen-based editor(ALEDIT), and a simple file transfer utility for moving files and programs between thesefour platforms (ALTRAN).

The ALEDIT, ALDEBUG and ALTRAN components of the ALDS system were initiallydeveloped in 1981 and 1982 mainly for the retail product, but were simultaneously beingused in-house to develop other software. These components were never written in “C” forthe VAX, mainly because both VAX operating systems came with editors, and each had atleast one file transfer utility. In addition to writing the new tools that formed the consumerALDS product, the original assembler and linker received some clean-up and polishing, aswell as the inevitable introduction of a few bugs that the C-based version did not have.

Developers of Model 4 Port of ALDS

In my first year at Tandy, I got to test the Model 4 version of ALDS, along with othermembers of the Quality Assurance department, where I worked at that time. I had alreadybeen using the Model II version for development of programs to test operating systems.The testing work on the Model 4 ALDS version occurred in March and April of 1983, withthe Model 4 computer itself being announced to the public during March 1983.

I still have some of the Software Performance Reports from the Model 4 ALDS testingeffort, and these reports provide some details on who was doing development on ALDS atthat time. (The phrase “Software Performance Reports (or SPR) was the title of the formsthat Digital Equipment Corporation made customers fill out in order to report bugs thatthe customer found in DECs software or hardware. This phrase was more politicallycorrect and generic than ‘Bug Report” form, so I got TSD-QA to use this instead of thehandwritten forms used previously.)

Based on the Tandy SPRs, Richard Hay was probably the project leader for Model 4 ALDSport, and Larry West was also working on the package. I’m pretty sure that Carole Waltonwas also working on ALDS components, although her name does not appear on any of theModel 4 reports I still have.

The QA testers included me, George Moore, Jim R., Kim Hoffpauir, and Shauna McManigal.(Kim and Jim appear to have generated the bulk of the problem reports on this product.)

The Model 4 version was essentially a port of the Model II version, but because the twooperating systems were very different, a lot of work had to be re-done, particularly in thearea of the debugger, screen editor and transfer utility. In addition to Mr, Hay, West andMrs Walton, I am sure that there were other engineers working on the Model 4 ALDSproject at various times. However, Richard responded to most of the SPRs instead of theindividual engineers, so I don’t have any further information.

Contd...



Notes It should be noted that a Model III version of ALDS was also produced, but it came out afterthe Model II and Model 4 versions did. The Model 4 version had priority in order to helpboost the number of software titles available for that new computer system.

Possible Pre-Tandy Source of Concepts for the ALDS Assembler (ALASM)

In 1990, I was cleaning out a filing closet at Tandy that was full of old Z80 and 68000software-related materials that dated back to 1978. In this material (that management hadnow ordered be discarded simply because it was there), I came across a binder marked“ALDS Base Paper”. Inside the binder was a short article published by BYTE magazine in1979, with the title “A Z80 Assembler”, written by Patrick A Crowe, then of SwindonEngland. The title on the binder interested me, so I saved these papers. These documentseventually got stored in a box of other Model 4 stuff, where it remained forgotten formany years.

In 2004, a review of the 1979 article suggests that it could have contributed some of theideas behind the development of the ALASM component ALDS. In my opinion, bothprograms use some common terminology internally, but they are not copies of one another.

The comparison makes it pretty clear that ALASM is not copied from Mr. Crowes absolute-only assembler. That was originally written in Z80 assembler, while the original aldsassembler was written in C. Further, the similarity of terminology that is seen may comefrom other common sources, as Mr. Crowe credits assembler structure information thathe found in Zilog and Intel application manuals that Tandy engineers of that periodwould have also possessed.

It should also be mentioned that Mr. Crowes assembler produced absolute binary formatfiles only and had no relocation/linker or macro capabilities, these features existed in theoriginal “C” version of ALDS, and an editor, debugger and file transfer utility were addedto ALDS for the Model II, Model III and Model 4 versions.

Questions:




Source: http://nemesis.lonestar.org/computers/tandy/software/tools/alds/history.html

Self Assessment


16. The op-code and operand will be default in a two byte instruction

17. A command sent to the microprocessor in order to perform a given task on specific data isan instruction

3.6 Summary

� The Intel 8085 microprocessor was one of the first microprocessors released by Intel in thelate 1970s.

� An instruction is a binary pattern designed inside a microprocessor to perform a specificfunction.

� The entire group of instructions, called the instruction set, determines what functions themicroprocessor can perform.



Notes� The microprocessor has different ways of specifying the data for the instruction. These arecalled “addressing modes”.

� In Implied Addressing mode, No operand (register or data) is specified in the instruction.

� In register indirect addressing mode, the instruction specifies the name of the register inwhich the address of the data is available.

� In immediate addressing mode, the data is specified in the instruction itself.

� In Direct Addressing mode, the address of the operand is given in the instruction itself.

� A command sent to the microprocessor in order to perform a given task on specific data isan instruction.

3.7 Keywords

Accumulator: It is an 8-bit register that is a part of arithmetic/logic unit (ALU).

Control Generator: It generates signals within uP to carry out the instruction which has beendecoded.

Control Unit: It generates signals within uP to carry out the instruction, which has been decoded.

Instruction Register/Decoder: It is a temporary store for the current instruction of a program.

Instruction: It is a binary pattern designed inside a microprocessor to perform a specific function.

Memory Address Register: It Holds address, received from PC, of next program instruction.

Program Counter (PC): This 16-bit register deals with sequencing the execution of instructions.

Stack pointer: It is also a 16-bit register used as a memory pointer.


1. Explain the 8085 Programming model in detail.

2. What is the function of a control unit?

3. Explain the role of an accumulator in 8085.

4. Write a short note on Data Copy Operations.

5. Discuss the Logical Operations in the 8085 microprocessor.

6. Define an instruction.

7. Differentiate between an operand and an operator.

8. Explain the instruction set of the 8085 microprocessor.

9. Write a short note on One-byte instruction.

10. Write a short program in assembly language.


1. Control Unit 2. 8

3. Instruction Register 4. Memory Address Register

5. Control Generator 6. True



Notes 7. False 8. False

9. True 10. Addressing Modes

11. Implied 12. Register indirect

13. Immediate 14. Direct

15. Register Indirect 16. False

17. True


Books Jeff Duntemann, Assembly Language Step-by-step: Programming with DOS and Linux.

Robert Lafore, Assembly Language Primer for the IBM PC.

Vlad Pirogov, The Assembly Programming Master Book.

Randall Hyde, The Art of Assembly Language.

Online links http://itsnka.files.wordpress.com/2010/10/mpmanual-first-ver.pdf

http://wiki.answers.com/Q/Explain_the_classification_of_the_instruction_set_of_8085_microprocessor_with_suitable_examples

http://www.iitg.ernet.in/asahu/cs421/Lects/Lec03.pdf

http://www.phy.davidson.edu/fachome/dmb/py310/8085.pdf


Unit 4: Microprocessor Architecture

NotesUnit 4: Microprocessor Architecture

CONTENTS

Objectives

Introduction

4.1 Microprocessor

4.2 Architecture of Microprocessor

4.3 Microprocessor Operations

4.4 Microprocessor Memory

4.4.1 Hard Disk Drives

4.4.2 RAM

4.4.3 SRAM

4.4.4 DRAM

4.4.5 Other RAM

4.5 Summary

4.6 Keywords



Objectives


� Understand the concept of Microprocessor

� Discuss Microprocessor Architecture

� Explain Microprocessor Operations

� Define the various types of memory used in Microprocessors

Introduction

The microprocessor is sometimes referred to as the ‘brain’ of the personal computer, and isresponsible for the processing of the instructions which make up computer software. It consistsof the central processing unit, commonly referred to as the CPU.

The first microprocessor to make it into a home computer was the Intel 8080, a complete 8-bitcomputer on one chip, introduced in 1974. The first microprocessor to make a real splash in themarket was the Intel 8088, introduced in 1979 and incorporated into the IBM PC (which firstappeared around 1982). PC market moved from the 8088 to the 80286 to the 80386 to the 80486 tothe Pentium to the Pentium II to the Pentium III to the Pentium 4. All of these microprocessorsare made by Intel and all of them are improvements on the basic design of the 8088.



Notes 4.1 Microprocessor

Since 2004, Intel has introduced microprocessors with multiple cores and millions moretransistors. But even these microprocessors follow the same general rules as earlier chips.

Source: http://computer.howstuffworks.com/microprocessor1.htm

In the table above:

� The date is the year that the processor was first introduced. Many processors are re-introduced at higher clock speeds for many years after the original release date.

� Transistors are the number of transistors on the chip. You can see that the number oftransistors on a single chip has risen steadily over the years.

� Microns are the width, in microns, of the smallest wire on the chip. For comparison, ahuman hair is 100 microns thick. As the feature size on the chip goes down, the number oftransistors rises.

� Clock speed is the maximum rate that the chip can be clocked at.

� Data Width is the width of the ALU. An 8-bit ALU can add/subtract/multiply/etc. two 8-bit numbers, while a 32-bit ALU can manipulate 32-bit numbers. An 8-bit ALU would haveto execute four instructions to add two 32-bit numbers, while a 32-bit ALU can do it in oneinstruction. In many cases, the external data bus is the same width as the ALU, but notalways. The 8088 had a 16-bit ALU and an 8-bit bus, while the modern Pentiums fetch data64 bits at a time for their 32-bit ALUs.

� MIPS stand for “millions of instructions per second” and are a rough measure of theperformance of a CPU. Modern CPUs can do so many different things that MIPS ratingslose a lot of their meaning, but you can get a general sense of the relative power of theCPUs from this column.

From this table you can see that, in general, there is a relationship between clock speed andMIPS. The maximum clock speed is a function of the manufacturing process and delays withinthe chip. There is also a relationship between the number of transistors and MIPS. For example,the 8088 clocked at 5 MHz but only executed at 0.33 MIPS (about one instruction per 15 clockcycles). Modern processors can often execute at a rate of two instructions per clock cycle.

Table 4.1: History of Computers



Notes

Did u know? The Pentium 4 can execute any piece of code that ran on the original 8088, butit does it about 5,000 times faster.

Self Assessment

Fill in the blanks:

1. The first microprocessor to make it into a home computer was the Intel …………………….

2. …………………… is the width of the smallest wire on the chip.

3. …………………… is the maximum rate that the chip can be clocked at.

4. …………………… is the width of the ALU.

4.2 Architecture of Microprocessor

A microprocessor executes a group of machine instructions that tell the processor what to do.Based on the instructions, a microprocessor does three basic things:

� The ALU (Arithmetic/Logic Unit) helps to perform mathematical operations like addition,subtraction, multiplication and division. Modern microprocessors contain complete floatingpoint processors that can perform extremely sophisticated operations on large floatingpoint numbers.

� A microprocessor can move data from one memory location to another.

� A microprocessor can make decisions and jump to a new set of instructions based on thosedecisions.

There may be very sophisticated things that a microprocessor does, but those are its three basicactivities. The following diagram shows an extremely simple microprocessor capable of doingthose three things:

Source: http://computer.howstuffworks.com/microprocessor2.htm

Figure 4.1: Microprocessor Architecture



Notes This is about as simple as a microprocessor gets. This microprocessor has:

� An address bus (that may be 8, 16 or 32 bits wide) that sends an address to memory

� A data bus (that may be 8, 16 or 32 bits wide) that can send data to memory or receive datafrom memory

� An RD (read) and WR (write) line to tell the memory whether it wants to set or get theaddressed location

� A clock line that lets a clock pulse sequence the processor

� A reset line that resets the program counter to zero (or whatever) and restarts execution

Example: Let’s assume that both the address and data buses are 8 bits wide in thisexample.

Here are the components of this simple microprocessor:

� Registers A, B and C are simply latches made out of flip-flops.

� The address latch is just like registers A, B and C.

� The program counter is a latch with the extra ability to increment by 1 when told to do so,and also to reset to zero when told to do so.

� The ALU could be as simple as an 8-bit, or it might be able to add, subtract, multiply anddivide 8-bit values. Let’s assume the latter here.

� The test register is a special latch that can hold values from comparisons performed in theALU. An ALU can normally compare two numbers and determine if they are equal, if oneis greater than the other, etc. The test register can also normally hold a carry bit from thelast stage of the adder. It stores these values in flip-flops and then the instruction decodercan use the values to make decisions.

� There are six boxes marked “3-State” in the diagram. These are tri-state buffers. A tri-statebuffer can pass a 1, a 0 or it can essentially disconnect its output (imagine a switch thattotally disconnects the output line from the wire that the output is heading toward). A tri-state buffer allows multiple outputs to connect to a wire, but only one of them to actuallydrive a 1 or a 0 onto the line.

� The instruction register and instruction decoder are responsible for controlling all of theother components.

Although they are not shown in this diagram, there would be control lines from the instructiondecoder that would:

� Tell the A register to latch the value currently on the data bus

� Tell the B register to latch the value currently on the data bus

� Tell the C register to latch the value currently output by the ALU

� Tell the program counter register to latch the value currently on the data bus

� Tell the address register to latch the value currently on the data bus

� Tell the instruction register to latch the value currently on the data bus

� Tell the program counter to increment

� Tell the program counter to reset to zero



Notes� Activate any of the six tri-state buffers (six separate lines)

� Tell the ALU what operation to perform

� Tell the test register to latch the ALU’s test bits

� Activate the RD line

� Activate the WR line

Coming into the instruction decoder are the bits from the test register and the clock line, as wellas the bits from the instruction register.

The address and data buses and the RD and WR lines connect either to RAM or ROM – generallyboth. In our sample microprocessor, we have an address bus 8 bits wide and a data bus 8 bitswide. That means that the microprocessor can address (28) 256 bytes of memory, and it can reador write 8 bits of the memory at a time. Let’s assume that this simple microprocessor has 128bytes of ROM starting at address 0 and 128 bytes of RAM starting at address 128.

� ROM stands for read-only memory. A ROM chip is programmed with a permanent collectionof pre-set bytes. The address bus tells the ROM chip which byte to get and place on the databus. When the RD line changes state, the ROM chip presents the selected byte onto the databus.

� RAM stands for random-access memory. RAM contains bytes of information, and themicroprocessor can read or write to those bytes depending on whether the RD or WR lineis signalled. One problem with today’s RAM chips is that they forget everything once thepower goes off. That is why the computer needs ROM.

Nearly all computers contain some amount of ROM (it is possible to create a simple computerthat contains no RAM – many microcontrollers do this by placing a handful of RAM bytes on theprocessor chip itself – but generally impossible to create one that contains no ROM). On a PC, theROM is called the BIOS (Basic Input/Output System). When the microprocessor starts, it beginsexecuting instructions it finds in the BIOS. The BIOS instructions do things like test the hardwarein the machine, and then it goes to the hard disk to fetch the boot sector. This boot sector isanother small program, and the BIOS stores it in RAM after reading it off the disk. Themicroprocessor then begins executing the boot sector’s instructions from RAM. The boot sectorprogram will tell the microprocessor to fetch something else from the hard disk into RAM,which the microprocessor then executes, and so on. This is how the microprocessor loads andexecutes the entire operating system.

Self Assessment


5. Using its ALU (Arithmetic/Logic Unit), a microprocessor can perform mathematicaloperations.

6. A data bus sends an address to memory.

7. ROM is a volatile memory.

8. On a PC, the RAM is called the BIOS.

4.3 Microprocessor Operations

The diagram below shows the basic flowchart of the sequence of operations that take place in amicroprocessor.



Notes

Source: http://www.eee.metu.edu.tr/~cb/e447/Chapter%201%20-%20v2.0.pdf

The flow starts by acquiring the operation code (Op code) and decoding it. In case there is anyoperand, the address of the operand is fetched and the instruction is executed.

Source: http://shannew.files.wordpress.com/2011/04/8085-architecture.jpg

� Fetch Cycle (Phase):

� The CPU puts the address of the instruction to be executed on the address bus.

� The address information comes from the program counter (PC) maintained by thecontrol unit.

Figure 4.2: Microprocessor Operation Flowchart

Figure 4.3: Microprocessor Operation



Notes� The control bus holds the information for reading the memory location and the databus holds the instruction from the memory which is stored into the instructionregister(IR)

� PC is updated to point to the next instruction.

� Execute Cycle (Phase):

� Instruction in the IR is decoded

� The required data transfer and the required logical and arithmetic operation areperformed

� The result is written back either to one of the registers or memory or I/O device

� Common Operations Performed in ALU are:

� addition, subtraction,

� logical AND, OR, XOR, NOT

� Increment, decrement, shift, clear, etc.

Self Assessment

Fill in the blanks:

9. The …………………… holds the information for reading the memory location.

10. …………………… holds the instruction from the memory which is stored into theinstruction register.

11. The CPU flow starts by acquiring the …………………… and decoding it.

4.4 Microprocessor Memory

Memory is a vital aspect of microcontroller design, and a good understanding of memory isnecessary to discuss and processor system. Memory suffers from the clash that it can be eitherlarge or it can be fast. As memory becomes larger, it becomes less fast, and vice-versa. Becauseof this trade-off, computer systems typically have a hierarchy of memory types, where faster(and smaller) memories are closer to the processor, and slower (but larger) memories arefurther from the processor.

4.4.1 Hard Disk Drives

Hard Disk Drives (HDD) are occasionally known as secondary memory or non-volatile memory.HDD typically stores data magnetically (although some newer models use flash), and data ismaintained even when the computer is turned off or removed from power. HDD is severalorders of magnitude slower than all other memory devices, and a computer system will bemore efficient when the number of interactions with the HDD is minimized.

Because most HDDs are mechanical and have moving parts, they tend to wear out and fail aftertime.

4.4.2 RAM

Random Access Memory (RAM), also known as main memory, is a volatile storage that holdsdata for the processor. Unlike HDD storage, RAM typically only has a capacity of a few megabytesto a few gigabytes. There are two primary forms of RAM, and many variants on these.



Notes 4.4.3 SRAM

Static RAM (SRAM) is a type of memory storage that uses 6 transistors to store data. Thesetransistors store data so long as power is supplied to the RAM and do not need to be refreshed.

Source: en.wikibooks.org/wiki/Microprocessor_Design/Memory

SRAM is typically used in processor caches because of its faster speed, but not in main memorybecause it takes up more space.

4.4.4 DRAM

Dynamic RAM (DRAM) is a type of RAM that contains a single transistor and a capacitor. DRAMis smaller than SRAM, and therefore can store more data in a smaller area. Because of the chargeand discharge times of the capacitor, however, DRAM tends to be slower than SRAM. Manymodern types of Main Memory are based on DRAM design because of the high memory densities.Because DRAM is simpler than SRAM, it is typically cheaper to produce.

Notes A popular type of RAM, SDRAM, is a variant of DRAM and is not related to SRAM.

As digital circuits continue to grow smaller and faster as per Moore’s Law, the speed of DRAMis not increasing as rapidly. This means that as time goes on, the speed difference between theprocessor and the RAM units (so long as the RAM is based on DRAM or variants) will continueto increase, and communications between the two units becomes more inefficient.

4.4.5 Other RAM

There are two more kinds of RAM that we discuss below.

Cache

Cache is memory that is smaller and faster than main memory and resides closer to the processor.RAM runs on the system bus clock, but Cache typically runs on the processor speed which can be10 times faster or more. Cache is frequently divided into multiple levels: L1, L2, and L3, with L1

Figure 4.4: A Single Bit of Storage in SRAM, showing 6 Transistors



Notesbeing the smallest and fastest and L3 is the largest and slowest. A computer system may havebetween several kilobytes to a few megabytes of available cache.

Registers

Registers are the smallest and fastest memory storage elements. A modern processor may haveanywhere from 4 to 256 registers.

�Case Study Small Cabbage Processor

This small business case study prepares, ferments, and packages sauerkraut. Theirbusiest time is August-November, when they employ seasonal workers (manywho do not speak English). The process starts with the cleaning, coring, and

shredding of raw cabbage. The outer leaves are peeled off by hand as the cabbage passeson a conveyor. The equipment in this room is noisy when running; employees wearearplugs and gloves. The fermentation processes occurs in large, two-storey tanks. Workersenter the tanks to load the sauerkraut into a vacuum hose, which carries it to the packaginglines. They wear harnesses hooked to overhead safety lines while performing this work.A confined-space entry permit program is followed. All employees are required to wearsafety glasses, earplugs, bump caps, and hairnets. On the packaging floor, there are linesthat run metal and glass containers They are rinsed, filled, pasteurized, packed into boxes,palleted, and shrink-wrapped for shipment. In another room, employees pack baggedsauerkraut into boxes and lift them onto a conveyor line.

Grant Work

After an initial gap analysis and interview several issues arose, the business had recentlybroke away from being part of a major corporation, leaving the business with limitedstaffing resources, causing some problems with keeping paperwork and procedures up todate.

Aside from that problem the business had a decent health and safety program left overfrom the parent company, the person left in charge of the safety and health program wasalso the director of human resources; they were beginning to bring in other people to helpwith running the safety and health programs. The business conducts scheduled safetymeetings and has a good system for addressing and investigating any accidents. Thereappears to be good communication of safety issues to employees.

The business had recently received an OSHA inspection, which cited several guardingissues around the facility, by the time the RIT assistants scheduled a visit majority of thecited issues were corrected. This showed that the business was interested in improvingupon its safety and health. OSHA did not cite several other issues that the RIT assistant feltneeded addressing.

The first of the issues involved injuries, the most common injuries are lifting andergonomic related. The worst of the ergonomic issues was in the palleting area, theemployees had to lift cases of jars from the conveyor line and in most cases had to spin 180degrees and lower the cases to a pallet that is located on the floor. The cases weighedbetween 15 and 50 lbs. The RIT assistants ran the NIOSH lifting equation on a worst andbest case scenario to help determine and design the best lift system possible for theiroperation. For the worst case scenario, which was present in the facility, the Recommended

Contd...



Notes Weight Limit (RWL) was only 2.68 pounds, for the best case which was not found the RWLto be 113.06 pounds. From an attempt to design for best case was begun, the RIT assistantwith the HR director and Operations supervisor, the owners of the facility would onlyaccept a very low cost solution which prevented the purchases of lift tables, this case waslater referred to the RIT Centre for Integrated Manufacturing studies which providesergonomic services under a NYS Hazard Abatement grant for more expertise. The businesshas realized this to be a problem before participating in the Harwood grant and has sentemployees to undergo ergonomic training by an outside consultant.

Much of the facility had a noise level that was over 85dBs. The cutting and coring roomwhich was not operating at the times of visits was described to be of deafening soundlevels, in this room there is much mechanical motor noise and noise from metal cuttingblades hitting metal tables during the coring process. Discussion about sound dampeningand guarding techniques was held. Hearing protection is required around much of thefacility but there was no formal audiometric testing at the time. The facility has contractedwith an outside consultant to conduct baseline hearing assessment and annual test. Sincehalf of their staff is seasonal that will provide some problems.

Questions:




Source: https://www.rit.edu/~w-outrea/training/Cases/CaseStudy6.pdf

Self Assessment


12. As memory becomes more large, it becomes more fast.

13. Faster and smaller memories are closer to the processor,

14. Hard Disk Drives (HDD) are volatile memory.

15. Static RAM is a type of memory storage that uses 6 transistors to store data.

4.5 Summary

� The first microprocessor to make it into a home computer was the Intel 8080.

� The maximum clock speed is a function of the manufacturing process and delays withinthe chip.

� A microprocessor executes a collection of machine instructions that tell the processorwhat to do.

� Using its ALU (Arithmetic/Logic Unit), a microprocessor can perform mathematicaloperations.

� ROM stands for read-only memory. A ROM chip is programmed with a permanent collectionof pre-set bytes.

� RAM stands for random-access memory. RAM contains bytes of information, and themicroprocessor can read or write to those bytes depending on whether the RD or WR lineis signalled.



Notes� As memory becomes larger, it becomes less fast.

� The faster (and smaller) memories are closer to the processor.

� Hard Disk Drives (HDD) are occasionally known as secondary memory or non-volatilememory. HDD typically stores data magnetically.

� Static RAM (SRAM) is a type of memory storage that uses 6 transistors to store data.

� Dynamic RAM (DRAM) is a type of RAM that contains a single transistor and a capacitor.

4.6 Keywords

Address Bus: It sends an address to memory.

Clock Speed: It is the maximum rate that the chip can be clocked at.

Data Bus: It sends data to memory or receives data from memory.

Data Width: It is the width of the ALU.

Dynamic RAM: It is a type of RAM that contains a single transistor and a capacitor.

Microns: It is the width of the smallest wire on the chip.

MIPS: It is a rough measure of the performance of a CPU.

Static RAM: It is a type of memory storage that uses 6 transistors to store data.


1. Discuss the history of microprocessors.

2. Explain the architecture of microprocessors with suitable diagram.

3. What is a microprocessor?

4. Why do we need an ALU?

5. What are the three basic functions of a microprocessor?

6. Differentiate between data bus and address bus.

7. What is a Random Access Memory?

8. Explain the basic difference between RAM and ROM.

9. Write a note on microprocessor operations.

10. What are the various types of memory used in microprocessors?


1. 8080 2. Microns

3. Clock Speed 4. Data Width

5. True 6. False

7. False 8. False

9. Control Bus 10. Data Bus

11. Opcode 12. False



Notes 13. True 14. False

15. True


Books Udaya Kumar K. and Umashankar B.S., The 8085 Microprocessor: Architecture,Programming and Interfacing. Pearson Education India.

Jon Stokes, Inside the Machine: An Illustrated Introduction to Microprocessors andComputer Architecture.

N.K. Srinath, 8085 Microprocessor: Programming and Interfacing.


Online links http://www.ece.ncsu.edu/research/cas/ma

h t t p : / / w w w . e h o w . c o m / a b o u t _ 6 7 5 4 8 3 4 _ d i f f e r e n t - o p e r a t i o n s -microprocessor.html

http://www.everythingcomputers.com/PCS/sample%20chapter.pdf

http://www.ybet.be/en-hardware-1-03/operation-microprocessor.htm


Unit 5: Microcomputer System

NotesUnit 5: Microcomputer System

CONTENTS

Objectives

Introduction

5.1 Microcomputer System

5.1.1 Microprocessor or Central Processing Unit (CPU)

5.1.2 Memory

5.1.3 Input/Output

5.2 Specification of a Simple Microcomputer System

5.2.1 Memory Subsystem

5.2.2 Input/Output (I/O) Subsystem

5.2.3 Microprocessor or CPU

5.3 Examples of Microcomputer

5.4 Summary

5.5 Keywords



Objectives


� Understand Microcomputer system concepts

� Discuss specification of a simple microcomputer system

� Explain I/O subsystem of microcomputer

� Learn about examples of microcomputer

Introduction

A microcomputer is a small, relatively inexpensive computer with a microprocessor as itsCentral Processing Unit (CPU). It includes a microprocessor, memory, and input/output (I/O)facilities. In this unit, you will learn about basic concepts of microcomputer system. As the unitprogress, you will learn about specification of a simple microcomputer system. Later on in theunit, I/O subsystem and examples of microcomputer system will be discussed.

5.1 Microcomputer System

All types of computer system regardless of their size, type and use, consist of at least thefollowing devices:

� Microprocessor or Central Processing Unit (CPU)



Notes � Storage device (Memory)

� Input/Output devices (I/O)

� Instructions (or programs)

When these devices are connected to work together as a system, it is called a microcomputersystem.

A microcomputer is a small, somewhat inexpensive computer with a microprocessor as itscentral processing unit (CPU). Microcomputers became well known in the 1970s and 80s withthe invention of increasingly powerful microprocessors. The predecessors to these computers,mainframes and minicomputers, were comparatively much bigger and more costly.

The CPU, memory and I/O are called hardware since they are physical devices, whereas theinstructions or programs are called software.

5.1.1 Microprocessor or Central Processing Unit (CPU)

A microprocessor is a multipurpose, programmable logic device that reads binary instructionsfrom a storage device called memory. It then accepts binary data as input and processes dataaccording to those instructions, and provides results as output. A multipurpose device means itcan be used to perform various computing tasks or functions, as well as simple tasks. Aprogrammable device means that it can be instructed to perform given tasks within its capability.

Microprocessor is also called Central Processing Unit (CPU) since it is the functional central unitof the computer system.

The first microprocessor was Intel 4004 (early 1970’s) used in calculators. It was designed by IntelCorporation and become known as the 4-bit microprocessor. It was quickly replaced by the 8-bitmicroprocessor (Intel 8008), which in turn superseded by the Intel 8080. In the mid 1970’s, theIntel 8080 was widely used in control applications, and small computers also were designedusing the 8080 as the CPU.

5.1.2 Memory

Memory is the term used for the various storage devices in which one can store the programsand data for the microprocessor. These storage devices are made of semiconductor devices, andalso known as Primary Storage Devices. The semiconductor memory is of 2 types that is ReadOnly Memory (ROM) and Read Write Memory (RWM). RWM is popularly known as RandomAccess Memory (RAM):

Read Only Memory (ROM)

Programs and data stored in ROMs can only be read by the CPU. Special equipment is used towrite programs and data into the ROMs and is called EPROM Programmer.

Read Write Memory (RWM)

It is used to store user programs and data, and can be altered at any time, i.e. temporary storage.The information stored in RAM or RWM can be easily read and altered by the CPU.

Example: An example of a RWM chip is the CMOS 6116 (2K X 8).



Notes5.1.3 Input/Output

The input/output unit allows the microprocessor to communicate with the outside world, eitherto receive or to send data. Most of the time, the input/output unit will also act as an interface forthe microprocessor, that is to convert the data into a suitable format for the microprocessor.Data can be in the form of parallel (8 bit) or serial format (single line).

Input devices are devices that input data or send data to the computer.

Example: Input devices are keyboard, punched card readers, sensors, switches, etc.

Output devices are devices that output data or perform various operations under the control ofthe CPU.

Example: Output devices are LEDs, 7-segment display unit, speaker, CRT, printer, digitalspeedometer, fuel injectors, etc.

Did u know? The Commodore 64 was one of the most popular microcomputers of its era,and is the best-selling model of home computer of all time.

Self Assessment

Fill in the blanks:

1. A …………………… is a small, somewhat inexpensive computer with a microprocessor asits Central Processing Unit (CPU).

2. A …………………… device means that it can be instructed to perform given tasks withinits capability.

3. The first microprocessor was …………………… used in calculators.

4. Programs and data stored in …………………… can only be read by the CPU.

5. The …………………… unit allows the microprocessor to communicate with the outsideworld, either to receive or to send data.

5.2 Specification of a Simple Microcomputer System

Figure 5.1 shows the architecture of a simple microprocessor system.

Source: http://www.cs.ucla.edu/Logic_Design/SLPDF/ch15.pdf

Figure 5.1: Specification of a Simple Microcomputer System



Notes Below code shows how the structure can be represented in µVHDL.

µvhdl STRUCTURAL DESCRIPTION

LIBRARY ieee;USE ieee.std_logic_1164.all;

PACKAGE comp_pkg ISSUBTYPE WordT IS STD_LOGIC_VECTOR(31 DOWNTO 0);SUBTYPE MAddrT IS STD_LOGIC_VECTOR(23 DOWNTO 0);SUBTYPE IOAddrT IS STD_LOGIC_VECTOR(10 DOWNTO 0);SUBTYPE ByteT IS STD_LOGIC_VECTOR(7 DOWNTO 0);TYPE StatusT IS (undef, p_reset, fetch, execute, memop, ioop);FUNCTION get_carry(RA_Data,RB_Data,Imm,Opcode: STD_LOGIC_VECTOR)RETURN STD_LOGIC;FUNCTION get_ovf (RA_Data,RB_Data,Imm,Opcode: STD_LOGIC_VECTOR)RETURN STD_LOGIC;FUNCTION get_cc (RA_Data,RB_Data,Opcode: STD_LOGIC_VECTOR)RETURN STD_LOGIC_VECTOR;

END comp_pkg;

PACKAGE BODY comp_pkg ISFUNCTION get_carry(RA_Data,RB_Data,Imm,Opcode: STD_LOGIC_VECTOR)RETURN STD_LOGICIS VARIABLE cy: STD_LOGIC:= ‘0’;BEGIN-- description of carry generation included hereRETURN(cy);END get_carry;FUNCTION get_ovf (RA_Data,RB_Data,Imm,Opcode: STD_LOGIC_VECTOR)RETURN STD_LOGICIS VARIABLE ovf: STD_LOGIC:= ‘0’;BEGIN-- description of overflow generation included hereRETURN(ovf);END get_ovf;FUNCTION get_cc (RA_Data,RB_Data,Opcode: STD_LOGIC_VECTOR)RETURN STD_LOGIC_VECTORIS VARIABLE cc: STD_LOGIC_VECTOR(3 DOWNTO 0):= “0000”;BEGIN-- description of cc generation included hereRETURN(cc);END get_cc;

END comp_pkg;

LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE WORK.ALL, WORK.comp_pkg.ALL;

ENTITY Computer ISPORT (Reset, Clk: IN STD_LOGIC);

END Computer;

ARCHITECTURE structural OF Computer ISSIGNAL MemAddr: MAddrT; – memory address bus



NotesSIGNAL MemLength, MemRd: STD_LOGIC; – memory control signalsSIGNAL MemWr, MemEnable: STD_LOGIC;SIGNAL MemRdy: STD_LOGIC; – memory status signalSIGNAL MemData: WordT; – memory data busSIGNAL IOAddr: IOAddrT; – I/O address busSIGNAL IOLength, IORd: STD_LOGIC; – I/O control signalsSIGNAL IOWr, IOEnable: STD_LOGIC;SIGNAL IORdy: STD_LOGIC; – I/O status signalSIGNAL IOData: WordT; – I/O data busSIGNAL Status: StatusT;

BEGINU1: ENTITY MemoryPORT MAP (MemAddr, MemLength, MemRd, MemWr, MemEnable,MemRdy, MemData);U2: ENTITY IOPORT MAP (IOAddr, IOLength, IORd, IOWr, IOEnable,IORdy, IOData);U3: ENTITY ProcessorPORT MAP (MemAddr, MemData, MemLength, MemRd, MemWr,MemEnable, MemRdy,IOAddr, IOData, IOLength, IORd, IOWr,IOEnable, IORdy,Status, Reset, Clk);

END structural;

Now, let us study the components of the system one by one.

5.2.1 Memory Subsystem

Figure 5.2 shows memory subsystem in a microprocessor. In this, 5.2 (a) shows external signals,5.2 (b) shows internal organization and 5.2 (c) shows timing diagram.

Below code shows entity declaration for memory subsystem in µVHDL:

LIBRARY ieee;USE ieee.std_logic_1164.all;USE WORK.comp_pkg.ALL;ENTITY Memory IS

PORT (Addr: IN MAddrT; – memory address busLength: IN STD_LOGIC; – byte/word operandRd, Wr: IN STD_LOGIC; – access control signalsEnable: IN STD_LOGIC; – enable signalRdy: OUT STD_LOGIC; – access completion signalData: INOUT WordT); – memory data bus

END Memory;

!Caution Most microcomputers emulate various terminals. For example, the KayPro IIemulates the Lear Ziegler ADM-3A and the Xerox 832-11 the Televideo 950. So, beforedismissing a particular microcomputer because it’s not listed in the program manual,check to see what terminal it emulates.



Notes


5.2.2 Input/Output (I/O) Subsystem


Below code shows I/O entity declaration for microprocessor:

µVHDL I/O entity declaration

LIBRARY ieee;USE ieee.std_logic_1164.all;USE WORK.comp_pkg.ALL;ENTITY IO IS

PORT (Addr: IN IOAddrT; – I/O address bus

Figure 5.2: Memory Subsystem – (a) External Signals, (b) InternalOrganization, (c) Timing Diagram

Figure 5.3: Input/Output Subsystem



NotesLength: IN STD_LOGIC; – byte/word controlRd, Wr: IN STD_LOGIC; – I/O access controlEnable: IN STD_LOGIC; – I/O enable controlRdy: OUT STD_LOGIC; – I/O completion signalData: INOUT WordT); – I/O data bus

END IO;

5.2.3 Microprocessor or CPU

The CPU is the functional centre of the microcomputer system. Its internal construction can bebroadly divided into three parts:

(a) Control Section: The control section/unit is the part of the microcomputer that controls itsbasic operations. It is made up of the control signal generating circuitry (clock) and thecommand (instruction) decoder. The control section fetches pre-programmed instructionsfrom memory as needed and temporarily stores them in the command register (alsoknown as Instruction Register IR). These instructions are then decoded by the operationdecoder (decode cycle), which sends control signals to the relevant parts of themicrocomputer system which make them carry out the required operation. The timingwith which these control signals are generated is determined by the clock.

The major types of operations carried by the control signals are:

� sending of data from one part of the microcomputer to another

� inputting and outputting of data to/from the microcomputer

� Arithmetic and Logic calculations.

� Jumping to another instruction during execution of a program.

(b) Arithmetic and Logic Unit (ALU): This part does the actual processing of data. It consists ofarithmetic operations (Addition, Subtraction, Incrementing, Decrementing, etc.) and logicaloperations (AND, OR, NOT, XOR, etc.).

(c) Registers: The register part consists completely of circuit used to temporarily store data orprogram codes until they are sent to the ALU or to the control unit or to memory. Typicallythere are two types of registers:

� General Purpose Registers: These registers are used to store data temporarily, either 8-bit data or 16-bit data according to their size. They are named as A, B, C, etc. They canalso be used in pairs for a 16-bit data. For all 8 bit operations, register A is used as theAccumulator, where the result after an ALU operation is stored. For 16 bit operations,register pair HL is used to store the result.

� Special Purpose Registers: These registers are normally used to keep the address orstatus for the use of human or CPU. Example: Stack counter, program counter etc.

The three components of the microcomputer system are connected by three buses, also knownas system bus.

Self Assessment

Fill in the blanks:

6. Most microcomputers …………………… various terminals.

7. The control section/unit is the part of the …………………… that controls its basicoperations.



Notes 8. The control section fetches pre-programmed instructions from …………………… as neededand temporarily stores them in the command register.

9. The timing with which these control signals are generated is determined by the…………………….

10. …………………… Registers are used to store data temporarily, either 8-bit data or 16-bitdata according to their size.

11. …………………… Registers are normally used to keep the address or status for the use ofhuman or CPU.

5.3 Examples of Microcomputer

Microcomputers, personal computers (PCs) are little, lightweight, and portable systems. Someof them are mightier than some of the older, larger mainframes and minicomputers.Microcomputers are unique in that the CPU is placed on a single integrated chip (IC) and thewhole computer system is contained on a handful of printed circuit boards established on a littlecompact frame or cabinet. In some cases an entire microcomputer is located on a single chip.Generally micros are utilised for word processing, database administration, spreadsheets,graphics, desktop publishing, and other general office submissions. Currently, micros and PCsare being utilised for tactical support systems, such as Naval Information Processing Systems(NIPS) and Joint Operational Tactical System (JOTS). Micros and PCs can also be used as a breakscheme for shore-based operational instructions, such as ASWOC.

Figure 5.4 shows a collection of early computers.

Source: http://upload.wikimedia.org/wikipedia/commons/thumb/8/8a/Early_Personal_Computers.jpg/529px-Early_Personal_Computers.jpg

Figure 5.4: A collection of early microcomputers, including a Processor TechnologySOL-20 (top shelf, right), an MITS Altair 8800 (second shelf, left),

a TV Typewriter (third shelf, centre), and an Apple I in the case at far right



NotesThe operational programs for PCs used for a tactical support system are supported externally bytechnical groups. Programs that are used for phrase processing, graphics, etc. are abundant andcan be got through citizen vendors and software support teams such as Commander NavalComputer and Telecommunications order (COMNAVCOMTELCOM).

Modern desktop computers, video game consoles, laptops, tablet PCs, and many types ofhandheld devices, including mobile phones, pocket calculators, and industrial embedded systems,may all be considered examples of microcomputers.

Self Assessment

Fill in the blanks:

12. Microcomputers are unique in that the CPU is placed on a …………………… integratedchip (IC).

13. Micros and PCs can also be used as a break scheme for shore-based operational instructions,such as …………………….

14. The operational programs for PCs used for a tactical support system are supportedexternally by …………………… groups.

15. …………………… that are used for phrase processing, graphics, etc. are abundant and canbe got through citizen vendors and software support teams such as Commander NavalComputer and Telecommunications order.

�Case Study History of Microcomputer

The term “microcomputer” came into popular use after the introduction of theminicomputer, although Isaac Asimov used the term microcomputer in his shortstory “The Dying Night” as early as 1956 (published in The Magazine of Fantasy and

Science Fiction in July that year). Most notably, the microcomputer replaced the manyseparate components that made up the minicomputer’s CPU with a single integratedmicroprocessor chip.

The earliest models often sold as kits to be assembled by the user, and came with as littleas 256 bytes of RAM, and no input/output devices other than indicator lights and switches.However, as microprocessor design advanced rapidly and semiconductor memory becameless expensive from the early-to-mid-1970s onwards, microcomputers in turn grew fasterand cheaper. This resulted in an explosion in their popularity during the late 1970s andearly 1980s.

The increasing availability and power of desktop computers for personal use attracted theattention of more software developers. As time went on and the industry matured, themarket for personal (micro) computers standardized around IBM PC compatibles runningMS-DOS (and later Windows).

Modern desktop computers, video game consoles, laptop computers, tablet PCs, and manytypes of hand-held devices, including mobile phones and pocket calculators, as well asindustrial embedded systems, may all be considered examples of microcomputers accordingto the definition given above.

Colloquial use of the Term

Everyday use of the expression “microcomputer” (and in particular the “micro” abbreviation)has declined significantly from the mid-1980s onwards, and is no longer commonplace.

Contd...



Notes It is most commonly associated with the first wave of all-in-one 8-bit home computers andsmall business microcomputers (such as the Apple II, Commodore 64, BBC Micro, and TRS80). Although—or perhaps because—an increasingly diverse range of modernmicroprocessor-based devices fit the definition of “microcomputer,” they are no longerreferred to as such in everyday speech.

In common usage, “microcomputer” has been largely supplanted by the description“personal computer” or “PC,” which describes that it has been designed to be used by oneperson at a time. IBM first promoted the term “personal computer” to differentiatethemselves from other microcomputers, often called “home computers” and also IBM’s ownmainframes and minicomputers. Unfortunately for IBM, the microcomputer itself waswidely imitated, as well as the term. The component parts were commonly available tomanufacturers and the BIOS were reverse engineered through clean room design techniques.IBM PC compatible “clones” became commonplace, and the terms “Personal Computer,”and especially “PC”, stuck with the general public.

Questions:

1. Describe briefly about home computers.

2. Differentiate between minicomputer and microcomputer.

Source: http://en.wikipedia.org/wiki/Microcomputer

5.4 Summary

� A microcomputer is a small, somewhat inexpensive computer with a microprocessor asits central processing unit (CPU).

� The CPU, memory and I/O are called hardware since they are physical devices, whereasthe instructions or programs are called software.

� A microprocessor is a multipurpose, programmable logic device that reads binaryinstructions from a storage device called memory.

� Microprocessor is also called Central Processing Unit (CPU) since it is the functionalcentral unit of the computer system.

� Memory is the term used for the various storage devices in which one can store theprograms and data for the microprocessor.

� The semiconductor memory is of 2 types that is Read Only Memory (ROM) and ReadWrite Memory (RWM).

� Programs and data stored in ROMs can only be read by the CPU.

� Read Write Memory (RWM) is used to store user programs and data, and can be altered atany time.

� The input/output unit allows the microprocessor to communicate with the outside world,either to receive or to send data.

� The control section/unit is the part of the microcomputer that controls its basic operations.It is made up of the control signal generating circuitry (clock) and the command (instruction)decoder.

� Arithmetic and Logic Unit (ALU) does the actual processing of data. It consists of arithmeticoperations (Addition, Subtraction, Incrementing, Decrementing, etc.) and logical operations(AND, OR, NOT, XOR, etc.).



Notes� The register part consists completely of circuit used to temporarily store data or programcodes until they are sent to the ALU or to the control unit or to memory.

� General Purpose Registers are used to store data temporarily, either 8-bit data or 16-bitdata according to their size.

� Special Purpose Registers are normally used to keep the address or status for the use ofhuman or CPU. Example: Stack counter, program counter, etc.

� Modern desktop computers, video game consoles, laptops, tablet PCs, and many types ofhandheld devices, including mobile phones, pocket calculators, and industrial embeddedsystems, may all be considered examples of microcomputers.

5.5 Keywords

Microcomputer: It is a small, somewhat inexpensive computer with a microprocessor as itscentral processing unit (CPU).

Memory: It is the term used for the various storage devices in which one can store the programsand data for the microprocessor.

ROM: Programs and data stored in ROMs can only be read by the CPU.

ROM or RWM: It is used to store user programs and data that can be altered at any time.

General Purpose Registers: They are used to store data temporarily, either 8-bit data or 16-bitdata according to their size.

Special Purpose Registers: They are normally used to keep the address or status for the use ofhuman or CPU.


1. What is the purpose of the Instruction Register (IR)?

2. What are the differences between a general purpose with a special purpose register?

3. Write code for entity declaration for memory subsystem in µVHDL

4. Differentiate between ROM and RAM.

5. Explain the Microcomputer system memory.

6. What are the features of Arithmetic and Logic Unit?

7. Describe the architecture of microcomputer system.

8. Describe code for I/O entity declaration for microprocessor.

9. Discuss specification of a simple microcomputer system.

10. Explain I/O subsystem of microcomputer.


1. microcomputer 2. programmable

3. Intel 4004 4. ROMs

5. input/output 6. emulate



Notes 7. microcomputer 8. memory

9. clock 10. General Purpose

11. Special Purpose 12. Single

13. ASWOC 14. Technical

15. Programs


Books A.P. Godse, D.A. Godse, Microprocessor & Microcontroller.



Online links electronicstechnician.tpub.com/14091/css/14091_18.htm

http://en.wikipedia.org/wiki/Microcomputer

http://www.cs.ucla.edu/Logic_Design/SLPDF/ch15.pdf

http://www.itsavvy.in/types-computer


Unit 6: 8085 Microprocessor Architecture

NotesUnit 6: 8085 Microprocessor Architecture

CONTENTS

Objectives

Introduction

6.1 Architecture of 8085 Microprocessor

6.2 Register Organization

6.2.1 Arithmetic and Logical Unit (ALU)

6.3 Interrupt Controller

6.3.1 Communication

6.3.2 Serial Communication Controller

6.3.3 Timing and Control Unit

6.4 Instruction Decoder and Machine Cycle Encoder Unit

6.4.1 Instruction Decoder

6.4.2 Machine Cycle Encoder

6.4.3 Address/Data Buffer

6.4.4 Address Lines

6.4.5 Data Lines

6.4.6 Incrementer/Decrementer Latch

6.5 Summary

6.6 Keywords



Objectives


� Explain 8085 architecture

� Discus register organization

� Learn about Interrupt Controller

� Define timing and control unit

� Elaborate Instruction Decoder and Machine Cycle Encoder Unit

Introduction

8085 microprocessor is a digital chip which is a combination of different digital circuits whichare used to perform the operations of the microprocessor. The architecture of any circuit is adiagrammatical representation of different blocks or circuits and their interconnections of anycircuit or chip. In this unit, Microprocessor 8085 architecture will be discussed. As the unit



Notes progress, you will learn about register organization and interrupts controller. Finally, timingand control unit will be discussed followed by instruction decoder and machine cycle encoderunit.

6.1 Architecture of 8085 Microprocessor

As we know that the 8085 microprocessor is a digital chip which is a combination of differentdigital circuits which are used to perform the operations of the microprocessor. The architectureof any circuit is a diagrammatical representation of different blocks or circuits and theirinterconnections of any circuit or chip. According to this, the architecture of the 8085 is definedby the figure 6.1 and different blocks and their functions are described in detail in later sectionsof the unit.

The whole architecture of 8085 microprocessor can be divided in different parts as:

� Register Organization

� Arithmetic and Logical Unit (ALU)

� Interrupt Controller

� Serial Input/output Controller

� Timing and Control Unit

� Instruction Decoder and Machine Cycle Encoder

� Address/Data Buffer

� Incrementer Decrementer Latch

Figure 6.1: Architecture of 8085 Microprocessor



Notes

Task Compare the architecture of 8085 microprocessor with the Van-Neumenarchitecture scheme.

Self Assessment

Fill in the blanks:

1. 8085 microprocessor is a digital chip which is a combination of different digital circuitswhich are used to perform the …………………… of the microprocessor.

2. The architecture of any circuit is a diagrammatical representation of different blocks orcircuits and their …………………… of any circuit or chip.

6.2 Register Organization

These are the storing elements used for the data transfer function of the microprocessor. Theregisters are basically set of binary storage cells (Flip-Flops) with the capability of reading andwriting functions on them. They are categorized in different categories named as General Purposeregisters, Temporary registers and Special Purpose Registers.

� General Purpose Registers: These are the registers or storing cells used for the general datastorage functions, i.e. they are meant for only data storage and data transfer functions.This category contains six different registers of 8-bit length or they are combination of 8flip-flops named as B, C, D, E, H and L registers. These registers can be used as 16-bitformats for 16-bit operations in pairs also as B-C, D-E and H-L but the pairing of theregisters are restricted for any other type of pairing they are only defined for the abovepairs.

� Temporary Registers: These are the registers used to store temporary data in it. Theseregisters are also known as Operand Registers as they provide operands to the ALU; theALU can store immediate data values and results to these registers. These are also used indifferent operations including data transfer between register to register as an intermediatemedium and are not available for the user. This category contains two registers of 8-bitlength named as W and Z registers.

� Special Purpose Registers: These are the registers used to store data but have some specialfunctions associated to them with the data storage. This category contains the registersnamed as Accumulator (A), Flag Register, Stack Pointer (SP), Program Counter (PC) andInstruction Register.

(a) Stack Pointer (SP): It is a 16-bit register used for the execution of different programsin the microprocessor. As the name suggests, Stack means a collection or arrangementof data values in the memory locations and the pointer means any indicating orpointing element so the stack pointer is used to point out any stack which is to beexecuted. The pointing of any stack can be done by pointing its starting point orstarting memory location.

So the stack pointer register is used to hold or store the starting address location no.of any stack and at the time of execution it stores the address location no. of thepresently executing data value and the address location nos. in 8085 microprocessorare of 16-bit length so it has a size of 16-bit.



Notes (b) Program Counter (PC): It is also of 16-bit length and supports the execution of datavalues. In sequence to the stack pointer this register is used to keep track of theexecution as it stores the next address location no. which is to be executed after thestack pointer address location no.

(c) Instruction Register: It is an 8-bit register and is not accessible to the user. It holds theopcodes (Instruction Commands) of any instruction and sends them to the instructiondecoder block for decoding. After decoding the opcodes the microprocessor willconverts the command into 0/1 format.

(d) Accumulator and Flag Register: These are the two registers which are parts of ALU andwill be discussed in the ALU part.

Register Organization

Temporary RegistersGeneral Purpose Registers Special Purpose Registers

W

Z

B

CD

E

HL

SP (Stack Pointer)

PC (Program Counter)A (Accumulator)

Flag Register

Did u know? W and Z registers have been used for temporary storage, i.e. the data storedin them are regularly written and overwritten with the operations.

6.2.1 Arithmetic and Logical Unit (ALU)

The arithmetic and logical unit is meant for all types of arithmetical and logical operations doneby the microprocessor. For that purpose it has different parts for performing different operationsso that any general arithmetic or logical process can be done. The ALU of 8085 microprocessorcan perform 8-bit as well as 16-bit arithmetic operations including Addition and Subtractiononly. The 8085 microprocessor is not defined for Multiplication and Division functions. It canalso perform 8-bit logical functions including AND, OR, XOR, NOT, etc. functions. Differentparts of ALU are defined as:

� Accumulator (Register A)

� Arithmetic and Logical Circuits

� Flag Register (Status Register)

Accumulator (Register A)

As we know, it is a special purpose register having length of 8-bit. This register has two basicfunctions according to the ALU functions.

� It holds one of the two data values meant for any arithmetic or logical operation.

� It holds the 8-bit output or result of any arithmetic or logical operation which will bestored in the accumulator automatically after any arithmetic or logical operation and thedata value stored in it previously will be overwritten.



NotesArithmetic and Logical Circuits

It is a collection of different circuits used for different arithmetic and logical expressions. Forarithmetic operations only addition and subtraction functions are defined for that Adder andSubtractor circuits are defined and for logical operations AND, OR, NOT, XOR, etc. functions aredefined for that different gates and combinational circuits are defined in this collection.

Flag Register (Status Register)

It is a special type of register having 8-bit length. It has 8-bit and each of the bits are defined forgiving the status of different characteristics of the result of any arithmetic or logical operationstored in the accumulator so it is also known as status register. It shows different characteristicsaccording to the 1 and 0 representation at the particular bit. It has a certain bit pattern as shown:

D7 D6 D5 D4 D3 D2 D1 D0

S Z X AC X P X C

Here,

� Carry Flag Bit (D0): D0 bit is Carry Flag bit which is used to show the status of carry at theMSB (Most Significant Bit) of the result, in 8085 carry will be checked at 8th bit of the resultstored in the accumulator. The carry flag bit will show status of carry in the result with thehelp of 0 and 1 as

1 There is carry present at the 8th bit of the result.

0 There is no carry in the result.

For example, if we add two 8-bit numbers 10001110 and 11110011 then,

10001110

+ 11110011

(Carry) 1 10000001

So here the result has the carry at the 8th bit of the result and the carry flag bit will show a1 at the D0 bit of the flag register. If there will be no carry there the carry flag bit will showa zero at that bit of the flag register.

� Parity Flag Bit (D2): D2 bit is Parity Flag bit which is used to show the status of parity thatmeans number of 1’s in the result stored in accumulator. According to the number of 1’sany bit pattern’s parity is defined as Even Parity and Odd Parity, if the number of 1’s iseven number then it is said to be even parity and if the number of 1’s is odd number thenit is said to be odd parity. To show the status parity flag bit will use 0 and 1 as

0 There is odd parity of the result.

1 There is even parity of the result.

For example, if the result stored in the accumulator is 11110001 then number of 1’s in theresult is 5 and it is an odd number so the parity will be odd and if the result stored in theaccumulator is 11110000 then number of 1’s in the result is 4 and it is an even number so theparity will be even and the parity flag bit will show 0 and 1, respectively for the tworesults.

� Auxiliary Carry Flag Bit (D4): D4 bit is Auxiliary Carry Flag bit which is used to show thestatus of carry at the 4th bit or the MSB (Most Significant Bit) of the Nibble (Four bit patternis known as nibble) in the result, in 8085 auxiliary carry will be checked at 4th bit of the



Notes result stored in the accumulator. The auxiliary carry flag bit will show status of carry inthe result with the help of 0 and 1 as

1 There is carry present at the 4th bit of the result.

0 There is no carry at the 4th bit in the result.

For example, if we add two 8-bit numbers 10001110 and 11110011 then,

10001110

+ 11110011

10000001

So here the result has the carry at the 4th bit of the result and the auxiliary carry flag bit willshow a 1 at the D4 bit of the flag register. If there will be no carry there the auxiliary carryflag bit will show a zero at that bit of the flag register.

� Zero Flag Bit (D6): D6 bit is Zero Flag bit which is used to show the status of result of anyarithmetic or logical operation stored in the accumulator whether the result is completezero (0) or non-zero in 8085 zero result will be checked at 7th bit of the flag register. Thezero flag bit will show status of result with the help of 0 and 1 as

1 The result stored in accumulator is complete zero (result = 0).

0 The result stored in accumulator is non-zero (result ≠ 0).

For example, if we add subtract two 8-bit numbers 10001110 and 10001110 then,

10001110

– 10001110

00000000

So here the result is complete zero and the zero flag bit will show a 1 at the D6 bit of the flagregister. If there will be non-zero result then the zero flag bit will show a zero at that bitof the flag register.

� Sign Flag Bit (D7): D7 bit is sign Flag bit which is used to show the sign of result of anyarithmetic or logical operation stored in the accumulator whether the result is Positive orNegative, in 8085 sign of the result will be checked at 8th bit of the flag register. The signflag bit will show status of result with the help of 0 and 1 as

1 The result stored in accumulator is negative (-ve).

0 The result stored in accumulator is positive (+ve).

� Don’t Care Bits (D1, D3 and D5): D1, D3 and D5 bit is don’t care condition (X) which can haveany value of 1 or 0 at these positions. There will be no effect of 1 or 0 on the flag registercontent or value at these positions. But preferably we use either 1 or 0 for all don’t carepositions.

Self Assessment

Multiple Choice Questions:

3. General purpose registers are used for

(a) Storage only (b) Some specific function only

(c) Both of the above (d) None of the above



Notes4. Special purpose registers are used for

(a) Storage only (b) Some specific function only

(c) Both of the above (d) None of the above

5. Which is a temporary register

(a) A (b) B

(c) Z (d) D

6. Flag register is used in

(a) ALU (b) Serial communicator

(c) Interrupt controller (d) None of the above

7. Zero flag is used to show that the result has

(a) +ve result (b) –ve result

(c) Zero result (d) Result with a carry


It is a circuit which is used to control all the interrupts coming from the external devices accordingto their priority order one by one to the microprocessor. It also stops the lower priority interruptsso that the earlier interrupts can be serviced first and stopping any interrupt is known as theMasking process. So if we summarize the functions of any interrupt controller, two functions aredone by it:

� It controls different interrupts coming at the same time to the microprocessor terminalaccording to their priority and sends them one by one to the microprocessor for interruptservice process.

� It stops the lower priority interrupts till they have their priority order.

6.3.1 Communication

It is the process by which we transfer or shift data bits or bit patterns from one point to another.To communicate data bits there are two methods named (a) Parallel communication; (b) Serialcommunication.

Parallel Communication

In this type of communication the whole data bit pattern is transferred from one place to anotherat the same time or parallel.

1 1 1 0 0 0 1 0 (Point A)

1 1 1 0 0 0 1 0 (Point B)

Example: In the given example the 8-bit data bit pattern is transferred from point A tothe point B, parallel. For this purpose we need number of conductive lines equal to the numberof bits so that one line is used for communicating one bit. This type of communication is done inthe data lines for transferring data bits from one point to another.



Notes Serial Communication

In this type of communication the whole data bit pattern is transferred from one point toanother one by one or serially.

11100010 11100010

Example: In the given example the 8-bit data bit pattern is transferred from one point toanother serially. For this purpose we need a single conductive line and only one line is used totransfer all the bits of the pattern. This type of communication is done for some special purposes.

6.3.2 Serial Communication Controller

This block is used to control the serial communication between microprocessor and the externaldevices. This controlling operation is done by converting the serial in data into parallel data forthe communication by the data lines and the data to be sent serial out will be converted fromparallel data coming from data lines into serial data.

This block has two signals to send data to the external devices from the microprocessor namedSerial in Data (SID) as input pin and to receive data from the external devices to the microprocessornamed Serial out Data (SOD) as output pin.

As we know the data bits are parallel communicated inside the microprocessor and outside themicroprocessor serially. So the serial communication controller will convert the parallel datainto serial to send outside and vice versa to receive inside the microprocessor. So serialcommunication controller will convert the data bits serial to parallel for receiving and parallelto serial for sending.

6.3.3 Timing and Control Unit

This block comprised of two units timing unit and control unit which are used to generate clockpulses and clocked control signals.

Timing Unit

This unit is used to generate clock pulses with the use of DC supply of +5V. for this, it has anOscillator circuit which is defined to generate 6 MHz frequency then this sine wave is fed to thewave shape circuit which is a Schmitt Trigger circuit to convert the sine wave into correspondingsquare wave form then this 6 MHz square wave form will be fed to the frequency divider circuitwhich is a Flip-Flop circuit to divide the frequency by 2 so it is a divide by 2 circuit. After this wecan have the clock pulses of 3MHz and duty cycle of 50%.

OSC Circuit(Crystal Oscillator

Circuit)

Wave Shape Circuit (Schmitt Trigger)

÷ 2 Circuit(Flip-Flop)

DC

+5V

Sine

Wave

Square

Wave

Control Unit

This unit is used to generate clocked control signals for this purpose this block has a mixingcircuit used to mix up the clock pulses with the control signals generated by the instructiondecoder unit. The aim to mix these signals is to make different control signals having different

Figure 6.2: Timing Unit



Notescharacteristics and frequencies at the same frequency of 3 MHz which is the operating frequencyof 8085 microprocessor and the control signals will get compatible to different internal circuitsof the microprocessor.

(Clock Pulses) (Clocked Control Signals)

(Control Signals from Instruction Decoder Unit)

Control Unit (Mixing Circuit)

Self Assessment

Fill in the blanks:

8. …………………… is a circuit used to control all the serial communication done by themicroprocessor with the external devices.

9. In …………………… type of communication the whole data bit pattern is transferred fromone place to another at the same time or parallel.

10. In …………………… type of communication the whole data bit pattern is transferred fromone point to another one by one or serially.

6.4 Instruction Decoder and Machine Cycle Encoder Unit

This is a combination of two unit named as Instruction decoder and machine cycle encoderwhich are used to convert the instructions (Alphanumeric Codes) into simpler language formicroprocessor and the output of the execution, in the simpler language, into correspondinginstructions (Alphanumeric Codes), respectively.

6.4.1 Instruction Decoder

In this block the instructions or the alphanumeric codes (High Level Language) will be convertedinto machine language or language understandable to the microprocessor (Low Level Language).This whole process is done in these steps.

� First the alphanumeric codes are converted into corresponding Hexadecimal codes, as the8085 microprocessor will accept the hex codes in place of alphanumeric codes; it is donemanually by the user.

� Then the hex codes are loaded to the 8085 microprocessor and the microprocessor willconvert these hex codes into corresponding binary codes, it is done by the code convertercircuit of the microprocessor.

� As we know that the internal circuits of the microprocessors are made up of combinationsof different logic gates, as the microprocessor is a digital circuit and these gates are madeup of different logic families which use the general components to make different gates astransistors, resistors, capacitors, etc. and they will make any process with the current orvoltage levels. So the microprocessor circuit will convert the binary bit patterns into

Figure 6.3: Control Unit



Notes corresponding voltage or current parameters, with the help of DAC (Digital to AnalogConverter) circuit, to be executed on the internal circuits of the microprocessor. TheseV/I levels are known as the control signals of different instructions, now these signals arefed to the control unit and then to the corresponding circuits to be executed and we get theoutput or result in the form of V/I levels.

Instructions (Alphanumeric Codes)

(Manually)

Hexadecimal Codes

(Code Converter Circuit)

Binary Codes

DAC Circuit

V/I Levels (Control Signals)

6.4.2 Machine Cycle Encoder

The output of any instruction at the corresponding circuit will be in V/I form and this V/I formof any instruction is known as Machine Cycle. In machine cycle encoder block these machinecycles are now converted into corresponding alphanumeric codes so that they can be easilyunderstandable to the user. This process is done in these steps.

� First the result in the V/I form is converted into its binary code or bit pattern. It is donewith the help of ADC (Analog to Digital Converter) circuit.

� Then the corresponding binary bits are converted into corresponding hex codes with theuse of code converter circuit.

� This hex coded pattern will be displayed on the output devices and the user will convertthe hex codes into corresponding alphanumeric codes manually.

V/I form (Machine Cycles)

Binary Codes

ADC Circuit

Code Converter Circuit

Hexadecimal Codes

Manually

Alphanumeric Codes (Instructions)

Figure 6.4: Steps for Instruction Decoding

Figure 6.5: Steps for Machine Cycle Encoding



Notes6.4.3 Address/Data Buffer

It is an 8-bit bidirectional buffer used to drive or separate the lower order 8-bit address lines and8-bit data lines. Under some special conditions and signals like reset, HOLD, HALT, etc. thisbuffer is tri-stated.

6.4.4 Address Lines

The address lines of 8085 are of 16-bit length. These 16 bits are derived as lower 8-bit is derivedfrom the Address-Data lines and higher 8-bit from the address lines. They are used to send theaddress codes to the memory so the address codes are defined in 16-bit pattern and theoreticallyit is defined by hex codes of 4 hex characters. Different addresses are defined by differentcombinations of 16-bit and will range from all 0 bits to all 1 bits and in hex code from 0000H toFFFFH, here H denotes that the characters are of hexadecimal code.

6.4.5 Data Lines

The data lines of 8085 are of 8-bit length. These 8 bits are derived from the Address-Data lines.They are used to transfer data values from one unit to other in the microprocessor circuits. So thedata values are defined in 8-bit pattern and theoretically it is defined by hex codes of 2 hexcharacters. Different data values are defined by different combinations of 8-bit and will rangefrom all 0 bits to all 1 bits and in hex code from 00H to FFH, here H denote that the characters areof hexadecimal code.

6.4.6 Incrementer/Decrementer Latch

It is a 16-bit register used to increment or decrement the contents of program counter (PC) andstack pointer (SP) registers at the time of any execution. This process is done by comparing thecontents of SP and PC registers and increment or decrement the content of PC register so that theexecution will go on till last.

Self Assessment

Fill in the blanks:

11. The address lines of 8085 are of …………………… bit length.

12. The data lines of 8085 are of …………………… bit length.

13. …………………… is a 16-bit register used to increment or decrement the contents ofprogram counter (PC) and stack pointer (SP) registers at the time of any execution.

�Case Study Virtual 8085

Virtual 8085 is a tool which enables students to run programs written in 8085assembly language on a personal computer instead of a microprocessor kit. Virtual8085 do not actually simulate the real hardware of Intel 8085, but it interprets the

8085 assembly language programs.Contd...



Notes When we study the C language, we always have a compiler and a computer to practice ourprograms at home. In case of 8085 microprocessor and its assembly language it is totallydifferent. If we write an 8085 assembly language program, we have to test it or run it on amicroprocessor kit kept in our college labs. And for no reason one would want to purchasea costly microprocessor kit to study at home.

Input Screen

Output Screen

Contd...



NotesAlso, Virtual 8085 updates the graphical user interface (GUI) after each instruction, so thatstudents understand what each instruction performs. Virtual 8085 also provide real timehelp for the instruction which the programmer is currently typing. Another useful featureis syntax highlighting which enables better readability of program. Virtual 8085 do notneed to take the program in form of op-codes, it understands mnemonics.

Questions:

1. Describe usage of Virtual 8085 tool.

2. How can the learning process of the 8085 assembly language be made easier?

Source: http://virtual8085.codeplex.com/

6.5 Summary

� Register Organization are the storing elements used for the data transfer function of themicroprocessor. The registers are basically set of binary storage cells (Flip-Flops) with thecapability of reading and writing functions on them.

� General Purpose Registers are the registers or storing cells used for the general datastorage functions i.e. they are meant for only data storage and data transfer functions.

� Temporary Registers are the registers used to store temporary data in it. These registersare also known as Operand Registers as they provide operands to the ALU; the ALU canstore immediate data values and results to these registers.

� Special Purpose Registers are the registers used to store data but have some special functionsassociated to them with the data storage.

� Stack Pointer (SP) is a 16-bit register used for the execution of different programs in themicroprocessor.

� Program Counter (PC) is also of 16-bit length and supports the execution of data values. Insequence to the stack pointer this register is used to keep track of the execution as it storesthe next address location no. which is to be executed after the stack pointer address locationno.

� Instruction Register is an 8-bit register and is not accessible to the user.

� The arithmetic and logical unit is meant for all types of arithmetical and logical operationsdone by the microprocessor.

� Accumulator (Register A) is a special purpose register having length of 8-bit.

� Arithmetic and Logical Circuits is a collection of different circuits used for differentarithmetic and logical expressions.

� Flag Register (Status Register) is a special type of register having 8-bit length. It has 8-bitand each of the bits are defined for giving the status of different characteristics of the resultof any arithmetic or logical operation stored in the accumulator so it is also known asstatus register.

� Interrupt Controller is a circuit which is used to control all the interrupts coming from theexternal devices according to their priority order one by one to the microprocessor.

� Serial Communication Controller is a circuit used to control all the serial communicationdone by the microprocessor with the external devices.

� Communication is the process by which we transfer or shift data bits or bit patterns fromone point to another.



Notes � Timing and Control unit comprised of two units timing unit and control unit which areused to generate clock pulses and clocked control signals.

� Timing Unit is used to generate clock pulses with the use of DC supply of +5V.

� Control Unit is used to generate clocked control signals for this purpose this block has amixing circuit used to mix up the clock pulses with the control signals generated by theinstruction decoder unit.

� Instruction Decoder and Machine Cycle Encoder Unit is a combination of two unit namedas Instruction decoder and machine cycle encoder which are used to convert the instructions(Alphanumeric Codes) into simpler language for microprocessor and the output of theexecution, in the simpler language, into corresponding instructions (Alphanumeric Codes),respectively.

� Address/Data Buffer is an 8-bit bidirectional buffer used to drive or separate the lowerorder 8-bit address lines and 8-bit data lines.

6.6 Keywords

Accumulator (Register A): It is a special purpose register having length of 8-bit.

Address/Data Buffer: It is an 8-bit bidirectional buffer used to drive or separate the lower order8-bit address lines and 8-bit data lines.

General Purpose Registers: They are the registers or storing cells used for the general datastorage functions i.e. they are meant for only data storage and data transfer functions.

Interrupt Controller: A circuit which is used to control all the interrupts coming from theexternal devices according to their priority order one by one to the microprocessor.

Program Counter (PC): It is also of 16-bit length and supports the execution of data values. Insequence to the stack pointer this register is used to keep track of the execution as it stores thenext address location no. which is to be executed after the stack pointer address location no.

Register Organization: Storing elements used for the data transfer function of the microprocessor.

Special Purpose Registers: They are the registers used to store data but have some specialfunctions associated to them with the data storage.

Stack Pointer (SP): It is a 16-bit register used for the execution of different programs in themicroprocessor.

Temporary Registers: They are the registers used to store temporary data in it.


1. Give the general characteristics of a microprocessor.

2. What are the specifications associated with any microprocessor?

3. If data bits are of 32 bits and address lines are of 128 bits, deduce the characteristicsassociated with this microprocessor.

4. Define the specifications of 8085 microprocessor with true values.

5. Give the pin diagram of 8085 microprocessor chip and name all the pins.

6. Define clearly the operations associated with the S0 and S1 pins of 8085.

7. Which pins of 8085 are treated as interrupt pins? Define them with pin nos. and theiroperations.



Notes8. What are the functions associated with pins 12 to 19?

9. How the operating frequency of 8085 microprocessor is achieved, define with diagrams.

10. What is the function of pin 40 in 8085 chip?


1. operations 2. interconnections

3. (c) 4. (d)

5. (c) 6. (c)

7. (c) 8. (a)

9. parallel 10. serial

11. 16 12. 8

13. Incrementer/Decrementer Latch





Online links fac-web.spsu.edu/ecet/apreethy/2210_resources/8085.ppt

http://virtual8085.codeplex.com/

http://www.cs.ucla.edu/Logic_Design/SLPDF/ch15.pdf

www.cpu-world.com/Arch/8085.html



Notes Unit 7: Memory Interfacing

CONTENTS

Objectives

Introduction

7.1 Memory Interfacing in Microprocessor 8085

7.2 Types of Address Decoding

7.3 Single Board Microcomputer

7.3.1 SDK-8085 Microcomputer

7.4 Summary

7.5 Keywords



Objectives


� Explain memory interfacing in Microprocessor 8085

� Learn about types of Address Decoding

� Discuss about a single board Microcomputer and its working

Introduction

While executing a program, the microprocessor needs to access memory frequently to readinstruction codes and data stored in memory and the interfacing circuit enables that access. Somemory is an essential component in microprocessor system which will allow the user to storethe program and data. In this unit, you will learn about memory interfacing in Microprocessor8085. Later on, in this unit, you will learn about various types of address decoding. Finally,single board microcomputer will be discussed.

7.1 Memory Interfacing in Microprocessor 8085

Microprocessor 8085 has 16 bit address bus; hence it can access 216 no. of memory locations,which is equal to 64KB memory. For any microprocessor memory is required to store programas well as data. Since microprocessor doesn’t have on-chip memory, we need to connect itexternally. So it requires addressing mechanism. The following are the steps involved ininterfacing memory with 8085 processor.

1. First decide the size of memory requires to be interfaced. Depending on this we can sayhow many address lines are required for it.

Example: If you want to interface 4KB (212) memory it requires 12 address lines.

Remaining address lines can be used in address decoding.


Unit 7: Memory Interfacing

Notes2. Depending on the size of memory required and given address range, construct addressdecoding circuitry. This address decoding circuitry can be implemented with NAND gatesand/or decoders or using PAL (when board size is a constraint).

3. Connect data bus of memory to processor data bus.

4. Generate the control signals required for memory using IO/M’, WR’, RD’ signals of 8085processor.

Example: Interface 4KB memory to 8085 with starting address A000H.

1. 4KB memory requires 12 address lines for addressing as already mentioned. But 8085 has16 address lines. Hence four of address lines are used for address decoding.

2. Given that starting address for memory is A000H. So for 4KB memory ending addressbecomes A000H+0FFFH (4KB) = AFFFH.

Source: http://1.bp.blogspot.com/-TfQ7VrYvg6A/T42LmdAJIfI/AAAAAAAAAWg/wrn3605eCqY/s1600/MP8513.png

A0-A11 address lines are directly connected to address bus of memory chip. A12-A15 is used forgenerating chip select signal for memory chip.

Address decoding circuit using 3X8 decoder:

Source: http://2.bp.blogspot.com/-dnZzFtmM59w/T42MHRe6boI/AAAAAAAAAWo/qB4X8pY7u-w/s1600/mp8514.png

A15 line is use for enabling 74x138 decoder chip. A12, A13, A14 lines are connected to 74X138chip as inputs. When these lines are 010 output should be ‘0’. This is provided at O2 pin of 74X138chip.

Figure 7.1: Interface Entry Table for the Example

Figure 7.2: Address Decoding Circuit using 3x8 Decoder



Notes Address decoding circuit using only NAND gates:

Source: http://3.bp.blogspot.com/-gju7mPCwE_E/T42MQV4E3LI/AAAAAAAAAWw/0AWwamNelrs/s1600/mp8515.png

A15, A14, A13, A12 inputs should be 1010, for enabling the chip. So the circuit for this is as shownabove.

Self Assessment

Fill in the blanks:

1. …………………… is an essential component in microprocessor system which will allowthe user to store the program and data.

2. Microprocessor 8085 has …………………… bit address bus.

3. …………………… can access 216 no. of memory locations.

4. 4KB memory requires …………………… address lines for addressing.

7.2 Types of Address Decoding

There are two types of address decoding mechanism, based on address lines used for generatingchip select signal:

1. Absolute decoding

2. Partial decoding

Absolute Decoding

All the higher order lines of microprocessor, left after using the required signals for memoryare completely used for generating chip select signal as shown in above example. This type ofdecoding is called absolute decoding.

Partial Decoding

Only some of the address lines of microprocessor left after using the required signals for memoryare used for generating chip select signal. Because of this multiple address ranges will be formed.If total memory space is not required for the system then, this type of address decoding can be

Figure 7.3: Address Decoding Circuit using only NAND Gates



Notesused. The advantage of this technique is fewer components are required for memory interfacingbecause of this board size reduces and in turn cost reduces.

Example: Connect 512 bytes of memory to 8085

1. For interfacing 512 bytes 9 address lines are required. So A0-A8 can be used to directlyconnect to address bus of memory.

2. In the remaining A9-A15 for example only A15-A12 are used for generating chip selectsignal. A11-A9 are don’t care signals.

Source: http://1.bp.blogspot.com/-Z1X9AM4Q8rQ/T42Pn8SRckI/AAAAAAAAAW4/rE5JN4EdXJs/s1600/MP8516.png

Because of the ‘don’t care signals’ the address range can be:

0000 to 01FF

0200 to 03FF

0400 to 05FF

0600 to 07FF

0800 to 09FF

0A00 to 0BFF

0C00 to 0DFF

0E00 to 0FFF

Address Decoding Circuit

Source: http://2.bp.blogspot.com/-8g_7YbKWM5s/T42PwAY4V8I/AAAAAAAAAXA/fg99mlAwpvI/s1600/mp8517.png

Figure 7.4: Interface Entry Table for the Example

Figure 7.5: Address Decoding Circuit



Notes Self Assessment

Fill in the blanks:

5. There are …………………… types of address decoding mechanism.

6. All the higher order lines of microprocessor, left after using the required signals formemory are completely used for generating …………………… signal.

7. If total memory space is not required for the system then, …………………… addressdecoding can be used.

8. The advantage of partial decoding is fewer components are required for ……………………because of this board size reduces and in turn cost reduces.

7.3 Single Board Microcomputer

A single board microcomputer is a microcomputer built on a single board. There are no plug-inboards required, though they might be optional. Most modern PC’s are single board, if youignore the fact that some of the parts, such as the RAM, are plugged in.

7.3.1 SDK-8085 Microcomputer

The SDK-8085 (the SDK) is a single board microcomputer with an 8085 CPU. It comes with aneight bit wide data bus and sixteen bit wide address bus.

Memory Map for the SDK-8085 with NVRAM and EPROM Addition.

The memory is decoded into eight 2K byte blocks at two different places in memory. Sixteenkilobytes of memory is one quarter of the whole memory addressing space. The four ranges are:

Hex Address Hex Address Comments

0000H 3FFFH The SDK area

4000H 7FFFH Not decoded

8000H BFFFH NVRAM and EPROM area

C000H FFFFH Not decoded

A deeper look at the lowest 16K addresses yields:

Hex Address Hex Address Comments

0000H 07FFH Monitor Rom (2K)

0800H 0FFFH Expansion Rom (not used)

1000H 17FFH Not used

1800H 1FFFH Keybd/Display Control

2000H 27FFH RAM (1/4 Kbyte folded over eight times)

2800H 2FFFH “

3000H 37FFH Not used

3800H 3FFFH Not used

A deeper look at the third 16K block of memory:



NotesHex Address Hex Address Comments

8000H 87FFH NVRAM (eventually 2K, now 1/2 K 8600-87FF)


9000H 97FFH EPROM (2K 2716 type)


A000H A7FFH Not used

A800H AFFFH Not used

B000H B7FFH Not used

B800H BFFFH Not used

Each of the “Not used” 2K blocks of memory has a Chip Select pulse available. These are fromthe 8205 decoder on the main board and the 74138 (identical to the 8205) on the expansion area.

Procedure (Working)

1. You are going to look at the decoding scheme for the SDK. The decoding is done by a 74138decoder (an 8205 or 3205) on the computer. It is directly above the 8085 CPU. It is a 3 to 8decoder with three enables, one high, two low. It is wired as shown below:

A15

A14

A13

A12

A11

A10....

A0

A0

A1

A2

O1

O0

O2

O3

O4

O5

O6O7

8355 below CPUEmpty Slot below 8355

Not usedKeyboard Display

Upper 8155 RAM by Keyboard

Lower 8155 RAM by Keyboard

Not usedNot used

Pin 15

Pin 14

Pin 13

Pin 12

Pin 11

Pin 10

Pin 9

Pin 7

Source: campus.udayton.edu/~physics/rlb/tbs/Phy333docs/SDK8085Intro.docý

The A15 to A0 lines are the sixteen address lines. In hexadecimal notation, give the rangeof addresses which will activate each of the outputs O0 to O7.

2. Turn the computer on by turning on the blue power supply. The basic operation of theSDK-8085 is quite simple. The four operations we will use are: RESET, EXAMINEMEMORY, SUBSTITUTE MEMORY, and GO. Key strokes entered from the keypad willbe given by < >, and the contents of the display will be given by ().

RESET

The RESET key on the keypad will cause the computer to “start over.” The current contentsof the RAM memory are not lost, but any program execution is halted and the monitorprogram starts over. This RESET is a “hardware reset”. The message “-8085” will bedisplayed in the display just as it is when the power is turned on.

<RESET> (-8085)

Used for breaking out of a program or reinitializing the system.

Examine Memory Contents

The contents of any memory location RAM or ROM may be examined. For example, toexamine the contents of memory location 92ACH push the following keystroke sequence.

Figure 7.6: SDK 8085 Wiring



Notes <RESET> (- 80 85)

<SUBST MEM> (.)

< 9 > (0 0 0 9)

< 2 > (0 0 9 2)

< A > (0 9 2 A)

< C > (9 2 A C)

< NEXT > (9 2 A C 0 7)

After the NEXT key is pushed, the 0 and 7 in the data field of the display will be the data (inHex numbers) of the memory address 92ACH. This address is shown in the address fieldof the display.

If the NEXT button is pushed again, the address 92ACH is incremented by one and thecontents of these new memory locations shown in the data field of the display. This maybe repeated as many times as you like. You cannot go backwards to smaller numbers. Toescape, you may push either the RESET or EXEC buttons. The RESET starts the monitorover again, and the EXEC button causes an escape from the Examine Memory sequenceand waits for the next command from the keypad.

Change Memory Contents

To change the contents of a memory location the same sequence as above is used, but afterthe NEXT is pushed the next two keystrokes will appear in the data field of the display. IfNEXT is now pushed, this new data is put into the memory location just examined and theaddress and the contents of the next memory are displayed. Again, two keystrokes fromthe keyboard followed by the NEXT button will cause this data to be entered into thememory. Only pushing NEXT or EXEC will cause the new data entered from the keypadto be written into the memory. The EXEC will cause an escape from the examine memorysequence and so will the RESET. However, the RESET will not write the last data changeinto memory.

Program Execution

The following sequence will cause a program to execute starting at a memory location ofyour choice.

< GO > (.)

< Hex num 1 > (0 0 0 n1)

< Hex num 2 > (0 0 n1 n2)

< Hex num 3 > (0 n1 n2 n3)

< Hex num 4 > (n1 n2 n3 n4)

< EXEC > (E)

The computer will begin the execution of your program at the memory address n1 n2 n3n4. The “E” in the display indicates the computer is executing a program. Unless yourprogram eventually jumps to the monitor restart point, the only way out of the programexecution is the RESET button.

(a) Examine memory location 07D1 (generally written 07D1H where the H indicatedthat the number preceding it is a Hex number.)

(b) Change the contents of RAM memory location 2050H to D9H and then check to seethat the change has been made.

(c) Start program execution at location 0000H. This is what the RESET button does.



Notes3. Enter and run the following programs. Be sure to understand how each statementcontributes to the program. These programs are to introduce machine code in a step bystep fashion.

PROGRAM 1 - Load the Accumulator and Move it to a Memory Location

Addr MC Assem Comments

8600 31 LXI SP ;Setup Stack Pointer

8601 C2 C2

8602 20 20

8603 3E MVI A ;Load Accum with following Byte

8604 35 35 ;Any Number

8605 21 LXI H ;Load HL Pair with the following

8606 E4 E4 ; L = E4

8607 28 28 ; H = 28

8608 77 MOV M,A ; Moves Accum to Memory Location Pointed to byHL Reg. Contents in this Case, 28E4

8609 76 HALT ; Stops Execution

1. Load memory location 28E4 with 00 from the keyboard using the SUBST MEMORY keysequence.

2. Check it to make sure it is there.

3. Load the program using the SUBST MEMORY key sequence.

4. Run the program using the GO key sequence.

5. Check the contents of 28E4 and verify that the program did indeed write 35 to memorylocation 28E4.

PROGRAM 2 - Displays the Accumulator to the Data Field of the Display



8601 C2 C2

8602 20 20

8603 3E MVI A ;Load Accum. with following Byte

8604 42 42 ;Byte to Move into Accum

8605 CD CALL ;Call to Subroutine, the

8606 C0 C0 Address is given in the Two

8607 90 90 Bytes following the Instruction Low Byte of AddressFist

8608 76 HLT ; Where the Computer Returns from the Subroutineand Ends Execution

Load the program and verify its operation.



Notes PROGRAM 3 - A counter in the Address Field of the Display



8601 C2 C2

8602 20 20

8603 11 LXI D ; Load De Regs with following

8604 00 00 E = 00

8605 00 00 D = 00

8606 CD L1: CALL ; Subroutine for Display of De

8607 B0 B0 in the Address Field of

8608 90 90 of the Display

8609 13 INX D ; Adds One to the 16 Bit Reg made up of de Together

860A C3 JMP L1 ; Unconditional Jump to

860B 06 06 Following Location Labeled L1

860C 86 86 ; Endless Loop

Load and execute the program.

PROGRAM 3a - Slowing the Counter Down

Leave everything up to 860A alone and add the following.

860A D5 PUSH D ; Saves De on the Stack

860B 11 LXI D ; Load De again with Number for

860C FF FF Delay Loop. FFFF is the

860D FF FF Longest and 0001 Shortest

860E CD CALL ;Call to Delay Routine

860F D0 D0 Counts Down the Contents

8610 90 90 of the De Reg Pair

8611 D1 POP D ; Restores De (Your Counter) from the Stack

8612 C3 JMP L1 ; Jump Back to the Loop L1

8613 06 06 Never Ending Loop from

8614 86 86 8606 (L1) to Here

Load this addition and execute the program.

PROGRAM 4 - Fill in a Page of Memory with Zeros


8600 31 LXI SP ;Setup Stack

8601 C2 C2



Notes8602 20 20

8603 21 LXI HL ;Pick Page of Memory for

8604 00 00 Zeroing I Pick the Expansion

RAM

8605 28 28

8606 AF XRA A ;Exclusive Ors Accum with Accum Zeros

Accum in One Statement

8607 77 LP: MOV M,A ;Moves Zero to First Mem Location

8608 2C INR L ;Increments L

8609 C2 JNZ LP ;Jumps if L Did not Set the Zero Flag

860A 07 07

860B 86 86

860C CF RST1 ;Interrupts Back to Monitor

1. Look at 2800 page and see if it contains zeros before you start.

2. Load and run the program.

3. Look at 2800 again and see if it contains zeros.

PROGRAM 5 - A Quick Look at the in Instruction



8601 C2 C2

8602 20 20

8603 DB IN ;Input from Port Address of

8604 21 21 the Next Channel (21 in this Case)

8605 CD CALL ;Subroutine to Display the

8606 CO CO Accumulator

8607 90 90

8608 C3 JMP ;Unconditional Jump Back to

8609 03 03 the in Instruction which

860A 86 86 Loops Over and Over

1. Load and execute this program. Touch Port 21 on the SDK -8085 and watch the display. Theports are along the right edge of the wire wrap area of the computer. Port 21 (and 22 and23) have a header in them (little metal posts sticking up).

2. Touch other Ports and watch the display. They should not have as much influence on thestate of the display as Port 21 does.

3. Change the program to input from Port 2B, find it on the computer and verify that you arenow inputing from this Port and no longer from Port 21.



Notes PROGRAM 6 - Output Ports



8601 C2 C2

8602 20 20

8603 3E MVI A ;Load Status Control Register

8604 01 01 With 01 which will make

Port 21 An Output Port

8605 D3 OUT ;Outputs 01 to Port 20 the

8606 20 20 Command Status Register

For Ports 21, 22 and 23

Note: 22 and 23 are Still Input Ports!

8607 3E MVI A ;Load A with all Zeros in the Highest Four Bits andOnes in the Lowest Four Bits

8608 OF OF

8609 D3 OUT ;Output this Bit Pattern to

860A 21 21 PORT 21

860B 76 HLT ;Stop Execution

1. Run the program and use the logic probe to determine whether you have put the correctbit pattern out to Port 21. Look at other ports with the logic probe. Since they are inputports (the default for this computer) they are high impedance and thus are not high or low.

2. Hit the RESET button and check Port 21 again. You will find if you check with the logicprobe that it is now backing to an input port. The monitor program does this on RESET

Try this and put out two different numbers to these ports and check them with your logic probe.Map the bit order at the Port 21 by setting one bit at a time and seeing to which pin thiscorresponds.

Self Assessment

Fill in the blanks:

9. A …………………… microcomputer is a microcomputer built on a single board.

10. In single-board microcomputer there are no …………………… required, though theymight be optional.

11. Most modern PC’s are single board, if you ignore the fact that some of the parts, such as the……………………, are plugged in.

12. The …………………… is a single board microcomputer with an 8085 CPU.

13. It comes with an …………………… wide data bus and sixteen bit wide address bus.

14. Two keystrokes from the keyboard followed by the …………………… button will causethis data to be entered into the memory.

15. Pushing NEXT or …………………… will cause the new data entered from the keypad to bewritten into the memory.



Notes

�Case Study Flash Memory Wears Leveller Analyser

The integrity of Flash memory devices degrades over time primarily due to theimpact of memory erase cycles. Wear-levelling techniques are internally employedby flash devices to distribute memory usage and prolong their life span. Our client,

a PhD research team in a leading university, contracted Emutex to design and develop adevice that would enable them to stress test a variety of flash memory devices fromvarious manufacturers. The results of the tests would lead to the development of improvedwear-levelling techniques to prolong memory life span.

Emutex commissioned an electronics company in the USA to design and develop anARM9 based memory analyser device. Emutex engineered the embedded software andalso developed a Microsoft .NET based test application to enable a PC to control andcollect test results from many networked devices via TCP/IP.

About Emutex

Emutex is a software engineering company that creates high performance embeddedsoftware solutions for the communications industry. The company’s core strength is in thedesign and development of network packet processing and acceleration software for voice,video and data communication applications, e.g. TCP/IP offload engines, Linux TCP/IPfastpaths, network transport and signalling protocols, media streamers, cryptographyaccelerators, video compression accelerators and pattern match accelerators. Theengineering team specialise in Linux kernel, driver and application software development.This is complemented by Android and Apple iOS software development. Emutex’scustomers include world renowned semiconductor and electronics manufacturers.

Included in Emutex’s product portfolio is the VMX, its proprietary suite of Voice over IP(VoIP) call switching and voice processing software technology. This technology formsthe core of its range of VMX phone systems which are currently deployed in businessesand enterprises in Ireland and the UK.

Questions:

1. Explain the working of Flash Memory wear leveller Analyser.

2. Differentiate between an embedded device and a PC analyse interface.

Source: http://www.emutex.com/embedded-software-solutions/flash-memory-wear-leveling-analyser

7.4 Summary

� Microprocessor 8085 has 16 bit address bus; hence it can access 216 no. of memory locations,which is equal to 64KB memory.

� For any microprocessor memory is required to store program as well as data. Sincemicroprocessor doesn’t have on-chip memory, we need to connect it externally. So itrequires addressing mechanism.

� There are two types of address decoding mechanism, based on address lines used forgenerating chip select signal: Absolute decoding and partial decoding.

� All the higher order lines of microprocessor, left after using the required signals formemory are completely used for generating chip select signal. This type of decoding iscalled absolute decoding.



Notes � In partial decoding only some of the address lines of microprocessor left after using therequired signals for memory are used for generating chip select signal. Because of thismultiple address ranges will be formed. If total memory space is not required for thesystem then, this type of address decoding can be used.

� A single board microcomputer is a microcomputer built on a single board. Most modernPC’s are single board, if you ignore the fact that some of the parts, such as the RAM, areplugged in.

� The SDK-8085 (the SDK) is a single board microcomputer with an 8085 CPU. It comes withan eight bit wide data bus and sixteen bit wide address bus.

7.5 Keywords

Absolute Decoding: In this, all the higher order lines of microprocessor, left after using therequired signals for memory are completely used for generating chip select signal.

Partial Decoding: In this only some of the address lines of microprocessor left after using therequired signals for memory are used for generating chip select signal.

Single Board Microcomputer: A single board microcomputer is a microcomputer built on asingle board.


1. Explain the steps involved in interfacing memory with 8085 processor.

2. Show interfacing of 4KB memory to 8085. Assume starting address as A000H.

3. Differentiate between partial and absolute decoding.

4. Describe connecting of 512 bytes of memory to 8085

5. Write short note on single board microcomputer.

6. Write a program to fill in a page of memory with zeros.

7. Write a program to load the accumulator and move it to a memory location.

8. Explain the working of the SDK-8085 microcomputer.


1. Memory 2. 16

3. Microprocessor 4. 12

5. two 6. chip select

7. partial 8. memory interfacing

9. single board 10. plug-in boards

11. RAM 12. SDK-8085 (the SDK)

13. eight bit 14. NEXT

15. EXEC



Notes7.7 Further Readings




Online links http://www.emutex.com/embedded-software-solutions/flash-memory-wear-leveling-analyser

https://www.classle.net/content-page/memory-interfacing-example-8085

www.niceindia.com/qbank/xcs_234_microprocessors.pdf

http://www.teachurselfece.com/2012/04/memory-intercaing-to-8085.html



Notes Unit 8: Interfacing I/O Devices

CONTENTS

Objectives

Introduction

8.1 Types of Input/Output Devices

8.2 Interfacing

8.2.1 Steps for Interfacing a Peripheral

8.2.2 Interfacing Devices

8.3 Programmable Timer/Counter (8253/8254)

8.3.1 Function

8.3.2 Pin Configuration

8.3.3 Architecture or Block Diagram

8.3.4 Control Word

8.3.5 Functions of Control Word

8.4 Programmable Peripheral Interface (8255)

8.4.1 Function



8.4.4 Control Words

8.4.5 Modes of I/O Mode

8.5 Universal Synchronous Asynchronous Receiver and Transmitter (USART) (8251)

8.5.1 Function



8.5.4 Control Words

8.6 Programmable Interrupt Controller (8259)

8.6.1 Function



8.6.4 Control Words

8.7 Programmable Direct Memory Access (DMA) Controller (8257)

8.7.1 Function



8.7.4 Control WordsContd...


Unit 8: Interfacing I/O Devices

Notes8.8 RS 232-C (Recommended Standard-232)

8.8.1 Function


8.9 Parallel Printer Interface

8.9.1 Function


8.10 Universal Serial Bus (USB)

8.10.1 Function


8.11 Summary

8.12 Keywords



Objectives


� Define the term peripheral devices

� Discuss interfacing and its types

� Define different types of I/O devices

� Explain function, pin diagram and architecture of 8255, 8254, 8251, 8259 etc. chips

Introduction

The peripheral devices are the external devices connected to the microprocessor to enhance theperformance of the whole system. For example the 8085 microprocessor can handle one interruptat a time as it has only one interrupt request pin (INTR) so we use the 8259 (ProgrammableInterrupt Controller) chip for the interrupt controlling operation which can control 8 interruptsat a time as it has 8 interrupt request pins (IR0- IR7). In this way we can see that the peripheraldevice (external device) 8259 chip is used to enhance the interrupt handling capacity of the 8085microprocessor system.

These peripheral devices are then categorized in two parts according to their functions namedInput devices (For giving input to the microprocessor) and the Output devices (For taking theresult or output of the microprocessor). In this unit, you will learn about types of input/outputdevices for interfacing. Later on in the unit various chips like 8255, 8254, 8251 and 8259 will bediscussed.

8.1 Types of Input/Output Devices

Input/output devices (I/O devices) are classified in different categories according to the way bywhich the I/O devices exchange data with the processor. These categories are defined as:

(a) Memory Mapped I/O

(b) I/O Mapped I/O



Notes (c) Interrupt Driven I/O

(d) Direct Memory Access (DMA) I/O

(a) Memory Mapped I/O

� This scheme will treat the I/O devices as memory locations.

� Each of the I/O devices is used as 16-bit addresses.

� The control signals used are MEMR and MEMW .

� The maximum numbers of I/O devices that can be shared are 64 KB.

(b) I/O Mapped I/O

� This scheme will treat the I/O devices as I/O devices.

� Each of the I/O devices is used as 8-bit addresses.

� The control signals used are IOR and IOW .

� The instructions used for data transfer are IN and OUT.

(c) Interrupt Driven I/O

� This scheme will initiate the I/O devices first.

� The devices will first send a request signal to the processor for data transfer.

� Then the processor sends the grant signal for the data transfer.

� After getting this signal, the data transfer operation will be allowed.

(d) Direct Memory Access (DMA) I/O

� This scheme will allow the I/O devices to communicate with microprocessor andthe CPU will not participate in this operation.

� The scheme is used for transfer of a bulk of data.

� This scheme uses HOLD and HLDA control signals for different data transferoperations.

� The DMA process is classified as Burst Transfer, Cycle Steal and Transparent DMA.

Did u know? The I/O methods are different for different purposes which are defined forthe nature of devices and nature of functions.

Task Take a microprocessor kit and check different peripheral devices connected to it.

Self Assessment


1. Peripheral devices are connected for the function of ……………………

(a) Output devices (b) Input devices

(c) External devices (d) Internal devices



Notes2. DMA operation is performed by the help of ……………………

(a) MEMR signal (b) HOLD signal

(c) MEMW signal (d) IOR signal

8.2 Interfacing

It is the process by which an external device is so connected to the processor that the functions ofprocessor and the external device can be controlled by each other and both can transfer data witheach other.

In other words the two will have a proper communication between each other. The interfacingprocess can be divided in two parts named:

� Hardware Interfacing

� Software Interfacing

Hardware Interfacing

This is the process by which the external device is connected hardwired i.e. the physical connectionor wired connection between the device and the processor with the appropriate pins connectedfor the communication is the hardware type of interfacing.

Software Interfacing

This is the process by which the external device is connected on software based i.e. the connectionbetween the device and the processor will be made with the help of programming. Properprograms are loaded on both the sides so that their software will be able to make proper datatransfer.

The interfacing process is completely done by the combination of these two interfacing processes:

8.2.1 Steps for Interfacing a Peripheral

� First the device to be interfaced is connected to the microprocessor hardwired i.e. the twowill be connected with the help of connecting wires with corresponding pins of the two.

� The interfacing programs are uploaded to both the devices so that they can be interfacedat software level so that they can transfer data easily.

� The control word and the controlling signals are transferred to the device for the properand desired operations.

� The results are transferred to the to the output point.

8.2.2 Interfacing Devices

The devices used to connect with the microprocessor are known as interfacing devices. Thesedevices are used to enhance the functions of the microprocessor. For example, the 8086 canhandle only two interrupts at a time by the help of NMI and INTR pins but when theProgrammable Interrupt Controller (8259) is connected to the processor it can handle 8 interruptsat a time and in cascaded mode it can handle 64 interrupts at a time. The interfacing devicesstudied here will have these points to study any chip or device:

� Function of the chip

� Pin configuration of the chip



Notes � Architecture or Block diagram of the chip

� Control word of the chip

� Description of the control word

Self Assessment


3. Hardware interfacing is done for the connection at

(a) Hardware level (b) Software level

(c) Both (a) and (b) (d) None of the above

4. 8086 can handle only how many interrupts at a time by the help of NMI and INTR pins?

(a) Two (b) Three

(c) Five (d) One

8.3 Programmable Timer/Counter (8253/8254)

The Intel 8253 and 8254 are Programmable Interval Timers (PITs), which perform timing andcounting functions. They were primarily designed for the Intel 8080/8085-processors, but laterused in x86-systems. They (or an equivalent circuit embedded in a larger chip) are found in allIBM PC compatibles.

8.3.1 Function

This device is used to provide delay and the counting functions to the processor at a larger level.As a timer it generates the time base functions or timing waveforms of different types to be usedas a delay. As a counter it is used to give counting of the incoming pulses to the processors, forcounting there are three 16-bit counters in this chip.


It is a 24 pin IC where different pins have different operations.

� Pin 1-8 (D0-D7): These are 8-bit data lines which are bidirectional in nature and are used totransfer data bits between processor and chip.

Figure 8.1: Pin Configuration of 8254 Chip



Notes� Pin 9, 15 and 18 (CLK0, CLK1, CLK2): These are the input lines of counters which willprovide clock input to the chip for the counters.

� Pin 10, 13 and 17 (OUT0,OUT1,OUT2): These are output pins for the counters to show theoutput of any counting done by the counters.

� Pin 11, 14, and 16 (GATE0,GATE1,GATE2): These are the input pins for the counters used togive the control of counters to the external hardware to control the corresponding counter.

� Pin 12 (GND): This is a power supply pin used to give the ground terminal to the chip byhaving 0 V at this pin.

� Pin 19 and 20 (A0 and A1): These are the input selection lines used to select differentcounters with the help of different configurations of A0 and A1 as

A1 A0 Counter Selected

0 0 Counter 0

0 1 Counter 1

1 0 Counter 2

1 1 Control Word

� Pin 21 ( CS ): It is an input pin used to enable the chip by applying an active low signal atthis pin.

� Pin 22 ( RD ): It is an active low input pin used to make the chip to load the out data to thedata lines.

� Pin 23 ( WR ): It is an active low input pin used to make the chip to load the selectedcounter with the input data.

� Pin 24 (VCC ): It is the power supply pin used to give the supply to the chip by applying +5 Vto it.


The block diagram of 8254 chip is given as in the Figure 8.2.

Figure 8.2: Architecture of 8254 Chip



Notes Different blocks and their functions can be described as:

� Data Bus Buffer: It is a tri-stated, bidirectional circuit. This circuit is used to connect thechip data bus to the system data bus but there functions or data flow direction will bedecided by the read or write signals.

� Read/Write Logic Block: This block is used to provide the logical selected read or writesignals for different operations.

The RD or WR signal will be connected to the IOR and IOW signals for the I/O

mapped I/O and to the MEMR and MEMW signals in memory mapped I/O.

The A0 and A1 lines are connected to the A0 and A1 of the system address lines.

The chip select line is connected to the address decoding line of system.

� Control Word Register: It is an 8-bit register used to store the control word of the chipgiven by the system. This block is selected by the A0 = 1 and A1 =1 condition.

� Counters: There are three counters associated to the chip named 0, 1 and 2. These countersare of 16-bit length that means it can count from 0 to 215 states. These counters can beoperated separately for any operation. All the counters are of same characteristics. Theseall counters are down counter.

8.3.4 Control Word

The term control word can be defined as control means the control of the device and the word isused for bit pattern so the bit pattern used to control the functions and operations of any deviceis known as Control Word. The control word of 8254 is of 8-bit length and each of the bits isdefined for different functions. The control word can be defined by the given pattern.

D7 D6 D5 D4 D3 D2 D1 D0

SC1 SC0 RL1 RL0 M2 M1 M0 BCD

8.3.5 Functions of Control Word

� D0 bit (BCD Count): This bit is used to define the counting mode of the chip. By setting (1)this bit the chip is allowed to make BCD counts of 16-bit length ranging from 0000 to 9999in BCD. By resetting (0) this bit the chip is allowed to make binary counts of 16-bit lengthranging from 0 to 215 (32,768).

� D1, D2, and D3 Bits (Mode Selection Bits): These bits are used to select the mode of operationsfor the chip with the different configurations of these bits as

M2 M1 M0 Modes

0 0 0 Mode 0 (Interrupt on terminal)

0 0 1 Mode 1 (Programmable One shot)

x 1 0 Mode 2 (Rate Generator)

x 1 1 Mode 3 (Square Wave Generator)

1 0 0 Mode 4 (Software Triggered Strobe)

1 0 1 Mode 5 (Hardware Triggered Strobe)

Figure 8.3: Control Word of 8254 Chip



NotesMode 0 (Interrupt on Terminal)

This mode is used as counter function. This is used to make an interrupt as when the countis ended new count is to be started by loading the count to the counter, till this time nooperation is done so this condition is treated as interrupt and the mode is named asinterrupt on terminal count.

Mode 1 (Programmable One Shot)

This mode is used to generate monoshot or one shot pulse by the counter.

Mode 2 (Rate Generator)

This mode is used to make modulo counter which can be done by loading the final countto the counter and the counting will be done when the counter sets to zero (0).

Mode 3 (Square Wave Generator)

This mode is used to generate the square waveforms of defined parameters.

Mode 4 (Software Triggered Strobe)

This mode is used to generate the strobe pulse at the software level for the synchronizationpurposes.

Mode 5 (Hardware Triggered Strobe)

This mode is used to generate the strobe pulse at the hardware level for the synchronizationpurposes.

� D4 and D5 Bit (Read/Write Operations): These bits are defined for different reading andwriting operations which are defined by the different configurations of the bits as:

RW1 RW0 Operations Selected

0 0 Counter latch

0 1 Read Write LSB only

1 0 Read Write MSB only

1 1 Read Write LSB first and MSB last

These read and write operations are defined for the counters and the counter latch operationis defined as the condition when the counters are latched or stopped at the time with thegiven values to it.

� D6 and D7 Bit (Counter Selection Bits): These bits are defined for selecting the counters fordifferent operations at the software level which are defined by the different configurationsof the bits as:

SC1 SC0 Counter Selected

0 0 Counter 0

0 1 Counter 1

1 0 Counter 2

1 1 Read Back Command

As we can easily see the counter selection by different configurations but 11 conditions aredefined as the read back command in which one or all the counters are latched and theprevious readings can be fetched or read back by the counters.



Notes

Did u know? The best example for the decimal counting is the distance measuring meterof automobiles.

Task Take a 555 timer IC for the function of timer and check its different modes ofoperations.

Self Assessment

Multiple Choice Question:

5. 8254 chip is …………………… timer/counter

(a) Programmed (b) programmable

(c) Non-programmable (d) None of the above

8.4 Programmable Peripheral Interface (8255)

The Intel 8255 (or i8255) Programmable Peripheral Interface (PPI) chip is a peripheral chiporiginally developed for the Intel 8085 microprocessor, and as such is a member of a large arrayof such chips, known as the MCS-85 Family. This chip was later also used with the Intel 8086 andits descendants. It was later made (cloned) by many other manufacturers. It is made in DIP 40 andPLCC 44 pins encapsulated versions.

8.4.1 Function

This device is used to interface the external devices to the processor. It is done by the use of threeports of 8-bit each. These ports are used to connect the external devices to the processor.



� Pin 1-4 and 37-40 (PA0-PA7): These are 8-bit data lines for the port A, which are bidirectionalin nature and are used to transfer data bits between external device and chip.

� Pin 18-25 (PB0-PB7): These are 8-bit data lines for the port B, which are bidirectional innature and are used to transfer data bits between external device and chip.

� Pin 10-17 (PC0-PC7): These are 8-bit data lines for the port C, which are bidirectional innature and are used to transfer data bits between external device and chip.





Notes

� Pin 7 (GND): This is a power supply pin used to give the ground terminal to the chip byhaving 0V at this pin.

� Pin 8 and 9 (A0 and A1): These are the input selection lines used to select different portswith the help of different configurations of A0 and A1 as:

A1 A0 Port Selected

0 0 Port A

0 1 Port B

1 0 Port C

1 1 Control Register


� Pin 27-34 (D0-D7): These are 8-bit data lines of the chip which are bidirectional in natureand are used to transfer data bits between processor and chip.

� Pin 35 (RESET): This pin is used to give the reset signal to the chip.







Notes

Different blocks and their functions can be described as:



The RD or WR signal will be connected to the IOR and IOW signals for the I/Omapped I/O and to the MEMR and MEMW signals in memory mapped I/O. The A0 andA1 lines are connected to the A0 and A1 of the system address lines.

The chip select line is connected to the address decoding line of system.

� Group A and Group B Control: These are two control circuits defined as group A andgroup B control circuits used to control the group A ports which are port A and port C(upper) and group B which are port B and port C (lower). This control process is done bystoring the control words storing in them for appropriate group.

� Port A and Port B: These two ports have identical characteristics as they both have 8-bitbidirectional data lines to communicate with the external devices.

� Port C: It is also of 8-bit data lines but this port can be divided into two ports of 4-bit eachnamed as upper and lower port.

8.4.4 Control Words

The control word of 8255 is divided into two categories named BSR mode and I/O mode andeach control word is of 8-bit length and each of the bits is defined for different functions. Thecontrol words can be defined by the given patterns.

D7 D6 D5 D4 D3 D2 D1 D0

0 X X X PC2 PC1 PC0 S/R


Figure 8.6: BSR Mode Control Word of 8255 Chip



Notes

D7 D6 D5 D4 D3 D2 D1 D0

1 MA1 MA0 PA PCU MB PB PCL

Functions of Control Word

For Bit Set Reset (BSR) Mode: This mode is defined for port C only as we can change theoperation or set/reset the port C bits bit by bit. At a time only one bit can be selected and forselecting different bits we have to load control words for different bits of port C.

� D0 Bit (Set/Reset Bit): This bit is used to set or reset the selected bit of port C.

� D1, D2, and D3 Bits (Port C Bits Selection Bits): These bits are used to select the port C bitsfrom PC0-PC7 with the different configurations of these bits as:

PC2 PC1 PC0 Port C Pins Selected

0 0 0 PC0

0 0 1 PC1

0 1 0 PC2

0 1 1 PC3

1 0 0 PC4

1 0 1 PC5

1 1 0 PC6

1 1 1 PC7

� D4, D5 and D6 Bit (Don’t Care Bits): These bits are defined for don’t care condition i.e. therewill be no effect of 1 or 0 at these bits.

� D7 Bit (Constant Bit): This bit will be constantly 0 for the BSR mode.

For Input/Output (I/O) Mode: This mode is defined for port A, port B and port C all the ports.The I/O mode is defined for three modes named as Mode0, Mode1 and Mode2.

� D0 Bit (Port CL Mode Selection Bit): This bit is used to select the mode of operation of PCL

as when the bit is set it is used as input port and for reset it is used as output port.

� D1 Bit (Port B Mode Selection Bit): This bit is used to select the mode of operation of PB aswhen the bit is set it is used as input port and for reset it is used as output port.

� D2 Bit (Mode Selection Bit for Group B): This bit is used to select the modes for the groupB as this group is associated for Mode0 and Mode1. These modes can be selected as a 0 at thisbit will select Mode0 and 1 will select Mode1 for the group B.

� D3 Bit (Port CU Mode Selection Bit): This bit is used to select the mode of operation of PCU

as when the bit is set it is used as input port and for reset it is used as output port.

� D4 Bit (Port A Mode Selection Bit): This bit is used to select the mode of operation of PAas when the bit is set it is used as input port and for reset it is used as output port.

� D5 and D6 Bits (Mode Selection Bits for Group A): These bits are used to select the modesfor the group A as this group is associated for Mode0, Mode1 and Mode2. These modes canbe selected by the different configurations of these bits.

Figure 8.7: I/O Mode Control Word of 8255 Chip



Notes MA1 MA0 Mode Selected

0 0 Mode 0

0 1 Mode 1

1 x Mode 2

� D7 Bit (Constant Bit): This bit will be constantly 1 for the I/O mode.

8.4.5 Modes of I/O Mode

� Mode 0 (Simple Input/Output Mode): In this mode, port A, B and C all the ports are usedfor the input or output functions. All the ports are programmed individually for theoperations. The 4 ports are defined for the 16 different possible I/O configurations.

� Mode 1 (Strobed I/O): In this mode port A and B will be used for input and output operationsand port C is defined for the control functions.

For input mode, PA is controlled by PC3, PC4 and PC5 and PB is controlled by PC0, PC1 andPC2. The control signals generated in this mode are:

Strobe Input ( STB )

Input Buffer Full (IBF)

Interrupt Request (INTR)

Interrupt Enable (INTE)

For output mode, PA is controlled by PC3, PC6 and PC7 and PB is controlled by PC0, PC1

and PC2. The control signals generated in this mode are:

Output Buffer Full ( OBF )

Acknowledge ( ACK )


Interrupt Enable (INTE)

� Mode 2 (Strobed Bi-directional I/O): In this mode port A will be used for input and outputoperations and port B and C is defined for the control functions.

For input mode, the control signals generated in this mode are:

Strobe Input ( STB )

Input Buffer Full (IBF)


For output mode, the control signals generated in this mode are:

Output Buffer Full ( OBF )

Acknowledge ( ACK )

Did u know? The ports defined in the computer systems (CPU) are basically 8255 chip’sports.





6. 8255 chip has how many no. of 4-bit ports?

(a) 1 (b) 2

(c) 3 (d) 4

8.5 Universal Synchronous Asynchronous Receiver and Transmitter(USART) (8251)

The 8251 is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for serialdata communication. As a peripheral device of a microcomputer system, the 8251 receivesparallel data from the CPU and transmits serial data after conversion. This device also receivesserial data from the outside and transmits parallel data to the CPU after conversion.

8.5.1 Function

This device is used to make the serial communication with the external devices. As its namesuggests it is used for the transmission and reception of serial communication i.e. works asreceiver and transmitter both in synchronous and asynchronous modes. The synchronous modeis defined as the clock given to the chip and the devices will be identical or the data transfer willbe done at the same time, like voice calls. The asynchronous mode is defined as the clock givento the chip and the devices is not identical or the data transfer will be done at different time, liketext messages, e-mails, etc.


It is a 28 pin IC where different pins have different operations:

� Pin 1,2,5,6,7,8,27 and 28 (D0-D7): These are 8-bit data lines of the chip which are bidirectionalin nature and are used to transfer data bits between processor and chip.




Notes � Pin 3 (RxD): It is the input pin for the serial data and will be connected to the TxD pin ofother chip.


� Pin 9 ( TxC ): It is an input pin used to give the clock to the transmitter of the chip.



� Pin 12 (C/ D ): It is a selection pin used in two different modes for high input it will selectthe data coming from D0-D7 as control word and for low input the data will be treated asdata value to be transmitted.


� Pin 14 (RxRDY): It is the output pin used to give the status to the other chip that thereceiver is ready to receive the characters.

� Pin 15 (TxRDY): It is the output pin used to give the status to the other chip that thetransmitter is ready to send the characters.

� Pin 16 (SYNDET/BRKDET): It is a bi-functional pin used in different manners in synchronousand asynchronous modes. In synchronous mode it is used to detect the synchronous bits.In asynchronous mode it is used to detect the break bits.

� Pin 17 ( CTS ): This pin is used to give the status that the path is clear for sending serialdata.

� Pin 18 (Tx EMPTY): This pin is used to give the status that the transmitter is empty i.e. thereis no character present at the transmitter to be sent.

� Pin 19 (TxD): It is the output pin for the serial data and will be connected to the RxD pin ofother chip.

� Pin 20 (CLK): It is an input pin to give the clock to the chip.

� Pin 21 (RESET): This pin is used to give the reset signal to the chip.

� Pin 22 ( DSR ): This pin is used to give the status that the data set to be sent is ready.

� Pin 23 ( RTS ): This pin is used to give the request to the other chip for sending serial data.

� Pin 24 ( DTR ): This pin is used to give the status that the data terminal is ready for thecommunication.

� Pin 25 ( RxC ): It is an input pin used to give the clock to the receiver of the chip.






Notes




The RD or WR signal will be connected to the IOR and IOW signals for the I/Omapped I/O and to the MEMR and MEMW signals in memory mapped I/O. The C/ Dis used to select the control word or data value coming from the data lines so the read orwrite functions will be done according to the selected control word or data value. The chipselect line is connected to the address decoding line of system.

� Modem Control: This block is used to control the MODEM or the functions of the chip as ithas 4 signals associated to give the status to the other chip while communication and viceversa.

� Transmitter Control and Transmitter Buffer: These blocks are used to control the data bitsto be sent and provide path to the transmission of data.

� Receiver Control and Receiver Buffer: These blocks are used to control the receiving ofdata bits and provide path for the receiving of data.

8.5.4 Control Words

The control word of 8251 is divided into two categories named Mode control word and StatusControl Word and each control word is of 8-bit length and each of the bits is defined for differentfunctions. The control words can be defined by the given patterns:

D7 D6 D5 D4 D3 D2 D1 D0

S1 S0 EP PEN L1 L0 B1 B0


Figure 8.10: Mode Control Word of 8251 Chip



Notes

D7 D6 D5 D4 D3 D2 D1 D0

DSR SYNDET/ BRKDET

FE OE PE TxE RxRDY TxRDY


For Mode Control Word: This control word is defined for the selection of different modes ofoperations done by the 8251 chip.

� D0 and D1 bit (Baud Rate Selection Bits): These bits are defined to give different modes ofbaud rate to be used which is basically the number of data bits transmitted at a time.Different baud rate can be defined by the different configurations of these two bits as:

B1 B0 Baud Rate Selected

0 0 SYNC mode

0 1 1 x

1 0 16 x

1 1 64 x

These modes are defined as 00 is for synchronous mode function and all others are forasynchronous mode as, 01 is for 1x mode which specifies that 1 bit is transmitted/receivedin one clock pulse. 10 is for 16x mode which specifies that 1 bit is transmitted/received in16 clock pulses. 11 is for 64x mode which specifies that 1 bit is transmitted/received in 64clock pulses.

� D2 and D3 Bits (Character Length Selection Bits): These bits are used to select the length ofcharacter bits used to send the proper data at the time of communication with the differentconfigurations of these bits as:

L1 L0 Character Length Selected

0 0 5 bits

0 1 6 bits

1 0 7 bits

1 1 8 bits

� D4 and D5 Bit (Parity Enable and Even Parity): Parity enable bit is used to enable theparity bit added with the data bits, if it is 1 the parity bit will be added to the character bitsand if it is 0 then there will be no parity bit added to the characters. Even Parity bit willmake the added parity bit even if this bit is 1 and will be odd parity bit if the even paritybit is 0. These bits are checked at the time of receiving if these are in correct order than thecommunication is error free otherwise it will have error while communication.

� D6 and D7 Bits (Stop Bits Selection Bits): These bits are defined to give the number of stopbits added at the end of sending bits to differentiate the characters from one another. Thenumber of stop bits can be decided by different configurations of these bits as:

S1 S0 No. of Stop Bits Selected

0 0 Invalid

Figure 8.11: Status Control Word of 8251 Chip



Notes0 1 1 bit

1 0 1½ bit

1 1 2 bits

The 1½ bit stop bits added means the ½ bit specifies that the output remains high for ½ bittime. At the receiver end these bits are checked along with the data bits if they are notmatched the communication has an error.

For Status Control Word: This control word is defined to give the status of different operationsassociated as:

� D0 Bit (Tx RDY): This bit is used to give the status of transmitter whether it is ready or notwhich is defined by the 1 and 0 conditions at this bit position, respectively.

� D1 Bit (Rx RDY): This bit is used to give the status of receiver whether it is ready or notwhich is defined by the 1 and 0 conditions at this bit position, respectively.

� D2 Bit (Tx E): This bit is used to give the status that the transmitter is empty or not i.e. thetransmitter has sent all the data bits or it is sending data bits. These statuses are given bythe 1 and 0 conditions at the bit position.

� D3 Bit (Parity Error Bit): This bit is used to give the status of parity error whether it ispresent or not, it is checked as the receiving data is checked for the parity bits if it is notmatched with the sending status then there will be a parity error. This status is shown bya 1 at this bit position.

� D4 Bit (Overrun Error Bit): This bit is used to give the status of overrun error whether it ispresent or not, it is checked as the receiving data is checked for the number of data bits ifit is not matched with the sending status then there will be an overrun error. This status isshown by a 1 at this bit position.

� D5 Bit (Framing Error Bit): This bit is used to give the status of stop bits error whether itis present or not, it is checked as the receiving data is checked for the stop bits associatedto it if it is not matched with the sending status then there will be a framing error. Thisstatus is shown by a 1 at this bit position.

� D6 Bit (Synchronous Detection/Break Detection Bit): This bit is used to give the status ofsynchronous detection in synchronous mode and break detection in the asynchronousmode of serial communication. This is shown by a 1 at the bit position.

� D7 Bit (Data Set Ready Bit): This bit is used to give the status of data set to be sent is readyto send or not. This status is shown by a 1 at this bit position.

Task Find out the difference between the serial and parallel communication and whichthe better one is.

Self Assessment


7. 8251 (USART) chip is used for

(a) Serial communication (b) Parallel communication

(c) DMA operation (d) Peripheral interfacing



Notes 8.6 Programmable Interrupt Controller (8259)

The Intel 8259 is a Programmable Interrupt Controller (PIC) designed for the Intel 8085 and Intel8086 microprocessors. The initial part was 8259, a later A suffix version was upward compatibleand usable with the 8086 or 8088 processor. The 8259 combines multiple interrupt input sourcesinto a single interrupt output to the host microprocessor, extending the interrupt levels availablein a system beyond the one or two levels found on the processor chip. The 8259A was theinterrupt controller for the ISA bus in the original IBM PC and IBM AT.

8.6.1 Function

This device is used as Interrupt controller and has the same function that means it handles theinterrupts coming from the external devices and the interrupts are sent to the microprocessoraccording to their priority. This chip can handle 8 interrupts at a time as a single chip operation.This chip can also be used in cascaded mode where it can handle 64 interrupts at a time and itserves the interrupts in different priority modes as fixed priority and rotating priority.




� Pin 2 ( WR ): It is an active low input pin used to make the chip to load the selected counterwith the input data.


� Pin 4-11 (D0-D7): These are 8-bit data lines of the chip which are bidirectional in nature andare used to transfer data bits between processor and chip.

� Pin 12, 13 and 15 (CAS0-CAS2): These are 3-bit bi-directional cascaded lines used in thecascaded mode only. These lines are used as output lines for master mode as it gives theidentification of slave chips by different combinations of these three lines. These lines areused as input lines in the slave mode as it takes the slave identification number by theselines same as master mode.





Notes� Pin 16 ( SP / EN ): This is an active low pin having bidirectional functions according to thebuffered or non-buffered mode. In buffered mode this pin is used as EN i.e. the enablepoint for the data buffers. In non-buffered mode it is used to distinguish between masterand slave chip, as it works as SP then for master chip it will be connected to Vcc and forslave chip it will be grounded.

� Pin 17 (INT): This is an output line used to out the highest priority interrupt request to themicroprocessor coming from the external devices. This pin will be connected to the INTRpin of the microprocessor.

� Pin 18-25 (IR0-IR7): These are 8-bit interrupt lines used to input the interrupts comingfrom the peripherals. These lines have a priority order having IR0 highest priority and theIR7 the lowest one. These lines can be edge or level triggered.

� Pin 26 ( INTA ): This is an input line used to in the INTA signal coming from themicroprocessor in acknowledge to the INTR signal. It is connected to the INTA pin of themicroprocessor.

� Pin 27 (A0): This is an address line used to select the appropriate control word by itsdifferent configurations.






� Read/Write Logic Block: This block is used to provide the logical selected read or writesignals for different operations. The RD or WR signal will be connected to the IOR andIOW signals for the I/O mapped I/O and to the MEMR and MEMW signals in memorymapped I/O. The A0 is used to select the control word as it is used with the control words.The chip select line is connected to the address decoding line of system.




Notes � Cascaded Buffer and Comparator: This block is used in the cascaded mode. In the cascadedmode it is used to send or receive the slave identification number in master and slavemode, respectively. The comparator function is used to compare the identification numbercoming from the CAS lines.

� Interrupt Request Register (IRR): This block is used to store the interrupt requests (IRs)coming from the peripherals by the IR lines connected to it.

� Priority Resolver: This block is used to resolve the priorities of the coming interrupts andset the highest priority bit of the In-service register.

� In-Service Register: This block is used to store all the interrupts to be served. All the bitsof this register are set by the priority resolver block and will be reset by the EOI command.It sends the highest priority interrupt to the control logic block.

� Interrupt Mask Register (IMR): This block is used for the masking process. This maskingis the process to stop the unwanted interrupts. The masking process is done with writingthe appropriate command word by the microprocessor.

� Control Logic: This block is used to generate the INT signal to be sent to the microprocessorwhich is basically the transformed form of the highest priority IR signal. It also accepts theINTA signal coming from the microprocessor.

8.6.4 Control Words

The control word of 8259 is divided into two categories named Initialization control words(ICWs) and Operational Control Words (OCWs). There are total 7 control words associated tothe 8259 chip and ICWs are used to initialize the chip and OCWs are used to control the operationsof the chip. The initialization of the chip has some steps associated to them as:

No Yes

Load ICW1

Ready to Operate

CascadedMode?

ICWneeded?

4

Load ICW2

Load ICW3

Load ICW4

No Yes

Figure 8.14: Initialization of 8259 Chip



NotesControl Words of 8259 Chip

Initialization Control Words Operational Control Words

ICW1 OCW1

ICW2 OCW2

ICW3 OCW3

ICW4

A0 D7 D6 D5 D4 D3 D2 D1 D0

0 A7 A6 A5 1 LTIM ADI SNGL ICW4

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 A15 A14 A13 A12 A11 A10 A9 A8

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 S7 S6 S5 S4 S3 S2 S1 S0

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 0 0 ID2 ID1 ID0

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 SFNM BUF M/S AEOI µPM

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 M7 M6 M5 M4 M3 M2 M1 M0

A0 D7 D6 D5 D4 D3 D2 D1 D0

0 R SL EOI 0 0 L2 L1 L0

Figure 8.15: ICW1 of 8259 Chip


Figure 8.17: ICW3 of 8259 Chip for Master Mode

Figure 8.18: ICW3 of 8259 Chip for Slave Mode


Figure 8.20: OCW1 of 8259 Chip




Notes

A0 D7 D6 D5 D4 D3 D2 D1 D0

0 0 ESMM SMM 0 1 P RIR RIS


For ICW1:

� D0 Bit (ICW4 is Needed): This bit is used to check whether the ICW4 is needed by the chipor not. For 1 the ICW4 is needed and for 0 there is no need of ICW4.

� D1 Bit (Single Mode Selection Bit): This bit is used to tell that the chip is used in the singleor cascaded mode. 1 is for the single mode and the 0 is for cascaded mode.

� D2 Bit (Address Interval Bit): This bit is used to give the call address interval and is onlyused in the 8086 mode. For 0 it gives 8 intervals and for 1 condition 4 interval of calladdress is given.

� D3 Bit (Level Triggered Initialization Mode Selection Bits): This bit is used to select thelevel triggered or edge triggered initialization mode for the chip by the 1 and 0 condition,respectively.

� D4 Bit (Constant Bit): This bit will be constant 1 all the time.

� D5, D6 and D7 Bits (Address Lines Bits): These bits are used to give the address lines and areused in the 8086 mode only.

For ICW2:

� D0 – D7 Bits (Address Line Bits): These all 8 bits are used to give the address lines and areused in the 8086 mode only.

For ICW3: This ICW3 is defined for the cascaded mode operations so this is of two types one forMaster mode and other is for Slave mode. The cascaded mode is nothing but the chip is connectedto the microprocessor and all the IR pins are connected to 8 different 8259 chips so we can get 64IR lines by these 8 chips. The chip connected to the microprocessor is known as Master chip andthe chip connected in cascade to the master chip is known as Slave chip.

ICW3 for Master Mode:

� D0 – D7 Bits (Slave Information Bits): These bits are used to give the information that anyIR pin has a slave connected to it if there is a 1 at any bit and there is no slave present if the0 is present at the bit. The S0-S7 bits are defined for the corresponding IR 0-IR7 pins.

ICW3 for Slave Mode:

� D0 – D2 Bits (IR Identification Bits): These bits are used to select the IR pins by theirdifferent configurations as:

ID2 ID1 ID0 IR Pins Selected

0 0 0 IR0

0 0 1 IR1

0 1 0 IR2

0 1 1 IR3

1 0 0 IR4




Notes1 0 1 IR5

1 1 0 IR6

1 1 1 IR7

� D4-D7 Bits (Constant Bits): These bits will be constant 0 all the time.

For ICW4:

� D0 Bit (Microprocessor Mode Bit): This bit is used to indicate whether the chip is operatingin 8085 or 8086 mode as 1 is for 8086 and 0 is for 8085 mode of operation.

� D1 Bit (Automatic End of Interrupt Selection Bit): This bit is used to set the mode ofoperation to EOI or AEOI mode as 0 is for End of Interrupt (EOI) mode and 1 is forAutomatic End of Interrupt (AEOI) mode.

The EOI mode is defined as the process by which the highest priority interrupts are servedand after this process the chip will be stopped till it is initiated for the next interrupt tomake the interrupt service function.

The AEOI mode is defined as the automatic end of interrupt function in which all theinterrupts coming at the same time will be served one by one automatically.

� D2 and D3 Bits (Buffered Mode Selection Bits): These bits are used to give the mode ofoperation in buffered or non-buffered mode by the different configurations of these twobits as:

BUF M/S Mode of Operation

0 X Non-Buffered Mode

1 0 Buffered Mode (Slave)

1 1 Buffered Mode (Master)

� D4 Bit (Special Fully Nested Mode Selection Bits): This bit is used to select the fully nestedmode or special fully nested mode by the given bit. If the bit is 1 it will work in SFNM andfor 0 it will work in FNM. The FNM is defined as the process in which the slave chips aremasked or stopped after the interrupt request from the same is served. The SFNM isdefined as the process in which the master chip will allow the slave to give the interruptrequest every time even the interrupt request is served just before.

� D5, D6 and D7 Bits (Constant Bits): These bits will be constant 0 all the time.

For OCW1:

� D0 – D7 Bits (Masking Selection Bits): These bits are used to give the information that anyIR pin is masked or not if there is a 1 at any bit the corresponding IR pin is masked and ifthe 0 is present at the bit there is no masking or no IR is coming at that pin. The M0-M7 bitsare defined for the corresponding IR 0-IR7 pins.

For OCW2:

� D0, D1 and D2 Bits (IR Pin Selection Bit): These bits are used to select the IR pins where theoperations decided by the other bits are to be implemented. The selection of IR pins aredone by different configurations of these bits as:

L2 L1 L0 IR Pins Selected

0 0 0 IR0

0 0 1 IR1



Notes 0 1 0 IR2

0 1 1 IR3

1 0 0 IR4

1 0 1 IR5

1 1 0 IR6

1 1 1 IR7

� D3 and D4 Bits (Constant Bits): These bits will be constant 0 all the time.

� D5, D6 and D7 Bits (Specific Modes Selection Bits): These bits are used to give the mode ofoperations as:

R SL EOI Operations Selected

0 0 1 Non-specific EOI

0 1 1 Specific EOI

1 0 1 Rotated non-specific EOI

1 0 0 Rotated AEOI (Set)

0 0 0 Rotated AEOI (Clear)

1 1 1 Rotated Specific EOI

1 1 0 Set Priority

0 1 0 No Operation

The rotated priority can be defined as the priority order in which the IR pin just served orhaving the highest priority level will get the lowest priority for the next interrupt servicecycle and the other IR pins will get the same priority order above this served IR pin. Thisprocess will go on and at a level the first priority can be achieved so it is known as theRotating priority as the first priority have taken a rotation for achieving the same prioritylevel.

For OCW3:

� D0 and D1 Bits (Read Operation Selection Bit): These bits are used to select the readingoperation of IRR and ISR as:

RIR RIS Mode of Operation

0 X No operation

0 0 Read IRR

1 1 Read ISR

� D2 Bit (Polled Operation Selection Bit): This bit is used to select the polled priority bygiving 1 and will be normal priority level taken for 0.

The polled priority is the process by which we program the priority levels of the IR pinsaccording to our convenience i.e. we can give any priority to any of the IR pin.

� D3 and D4 Bits (Constant Bits): These bits will be constant 1 and 0 all the time for D3 andD4 bits, respectively.

� D5 and D6 Bits (Masking Mode Selection Bits): These bits are used to select the maskingmodes by the different configurations as:



NotesESMM SMM Mode of Operation

0 X No operation

1 0 Reset SMM

1 1 Set SMM

The Special Masking Mode is the process by which the chip will mask all the interruptsother than the interrupt which is serving at the time.

� D7 Bit (Constant Bit): This bit will be constant 0 all the time.

Self Assessment


8. Programmable interrupt controller has the chip no.

(a) 8257 (b) 8255

(c) 8259 (d) 8251

9. How many control words are associated with the 8259 chip for the controlling of operations

(a) 2 (b) 5

(c) 8 (d) 7

10. From IR0 – IR7 of 8259 chip, which pin has the highest priority of operations

(a) IR2 (b) IR4

(c) IR0 (d) IR7

8.7 Programmable Direct Memory Access (DMA) Controller (8257)

Description of 8257 chip is given as:

8.7.1 Function

This device is used to give an interface to the external devices for the DMA operations or datatransfer. It has four channels which are used to connect the four external devices for the DMAoperation to the processor.


It is a 40 pin IC where different pins have different operations:

� Pin 1 ( IOR ): This pin is used to give the Input/output read signal.

� Pin 2 ( IOW ): This pin is used to give the Input/output write signal.

� Pin 3 ( MEMR ): This pin is used to give the memory read signal.

� Pin 4 ( MEMW ): This pin is used to give the memory write signal.

� Pin 5 (MARK): It is a status pin used to give the indication of the transfer of 128 bytes ofdata in any DMA operation if the transferring data is less than 128 bytes it will not beactivated.



Notes

� Pin 6 (READY): It is a status pin used to give the indication of the chip that it is ready forany operation.

� Pin 7 (HLDA): This is the input pin used to take the hold acknowledgement signal comingfrom the processor point in response to the HOLD signal.

� Pin 8 (ADSTB): It is the output pin used to give the strobe signal to synchronize the higherand lower bits of address lines.

� Pin 9 (AEN): This is the enabling pin for the address lines.

� Pin 10 (HRQ): This is an out pin used to give the HOLD signal to the processor which is thehighest priority DRQ signals coming from the peripherals connected to the channels.


� Pin 12 (CLK): It is an input pin used to take the clock for the whole chip.

� Pin 13 (RESET): It is an input pin used to take the reset signal for the chip.

� Pin 14, 15, 24 and 26 ( DACK ): These are the out pins used to give the DMAacknowledgement signals to the peripherals in response to the DRQ signals.

� Pin 16-19 (DRQ0-DRQ3): These are the DMA request signals coming from the externaldevices.

� Pin 28 (VSS ): It is the power supply pin used to give the supply to the chip by applying +5 Vto it.

� Pin 21-23 and 26-30 (D0-D7): These are 8-bit data lines of the chip which are bidirectionalin nature and are used to transfer data bits between processor and chip.


� Pin 32-35 and 37-40 (A0-A7): These are 8-bit Address lines of the chip which areunidirectional in nature and are used to transfer address bits between processor and chip.




Notes� Pin 36 (TC): It is the output status pin used to give the status that the present DMA cycle oroperation is completed.





� Read/Write Logic Block: This block is used to provide the logical selected read or writesignals for different operations. The RD or WR signal will be connected to the IOR andIOW signals for the I/O mapped I/O and to the MEMR and MEMW signals in memorymapped I/O. The A0 and A1 lines are connected to the A0 and A1 of the system address lines.The chip select line is connected to the address decoding line of system. In slave mode itaccepts the address bits and control signals and in the master mode it will give the addressbits and control signals.

� Control Logic Block: This block is used to give the control signals, address signals andHRQ signals. It also accepts the HLDA signal and it increments the address register anddecrements the count register. It will be disabled in the slave mode of operation.

� Priority Resolver: This block is used for the priority resolution of the channels as the DRQsignals are treated as interrupts.




Notes � Channels: There are four channels associated with the DMA controller having two 16-bitregisters named address register and count register.

� Address Register: It is a 16-bit register used to hold the starting address of the memory forthe DMA operation and will be decremented after every DMA cycle to provide the nextaddress to be fetched.

� Count Register: It is also of 16-bit length used to count the DMA cycles by using its least 14bits and makes the down counting. Rest two higher bits are used to give the status of theDMA operation by its different configurations as:

D15 D14 DMA Operations

0 0 DMA verify cycle

0 1 DMA write cycle

1 0 DMA read cycle

1 1 No operation

8.7.4 Control Words

The control word of 8237 is divided into two categories named Mode set control word and Statuscontrol word and each control word is of 8-bit length and each of the bits is defined for differentfunctions. The control words can be defined by the given patterns:

D7 D6 D5 D4 D3 D2 D1 D0

AL TCS EW RP EN3 EN2 EN1 EN0

D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 UP TC3 TC2 TC1 TC0


For Mode Set Control Word:

� D0-D3 Bit (Enabling Bits) :These are the enabling bits for the channels and each of the bitsis defined for the corresponding channel. 1 at any bit is defined for the enable condition ofthat channel i.e. it is ready to take the DRQ signal from that channel.

� D4 Bit (Rotating Priority Bit): This bit is used to set the rotating priority mode for thechannels by having a 1 at the bit and by having 0 it will have the normal fixed prioritymode for the operation which is channel0 having highest and the channel 3 has the lowestpriority.

� D5 Bit (Extended Write Bit): This bit is used to set the extended write operation by 1 and by0 it makes the normal write mode.

In extended write mode, the chip will extend the write signal so that there will be time forthe next write operation to have the address fetching and after the first write operationcompleted, immediately the next write operation will be started which saves the time andgives more data written.

Figure 8.25: Mode Set Control Word of 8257 Chip

Figure 8.26: Status Control Word of 8257 Chip



Notes� D6 Bit (Terminal Count Stop Bit): This bit will be set for the DMA operation to be completedfor the selected channel, if it is reset it means the DMA operation is in process at thatselected channel.

� D7 Bit (Auto Load Mode Bit): This bit will be set for the selection of auto load mode for1 condition and will disable the auto load mode when 0 will be there. In auto load mode,the channel 2 will only be in function. In this mode, the parameters of channel 2 will becopied to the channel 3 and channel 2 will transfer the first block and makes an updatecycle in which the contents of the channel 3 will be transferred back to the channel 2, thisprocess is also known as the repeat block operation.

For Status Control Word:

� D0-D3 Bits (Terminal Count Bits): These bits are defined for giving the status of the terminalcounts of different channels by the corresponding bits i.e. they will give the status whetherthe DMA operation at any channel is completed or not. Set condition will give that theDMA cycle is completed and reset will show that the DMA cycle is presently going on.

� D4 Bit (Update Flag Bit): This bit is used to give the status of the update cycle whether it ispresently executing or not. These conditions can be given by set condition which showspresently the update cycle is executing and reset will show that there is no execution ofupdate cycle.

� D4-D7 Bits (Constant Bit): These bits will be constant 0 all the time.

Self Assessment


11. In 8257 chip which bit is used to give the status of the update cycle whether it is presentlyexecuting or not.

(a) D4 (b) D1

(c) D5 (d) D8

8.8 RS 232-C (Recommended Standard-232)

Description of RS 232 cable is given as:

8.8.1 Function

This is basically a cable used to connect processor and the peripherals. RS-232 (Recommendedstandard-232) is a standard interface approved by the Electronic Industries Association (EIA) forconnecting serial devices. In other words, RS-232 is a long established standard that describesthe physical interface and protocol for relatively low-speed serial data communication betweencomputers and related devices. An industry trade group, the Electronic Industries Association(EIA), defined it originally for teletypewriter devices. In 1987, the EIA released a new version ofthe standard and changed the name to EIA-232-D. Many people, however, still refer to thestandard as RS-232C, or just RS-232. RS-232 is the interface that your computer uses to talk to andexchange data with your modem and other serial devices. The serial ports on most computersuse a subset of the RS-232C standard.


It is a 25 pin connector where different pins have different operations.



Notes

� TxD: This pin carries data from the computer to the serial device.

� RXD: This pin carries data from the serial device to the computer.

� DTR Signals: DTR is used by the computer to signal that it is ready to communicate withthe serial device like modem. In other words, DTR indicates to the Dataset (i.e., the modemor DSU/CSU) that the DTE (computer) is ON.

� DSR: Similarly to DTR, Data set ready (DSR) is an indication from the Dataset that it is ON.

� DCD: Data Carrier Detect (DCD) indicates that carrier for the transmit data is ON.

� RTS: This pin is used to request clearance to send data to a modem.

� CTS: This pin is used by the serial device to acknowledge the computer’s RTS Signal. Inmost situations, RTS and CTS are constantly on throughout the communication session.

� Clock Signals (TC, RC, and XTC): The clock signals are only used for synchronouscommunications. The modem or DSU extracts the clock from the data stream and providesa steady clock signal to the DTE. Note that the transmit and receive clock signals do nothave to be the same, or even at the same baud rate.

� CD: CD stands for Carrier Detect. Carrier Detect is used by a modem to signal that it hasa made a connection with another modem, or has detected a carrier tone. In other words,this is used by the modem to signal that a carrier signal has been received from a remotemodem.

� RI: RI stands for Ring Indicator. A modem toggles (keystroke) the state of this line whenan incoming call rings your phone. In other words, this is used by an auto answer modemto signal the receipt of a telephone ring signal.

The Carrier Detect (CD) and the Ring Indicator (RI) lines are only available in connectionsto a modem. Because most modems transmit status information to a PC when either acarrier signal is detected (i.e. when a connection is made to another modem) or when theline is ringing, these two lines are rarely used.

Self Assessment

Fill in the blank:

12. The Carrier Detect (CD) and the …………………… lines are only available in connectionsto a modem.

Figure 8.27: Pin Configuration of RS-232 C Connector



Notes8.9 Parallel Printer Interface

Description of parallel printer interface port is given as:

8.9.1 Function

This is basically a connecting port used to connect the printer to the system. This is located at therear of CPU. This port can be used as both receiver as well as transmitter which are done by theD0-D7 data lines of the port. It can also support the devices such as CD-ROMs other than theprinter.


It is a 36 pin port where different pins have different operations.

� Pin 1 ( STR ): This is the out pin used to give the strobe signal to the printer.

� Pin 2-9 (D0-D7): These are 8-bit data lines of the chip which are bidirectional in nature andare used to transfer data bits between processor and printer.

� Pin 10 ( ACK ): This is an input pin used to take the acknowledgement signal from theprinter for the data transfer.

� Pin 11 (BUSY): It is an input pin used to take the status signal from the printer about thestatus that the printer is busy in any execution.

� Pin 12 (PAPER): It is an input pin used to give the status that the printer is now out ofpaper and it cannot make the printing operation.

� Pin 13 (ONLINE): It is an input pin used to take the signal that the printer is used onlinethat means it is used by any other system connected.

� Pin 17 (PG): It is the protective ground pin used to give the earthed ground to the port.

� Pin 18 (+5 V): It is the power supply pin used to give the power of +5 V to the port.

� Pin 31 ( RESET ): It is an output pin used to give the reset signal to the printer.

Figure 8.28: Pin Configuration of Parallel Printer Interface



Notes � Pin 32 ( ERROR ): It is an output pin used to give the status that there is any error presentat the printer terminal.

� Pin 36 ( SEL ): It is an output pin used to select the printer or enable the printer.

All the other pins of the port are signal grounded (GND) i.e. it will be connected to the 0 Vsupply.

Self Assessment

Fill in the blank:

13. …………………… is an output pin used to give the status that there is any error present atthe printer terminal.

8.10 Universal Serial Bus (USB)

Description of USB is given as:

8.10.1 Function

This is basically a connecting bus used to connect the peripherals and the processor. These areused for the devices having low noise applications like sound cards, video cards, keyboards andmodems.

The USB connector can work with the maximum of 100 mA current. The data signals transferredby this connector are bi-phase in nature having +ve and –ve data bits having voltage levels of+5 V and 0 V, respectively.


It is a 4 pin connector where different pins have different operations.

� Pin 1 (+5 V): It is the power supply pin used to give the power of +5 V to the connector.

� Pin 2 (–Data): This pin is used to give the data of –ve phase that means it allows the datavalues having 0 V level.

� Pin 3 (+Data): This pin is used to give the data of +ve phase that mean it allows the datavalues having +5 V level.


Figure 8.29: Pin Configuration of USB Connector




Fill in the blanks:

14. The USB connector can work with the maximum of …………………… current.

15. In USB, …………………… is a power supply pin used to give the ground terminal to thechip by having 0V at this pin.

�Case Study Touch Tablets

Touch tablets are an interesting subject for a case study. On the one hand, they aresimplicity personified. They are just a flat surface that can sense that it has beentouched and communicate to the computer the location of where that touch occurred.

On the other hand, they form the basis for an extremely broad and diverse set of physicaland logical manifestations, as well as interaction techniques.

Hence, they constitute a rich source for improving our understanding of input. In simplestterms, a touch tablet is typically mounted horizontally on a working surface and operatedwith a single finger. But from this basic configuration is a broad range of variations. Theycan range in size from an inch per side to several feet. They differ in how much pressure isrequired before a touch is registered. Some are capable of continuously reporting to thecomputer the amount of pressure being applied by the touch. Some are able to be operatedwith a stylus as well as a finger, while others are capable of independently sensing thelocation (and sometimes pressure) of multiple simultaneous points of touch.

The biggest problem in any discussion around touch tablets stems from confusing themwith touch screens. The problem is legitimate since the differences between the two arenot always a clear cut as one might first think. Both are controlled by touch. With touchscreens, the touch technology is superimposed over a display. It is technically a touchscreen, since the touch sensor is over a display. On the other hand, it is more like a touchtablet, since it is not mounted on the primary visual display, and is horizontally mountedin a tablet-like fashion.

Questions:

1. Explain difference between touch tablet and laptop.

2. What are the key issues in touch tablet?

Source: http://www.billbuxton.com/input05.TouchTablets.pdf

8.11 Summary

� Peripheral devices are the external devices connected to the processors to enhance theirfunctions.

� Peripheral devices have two categories named input devices (to take data inside themicroprocessor) and output devices (to take data out of the microprocessor).

� The I/O devices are defined according to their working scheme as memory mapped I/O,I/O mapped I/O, Interrupt driven I/O and DMA driven I/O.



Notes � Interfacing is the process by which the external devices are connected to the processor sothat both can control each other’s functions.

� Interfacing is of two types named Hardware (Hardwired connections) and software(programmed connections) interfacing and the full interfacing is said to be done onlywhen these two interfacings are done.

� 8253/8254 chip is known as the programmable Timer/counter and is used to generate thetime base functions as timer and counts the clock pulses given to it as a counter.

� 8255 chip is known as the programmable peripheral interface and is used as the interfaceor medium between the peripherals and the processor.

� 8251 chip is known as the universal synchronous asynchronous receiver transmitter(USART) and is used for the serial communication process.

� 8259 chip is known as the programmable interrupt controller and is used to control theinterrupts coming from the peripheral devices to the processors.

� 8237 chip is known as the programmable DMA controller and is used as a medium betweenperipheral devices and the processor for the DMA process.

� RS-232C is a 25 pin connector cable used to connect different blocks inside the CPU.

� Parallel Printer Interface is a 36 pin port used to connect the printers to the processor.

� Universal serial bus (USB) is a connector used to connect different sound and video devicesto the processor and is used for the low noise applications.

8.12 Keywords

Interfacing: It is the process by which the external devices are connected to the processor so thatboth can control each other’s functions.

Parallel Printer Interface: It is a 36 pin port used to connect the printers to the processor.

Peripheral Devices: External devices connected to the processors to enhance their functions.

Universal Serial Bus (USB): It is a connector used to connect different sound and video devicesto the processor and is used for the low noise applications.


1. Define different types of I/O devices with the examples.

2. Define the term Interfacing and its types and give a brief idea of different steps to interfaceany peripheral to the microprocessor.

3. Define the 8254 chip according to its block diagram.

4. Give the control word/s associated to the 8255 chip and define each of its controlling bitsand their functions associated to them.


6. Give the control word/s associated to the 8259 chip and define each of its controlling bitsand their functions associated to them.




Notes8. Define the RS-232C connector according to its pin configuration and define the functionsassociated to each of the pins.

9. Define the Parallel Printer Interface port according to its pin configuration and define thefunctions associated to each of the pins.

10. Define the Universal Serial Bus (USB) connector according to its pin configuration anddefine the functions associated to each of the pins.


1. (c) 2. (b)

3. (a) 4. (a)

5. (b) 6. (c)

7. (a) 8. (c)

9. (d) 10. (c)

11. (a) 12. Ring Indicator (RI)

13. Pin 32 14. 100 mA

15. Pin 4





Online links 112.196.5.130/edusat/poly/Electrical/sem-4/Memory_interfacing.ppt

http://www.billbuxton.com/input05.TouchTablets.pdf

www.cs.gmu.edu/~setia/cs365-S02/Ch8-2.pdf

www.eee.metu.edu.tr/~cb/e447/Chapter%206%20-%20v2.2.pdf



Notes Unit 9: Introduction to 8085 Instructions

CONTENTS

Objectives

Introduction

9.1 Data Transfer Operations

9.1.1 MOV Rd, Rs

9.1.2 MOV M,R or MOV R,M

9.1.3 MOV ALN,R or MOV R,ALN

9.1.4 MVI R, Data Value

9.1.5 MVI M, Data Value

9.1.6 LXI RP, Data Value (16-bit)

9.1.7 LDA ALN/Rs

9.1.8 STA ALN/Rs

9.1.9 SHLD ALN

9.1.10 LHLD ALN

9.1.11 STAX RP

9.1.12 LDAX RP

9.1.13 XCHG

9.2 Arithmetic Group

9.2.1 ADD R/M

9.2.2 ADC R/M

9.2.3 ADI Data Value

9.2.4 ACI Data Value

9.2.5 DAD RP

9.2.6 SUB R/M

9.2.7 SBB R/M

9.2.8 SUI Data Value

9.2.9 SBI Data Value

9.2.10 INR R/M

9.2.11 DCR R/M

9.2.12 INX RP

9.2.13 DCX RP

9.2.14 DAA

9.3 Logical GroupContd...


Unit 9: Introduction to 8085 Instructions

Notes9.3.1 ANA R/M

9.3.2 ANI Data Value

9.3.3 ORA R/M

9.3.4 ORI Data Value

9.3.5 XRA R/M

9.3.6 XRI Data Value

9.3.7 CMA

9.3.8 CMC

9.3.9 STC

9.3.10 CMP R/M

9.3.11 CPI Data Value

9.3.12 RLC

9.3.13 RRC

9.3.14 RAL

9.3.15 RAR

9.4 Branch Group

9.4.1 JMP ALN

9.4.2 Conditional JMP

9.4.3 CALL ALN

9.4.4 Conditional CALL

9.4.5 RET ALN

9.4.6 Conditional RET

9.5 Machine Control Group

9.5.1 NOP

9.5.2 HLT

9.5.3 EI

9.5.4 DI

9.5.5 RIM

9.5.6 SIM

9.5.7 IN 8-bit Address

9.5.8 OUT 8-bit Address

9.5.9 RST n

9.6 Stack I/O Operations

9.6.1 SPHL

9.6.2 PUSH RPContd...



Notes 9.6.3 PUSH PSW

9.6.4 POP RP

9.6.5 POP PSW

9.6.6 XTHL


9.7.1 One-Byte (1-byte) Instruction

9.7.2 Two-Byte (2-Byte) Instruction

9.7.3 Three-Byte (3-Byte) Instruction

9.8 Summary

9.9 Keywords



Objectives

After studying this unit, you will be able to define:

� Data Transfer Group Instructions

� Arithmetic Group Instructions

� Logical Group Instructions

� Branching Group Instructions

� Stack Control Group Instructions

� Machine Control Group Instructions

Introduction

Instructions are the commands given by the user in the software form to make different executionsthrough the microprocessors as the microprocessors can understand only assembly language orthe language of binary bits so these instructions are defined in binary codes that mean these aredifferent binary patterns used as commands defined for any particular execution and named asinstructions. For the user point of view the binary patterns are complicated and complex tounderstand and write so we use alphanumeric codes i.e. alphabets and numeral numbers toshow any instruction. In any language the instructions are defined in a unique particular formatin which they are represented. The processor has the understanding of this format only and ifthere will be any disturbance to this format the processor will show an error for that instruction.This particular format for any instruction is known as the Instruction-Set. The instructions of8085 microprocessor are classified as Data Transfer Group, Arithmetic Group, Logical Group,Branching Group, Stack Control and Machine Control Group.

9.1 Data Transfer Operations

This group specifies the instructions which are used to transfer data from one point to another.The instructions are:



Notes9.1.1 MOV Rd, Rs

� Full form of the Instruction: Move the content of source register to the destination register.

� Function of the Instruction: This instruction will copy the data content of the sourceregister specified to the specified destination register but the contents of source registerwill be unchanged. The registers used here will be A, B, C, D, E, H and L.

� Algorithm of the Instruction: Rs → Rd.

� Type of the Instruction: 1-byte instruction.

� Addressing Mode: Register Addressing Mode.

Example: MOV B, C

In the given example the source register is C and the destination register is B and theopcode MOV will move the data content of C into B but the content of C will not changei.e. if C has data 72H and B has data 28H then after the execution of this instruction registerB will have 72H and register C will have 72H.

9.1.2 MOV M,R or MOV R,M

� Full form of the Instruction: Move the content of source register or memory pointer to thedestination register or memory pointer.

� Function of the Instruction: This instruction will copy the data content of the sourceregister or memory pointer specified to the specified destination register or memorypointer but the contents of source register or memory pointer will be unchanged. Theregisters used here will be A, B, C, D and E and the memory pointer is used to point thecontents of H-L pair which will be used as 16-bit address location number and this will beused in the instruction as memory location.

� Algorithm of the Instruction: Rs or Ms → Rd or Md.


� Addressing Mode: Register Indirect Addressing Mode.

Example: MOV D, M

In the given example the source is a memory pointer and the destination register is D andthe opcode MOV will move the data content of pointing memory location number toregister D but the content of memory location number will not change i.e. if the H-L pairhas the 16-bit data value 3407H then this data value will now act as address locationnumber and the address location 3407H will now act as source and the content of thislocation will be transferred to the register D but the contents of 3407H will be unchanged.

9.1.3 MOV ALN,R or MOV R,ALN

� Full form of the Instruction: Move the content of source register or Address Locationnumber to the destination register or Address Location Number.

� Function of the Instruction: This instruction will copy the data content of the sourceregister or source address location number specified to the specified destination registeror address location number but the contents of source register or address location number



Notes will be unchanged. The registers used here will be A, B, C, D, E, H and L and the addresslocation number is direct address coding of any memory location.

� Algorithm of the Instruction: Rs or ALNs → Rd or ALNd.


� Addressing Mode: Direct Addressing Mode.

Example: MOV 2000H, A

In the given example the source is register A and the destination is address locationnumber 2000H and the opcode MOV will move the data content of register A to theaddress location number 2000H but the content of register A will not change i.e. if theregister A is having a data 34H and address 2000H is having 23H then after the execution2000H will have 34H and register A will have 34H.

9.1.4 MVI R, Data Value

� Full form of the Instruction: Move the immediate data value to the destination register.

� Function of the Instruction: This instruction will copy the data content given by the inputdevices to the specified destination register. The registers used here will be A, B, C, D, E,H and L and this will be used in the instruction as destination.

� Algorithm of the Instruction: Immediate data value → Rd.


� Addressing Mode: Immediate Addressing Mode.

Example: MVI D, 60H

In the given example the source is an input device (like key-pad) and the destinationregister is D and the opcode MVI will move the data content given by the input device(Immediate data value) to register D i.e. the immediate data value given by the inputdevice is 60H and this will be transferred to the register D.

9.1.5 MVI M, Data Value

� Full form of the Instruction: Move the immediate data value to the destination memorypointer.

� Function of the Instruction: This instruction will copy the data content given by the inputdevices to the specified destination memory pointer address location number. The registerused here will be H-L pair for memory pointing and the address location number generatedby this pair will be used in the instruction as destination.

� Algorithm of the Instruction: Immediate data value → Memory pointer ALN.



Example: MVI M, 60H

In the given example the source is the immediate data value and the destination is addresslocation number pointed by H-L pair and the opcode MVI will move the immediate data



Notescontent of input device to address location number pointed by H-L pair i.e. if the H-L pairhas the 16-bit data value 2000H then this data value will now act as address locationnumber and the address location 2000H will now act as destination and the immediatedata value will be transferred to the ALN 2000H.

9.1.6 LXI RP, Data Value (16-bit)

� Full form of the Instruction: Load the 16-bit immediate data value to the destinationregister pair.

� Function of the Instruction: This instruction will copy the data content given by the inputdevices to the specified destination register pair. The register pairs used here will be B-C,D-E and H-L pair for destination and the immediate data of 16-bit, as the register pair willhave 16-bit length, will be transferred to this destination.

� Algorithm of the Instruction: Immediate data value (16-bit) → Register pair.



Example: LXI B, 2060H

In the given example the source is the immediate data value and the destination is B-Cregister pair and the opcode LXI will load the immediate data content of input device toB-C register pair i.e. if the immediate data value of 16-bit is 2000H by the use of thisinstruction this data will be loaded to the B-C register pair.

9.1.7 LDA ALN/Rs

� Full form of the Instruction: Load to the accumulator the data content of the specifiedsource register or address location number.

� Function of the Instruction: This instruction will load the data content given by thespecified source register or ALN to accumulator register (Register A).

� Algorithm of the Instruction: ALN or Rs → Accumulator.

� Type of the Instruction: 1-byte instruction for source as register and 3-byte for source asALN.

� Addressing Mode: Register Addressing Mode (Register as source) and Direct AddressingMode (ALN as source).

Example: LDA 2060H or LDA C

In the given example the source is the ALN 2060H or register C and the destination isregister A and the opcode LDA will load the data content of ALN 2060H or register C to theregister A.

9.1.8 STA ALN/Rs

� Full form of the Instruction: Store from the accumulator to the specified ALN or register.

� Function of the Instruction: This instruction will store the data content given by theregister A to the specified ALN or register.



Notes � Algorithm of the Instruction: Accumulator → ALN or Rd.

� Type of the Instruction: 1-byte instruction for register as destination and 3-byte for ALNas destination.

� Addressing Mode: Register Addressing Mode (Register as destination) and Direct AddressingMode (ALN as destination).

Example: STA 2060H or STA C

In the given example the source is the register A and the destination is ALN 2060H orregister C and the opcode LDA will load the data content of accumulator to the ALN 2060Hor register C.

9.1.9 SHLD ALN

� Full form of the Instruction: Store 16-bit data from the H-L register pair to the specifiedALN and the next to the specified ALN.

� Function of the Instruction: This instruction will store the 16-bit data content given by theregister pair H-L to the specified ALN and the next ALN to the specified ALN.

Notes The content of register L will be transferred to the ALN specified in the instructionand the content of register H will be transferred to the next ALN to the specified ALN.

� Algorithm of the Instruction: L → ALN and H → Next to the specified ALN (ALN+1)

� Type of the Instruction: 3-byte instruction

� Addressing Mode: Direct Addressing Mode

Example: SHLD 2000H

In the given example the source is the register pair H-L and the destination is ALN 2000Hand the opcode SHLD will store the 8-bit data content of register L to the ALN 2000H andthe 8-bit data content of register H to the ALN 2001H.

9.1.10 LHLD ALN

� Full form of the Instruction: Load 16-bit data to the H-L register pair from the specifiedALN and the next to the specified ALN.

� Function of the Instruction: This instruction will load the 16-bit data content given by theALN and the next ALN to the specified ALN to the H-L register pair. The content of ALNspecified will be transferred to the register L in the instruction and the content of next ALNto the specified ALN will be transferred to the register H.

� Algorithm of the Instruction: ALN → L and Next to the specified ALN (ALN+1) → H





NotesExample: LHLD 2000H

In the given example the destination is the register pair H-L and the source is ALN 2000Hand the opcode SHLD will store the 8-bit data content of ALN 2000H to register L and the8-bit data content of ALN 2001H to register H.

9.1.11 STAX RP

� Full form of the Instruction: Store from the register A to the ALN generated by thespecified register pair in the instruction.

� Function of the Instruction: This instruction will store the 8-bit data content to the specifiedALN generated by the 16-bit data value of the register pair specified in the instruction.

� Algorithm of the Instruction: A → ALN specified by the register pair



Example: STAX H

In the given example the source is the accumulator and it will transfer its 8-bit data to theALN defined by the 16-bit data value of the H-L register pair i.e. if the 16-bit data contentof H-L pair is 2010H then this data value will be treated as ALN by the instruction and willbe used as destination then the data content of the register A will be transferred to the2010H ALN.

9.1.12 LDAX RP

� Full form of the Instruction: Load to the register A from the ALN generated by thespecified register pair in the instruction.

� Function of the Instruction: This instruction will store the 8-bit data content from thespecified ALN generated by the 16-bit data value of the register pair specified in theinstruction to the register A.

� Algorithm of the Instruction: ALN specified by the register pair → A



Example: LDAX H

In the given example the destination is the accumulator and the ALN defined by the 16-bitdata value of the H-L register pair will transfer its 8-bit data to the register A i.e. if the 16-bit data content of H-L pair is 2010H then this data value will be treated as ALN by theinstruction and will be used as source then the data content of the 2010H ALN will betransferred to the register A.

9.1.13 XCHG

� Full form of the Instruction: Exchange the data content between H-L pair and D-E pair.



Notes � Function of the Instruction: This instruction will exchange the data content between H-Lpair and D-E pair i.e. the content of H-L pair will be transferred to D-E pair and from D-Epair to the H-L pair.

� Algorithm of the Instruction:

H ↔ D

L ↔ E


� Addressing Mode: Implied Addressing Mode

Example: XCHG

In the given example the source and the destination is H-L pair and D-E pair both i.e. thedata content of both the register pairs are exchanged and after the execution of this instructionthe data contents will be exchanged and there is no need to mention any source ordestination in the instruction.

Self Assessment

Fill in the blanks:

1. …………………… group specifies the instructions which are used to transfer data fromone point to another.

2. The instruction …………………… store 16-bit data from the H-L register pair to the specifiedALN and the next to the specified ALN.

3. The instruction …………………… exchange the data content between H-L pair and D-Epair.

9.2 Arithmetic Group

This group specifies the instructions which are used to perform arithmetic functions of themicroprocessor. In 8085 there will be 8-bit arithmetic functions and all the functions are doneusing register A so in all the instructions the destination and the first data value to be executedis pre-defined in the instructions and the user will mention only the source point or the seconddata value in the instructions.

Did u know? 8085 can perform only addition and subtraction processes so the arithmeticinstructions are defined only for these two functions.

The arithmetic instructions are:

9.2.1 ADD R/M

� Full form of the Instruction: Add the content of given register or the memory pointer withthe content of register A.

� Function of the Instruction: This instruction will add the contents of register or memorypointer with the accumulator contents and the result of this addition will be transferred tothe accumulator automatically. The register used can be B, C, D, E, H and L in the instruction.



Notes� Algorithm of the Instruction: A+ R/M → A


� Addressing Mode: Register Addressing mode for register content and Register IndirectAddressing Mode for memory pointer.

Example: ADD B or ADD M

In the given examples in the first one the content of register B and register A will be addedand the result will go in the register A. in the second example the content of the ALNdefined by the memory pointer will be added to the register A content and the result willbe stored in the register A.

9.2.2 ADC R/M

� Full form of the Instruction: Add the content of given register or the memory pointer withthe content of register A and the carry flag bit.

� Function of the Instruction: This instruction will add the contents of register or memorypointer with the accumulator contents and the carry flag bit and the result of this additionwill be transferred to the accumulator automatically. The register used can be B, C, D, E, Hand L in the instruction.

� Algorithm of the Instruction: A+ R/M + Carry Flag bit → A



Example: ADC B or ADC M

In the given examples in the first one the content of register B and register A with the carryflag bit will be added and the result will go in the register A. in the second example thecontent of the ALN defined by the memory pointer will be added to the register A contentand carry flag and the result will be stored in the register A.

9.2.3 ADI Data Value

� Full form of the Instruction: Add the 8-bit immediate data value with the content ofregister A.

� Function of the Instruction: This instruction will add the 8-bit immediate data value withthe accumulator contents and the result of this addition will be transferred to theaccumulator automatically.

!Caution The immediate data value will be given by the input devices.

� Algorithm of the Instruction: A+ 8-bit data value ®A


� Addressing Mode: Immediate Addressing Mode



NotesExample: ADI 02H

In the given example the 8-bit immediate data value 02H given by the input devices andthe register A content will be added and the result will go in the register A.

9.2.4 ACI Data Value

� Full form of the Instruction: Add the 8-bit immediate data value with the content ofregister A and the carry flag bit.

� Function of the Instruction: This instruction will add the 8-bit immediate data value withthe accumulator contents and the carry flag bit and the result of this addition will betransferred to the accumulator automatically. The immediate data value will be given bythe input devices.

� Algorithm of the Instruction: A+ 8-bit data value + Carry Flag → A


� Addressing Mode: Immediate Addressing Mode

Example: ADI 02H

In the given example the 8-bit immediate data value 02H given by the input devices andthe register A content and the carry flag bit will be added and the result will go in theregister A.

9.2.5 DAD RP

� Full form of the Instruction: Add the content of H-L pair with the content of specifiedregister pair.

� Function of the Instruction: This instruction will add the 16-bit content of H-L pair and thespecified register pair and the result of this addition will be transferred to the H-L pairautomatically i.e. the H-L pair is working here as accumulator for 16-bit addition function.

� Algorithm of the Instruction: H-L + Register pair → H-L



Example: DAD B

In the given example the 16-bit data value of H-L pair will be added with the B-C registerpair and the result of this execution of 16-bit length will be transferred to the H-L pairautomatically.

9.2.6 SUB R/M

� Full form of the Instruction: Subtract the content of given register or the memory pointerwith the content of register A.

� Function of the Instruction: This instruction will subtract the contents of register or memorypointer with the accumulator contents and the result of this subtraction will be transferred



Notesto the accumulator automatically. The register used can be B, C, D, E, H and L in theinstruction.

� Algorithm of the Instruction: A - R/M → A



Example: SUB B or SUB M

In the given examples in the first one the content of register B and register A will besubtracted and the result will go in the register A. in the second example the content of theALN defined by the memory pointer will be subtracted to the register A content and theresult will be stored in the register A.

9.2.7 SBB R/M

� Full form of the Instruction: Subtract the content of given register or the memory pointerwith the content of register A and the carry flag bit.

� Function of the Instruction: This instruction will subtract the contents of register or memorypointer with the accumulator contents and the carry flag bit and the result of this subtractionwill be transferred to the accumulator automatically. The register used can be B, C, D, E, Hand L in the instruction.

� Algorithm of the Instruction: A- R/M - Carry Flag bit → A



Example: SBB B or SBB M

In the given examples in the first one the content of register B and register A with the carryflag bit will be subtracted and the result will go in the register A. in the second examplethe content of the ALN defined by the memory pointer will be subtracted to the register Acontent and carry flag and the result will be stored in the register A.

9.2.8 SUI Data Value

� Full form of the Instruction: Subtract the 8-bit immediate data value with the content ofregister A.

� Function of the Instruction: This instruction will subtract the 8-bit immediate data valuewith the accumulator contents and the result of this subtraction will be transferred to theaccumulator automatically. The immediate data value will be given by the input devices.

� Algorithm of the Instruction: A- 8-bit data value → A





NotesExample: SUI 02H

In the given example the 8-bit immediate data value 02H given by the input devices andthe register A content will be subtracted and the result will go in the register A.

9.2.9 SBI Data Value

� Full form of the Instruction: Subtract the 8-bit immediate data value with the content ofregister A and the carry flag bit.

� Function of the Instruction: This instruction will subtract the 8-bit immediate data valuewith the accumulator contents and the carry flag bit and the result of this subtraction willbe transferred to the accumulator automatically. The immediate data value will be givenby the input devices.

� Algorithm of the Instruction: A- 8-bit data value - Carry Flag → A



Example: ADI 02H

In the given example the 8-bit immediate data value 02H given by the input devices andthe register A content and the carry flag bit will be subtracted and the result will go in theregister A.

9.2.10 INR R/M

� Full form of the Instruction: Increment the content of given register or the memorypointer.

� Function of the Instruction: This instruction will increment the contents of register ormemory pointer and the result will be transferred to the register or ALN defined by thememory pointer automatically. The register used can be B, C, D, E, H and L in the instruction.

� Algorithm of the Instruction: R/M + 1 → R/M



Example: INR C or INR M

In the given examples in the first one the content of register C will be incremented and theresult will go in the register C. In the second example the content of the ALN defined bythe memory pointer will be incremented and the result will be stored in the ALN specifiedby the memory pointer.

9.2.11 DCR R/M

� Full form of the Instruction: Decrement the content of given register or the memorypointer.



Notes� Function of the Instruction: This instruction will decrement the contents of register ormemory pointer and the result will be transferred to the register or ALN defined by thememory pointer automatically. The register used can be B, C, D, E, H and L in the instruction.

� Algorithm of the Instruction: R/M - 1 → R/M



Example: DCR C or DCR M

In the given examples in the first one the content of register C will be decremented and theresult will go in the register C. In the second example the content of the ALN defined bythe memory pointer will be decremented and the result will be stored in the ALN specifiedby the memory pointer.

9.2.12 INX RP

� Full form of the Instruction: Increment the 16-bit content of given register pair.

� Function of the Instruction: This instruction will increment the 16-bit contents of registerpair and the result will be transferred back to the register pair automatically. The registerpairs used can be B-C, D-E and H-L in the instruction.

� Algorithm of the Instruction: Register pair + 1 → Register pair



Example: INX D

In the given example the content of register pair D-E will be incremented and the resultwill go back in the register pair D-E.

9.2.13 DCX RP

� Full form of the Instruction: Decrement the 16-bit content of given register pair.

� Function of the Instruction: This instruction will decrement the 16-bit contents of registerpair and the result will be transferred back to the register pair automatically. The registerpairs used can be B-C, D-E and H-L in the instruction.

� Algorithm of the Instruction: Register pair - 1 → Register pair



Example: DCX D

In the given example the content of register pair D-E will be decremented and the resultwill go back in the register pair D-E.



Notes 9.2.14 DAA

� Full form of the Instruction: Decimal Adjust the Accumulator content.

� Function of the Instruction: This instruction will convert the content of accumulator intopacked BCD format, i.e. the characters will range from 0 to 9 or 0000 to 1001 for thispurpose first the lower nibble will be checked if it is more than 9 then 06H will be addedor there will be no change, then higher nibble will be checked for greater than zerocondition and if there is higher than 9 condition then 60H will be added or there will be nochange in the accumulator content. When both the nibbles are less than 9 then the wholeaccumulator content is in packed BCD format and there is no need to make any change inthe accumulator content.


Accumulator + 06H (Lower nibble of A > 9)

Accumulator + 60H (Higher nibble of A > 9)

No change (Lower and higher nibble both < 9)


� Addressing Mode: Implied Addressing Mode.

Example: DAA

In the given example if the content of accumulator is 7DH then first lower nibble D ischecked which greater than 9 is, so 06H will be added to the accumulator content whichwill result the accumulator content 73H. Now both the nibbles are less than 9 so there is noneed to make any change with the accumulator content and after the execution of thegiven example the content of accumulator will be 73H.

Task Compare and contrast ADD R/M and ADC R/M.

Self Assessment

Fill in the blanks:

4. …………………… group specifies the instructions which are used to perform arithmeticfunctions of the microprocessor.

5. …………………… instruction add the content of H-L pair with the content of specifiedregister pair.

9.3 Logical Group

This group specifies the instructions which are used to perform logical functions of themicroprocessor. In 8085 there will be 8-bit logical functions and all the functions are done usingregister A so in all the instructions the destination and the first data value to be executed is pre-defined in the instructions and the user will mention only the source point or the second datavalue in the instructions.



Notes

Notes 8085 can perform AND, OR, XOR, NOT and Rotate processes so the logicalinstructions are defined only for these functions.

The logical instructions are:

9.3.1 ANA R/M

� Full form of the Instruction: AND the content of given register or the memory pointerwith the content of register A.

� Function of the Instruction: This instruction will have the AND operation done to thecontents of register or memory pointer with the accumulator contents and the result ofthis operation will be transferred to the accumulator automatically. The register used canbe B, C, D, E, H and L in the instruction.

� Algorithm of the Instruction: A AND R/M →A



Example: ANA B or ANA M

In the given examples in the first one the content of register B and register A will beANDed and the result will go in the register A. in the second example the content of theALN defined by the memory pointer will be ANDed to the register A content and theresult will be stored in the register A.

9.3.2 ANI Data Value

� Full form of the Instruction: AND the 8-bit immediate data value with the content ofregister A.

� Function of the Instruction: This instruction will have the AND operation done to the 8-bit immediate data value with the accumulator contents and the result of this operationwill be transferred to the accumulator automatically. The immediate data value will begiven by the input devices.

� Algorithm of the Instruction: A AND 8-bit data value → A



Example: ANI 02H

In the given example the 8-bit immediate data value 02H given by the input devices andthe register A content will be ANDed and the result will go in the register A.

9.3.3 ORA R/M

� Full form of the Instruction: OR the content of given register or the memory pointer withthe content of register A.



Notes � Function of the Instruction: This instruction will have the OR operation done to thecontents of register or memory pointer with the accumulator contents and the result ofthis operation will be transferred to the accumulator automatically. The register used canbe B, C, D, E, H and L in the instruction.

� Algorithm of the Instruction: A OR R/M → A



Example: ORA D or ORA M

In the given examples in the first one the content of register D and register A will be ORedand the result will go in the register A. in the second example the content of the ALNdefined by the memory pointer will be ORed to the register A content and the result willbe stored in the register A.

9.3.4 ORI Data Value

� Full form of the Instruction: OR the 8-bit immediate data value with the content of registerA.

� Function of the Instruction: This instruction will have the OR operation done to the 8-bitimmediate data value with the accumulator contents and the result of this operation willbe transferred to the accumulator automatically. The immediate data value will be givenby the input devices.

� Algorithm of the Instruction: A OR 8-bit data value → A



Example: ORI 20H

In the given example the 8-bit immediate data value 20H given by the input devices andthe register A content will be ORed and the result will go in the register A.

9.3.5 XRA R/M

� Full form of the Instruction: XOR the content of given register or the memory pointerwith the content of register A.

� Function of the Instruction: This instruction will have the XOR operation done to thecontents of register or memory pointer with the accumulator contents and the result ofthis operation will be transferred to the accumulator automatically. Here the XOR operationis defined by y a.b a.b= + and each bit will be XORed according to the given expressionfor having the result. The register used can be B, C, D, E, H and L in the instruction.

� Algorithm of the Instruction: A XOR R/M → A





NotesExample: XRA D or XRA M

In the given examples in the first one the content of register D and register A will beXORed and the result will go in the register A. in the second example the content of theALN defined by the memory pointer will be XORed to the register A content and theresult will be stored in the register A.

9.3.6 XRI Data Value

� Full form of the Instruction: XOR the 8-bit immediate data value with the content ofregister A.

� Function of the Instruction: This instruction will have the XOR operation done to the 8-bitimmediate data value with the accumulator contents and the result of this operation willbe transferred to the accumulator automatically. The immediate data value will be givenby the input devices.

� Algorithm of the Instruction: A XOR 8-bit data value → A



Example: XRI 20H

In the given example the 8-bit immediate data value 20H given by the input devices andthe register A content will be XORed and the result will go in the register A.

9.3.7 CMA

� Full form of the Instruction: Compliment the accumulator.

� Function of the Instruction: This instruction will give the compliment or invert the contentof the accumulator that means all the bits of accumulator will be converted as 0 willbecome 1 and 1 will become 0. It is a logical NOT function done by the ALU and the resultwill be stored back to the accumulator.

� Algorithm of the Instruction: A → A


� Addressing Mode: Implicit Addressing Mode.

Example: CMA

In the given example the 8-bit accumulator content will be inverted and will be storedback to the accumulator. If the content of accumulator is 73H then the bit pattern will be01110011 by taking the NOT operation or inverting the bit pattern we will have 10001100then the hex equivalent will be 8CH. So the accumulator content will be 8CH after theexecution of this instruction.

9.3.8 CMC

� Full form of the Instruction: Compliment the Carry Flag Bit.

� Function of the Instruction: This instruction will give the compliment or invert the contentof the carry flag bit that means the bit will be converted as 0 will become 1 and 1 will



Notes become 0. It is a logical NOT function done by the ALU and the result will be stored backto the carry flag bit.

� Algorithm of the Instruction: Carry Flag Bit → Carry Flag Bit



Example: CMC

In the given example the carry flag bit will be inverted and will be stored back to the carryflag bit. Let the content of carry flag bit is 1 by taking the NOT operation or inverting thebit we will have 0 at the carry flag bit.

9.3.9 STC

� Full form of the Instruction: Set the Carry Flag Bit.

� Function of the Instruction: This instruction will set the carry flag bit that means the bitwill become 1 whatever is the bit either 1 or 0.

� Algorithm of the Instruction: Carry Flag Bit → 1



Example: STC

In the given example the carry flag bit will be set that means become 1 whatever will bethe bit at this bit i.e. either 1 or 0. Let the content of carry flag bit is 0 and by executing theinstruction the bit will be 1.

9.3.10 CMP R/M

� Full form of the Instruction: Compare the content of the given register or the memorypointer with the content of register A.

� Function of the Instruction: This instruction will compare the content of register or memorypointer with the accumulator content by subtracting the content of register or memorypointer from accumulator content and the result will be stored in accumulator and therelation between the two data values will be checked by the flag register bits i.e. thecharacteristics of the result, stored in the accumulator, the characteristics or flag bits areCarry, Zero and Sign. The relations are checked by the different combinations of these flagbits for different relations as:

Relation between the Two Data Values Carry Flag Bit Zero Flag Bit Sign Flag Bit

Accumulator > Data value 0 0 0

Accumulator < Data value 1 0 1

Accumulator = Data value 0 1 0

Table 9.1: Bit Patterns for Compare Instruction



Notes� Algorithm of the Instruction: A compare R/M → A, result will be checked by thecombinations given in the Table 9.1.



Example: CMP B or CMP M

In the given examples in the first one the content of register B and register A will becompared and the result will be checked by the flag register content giving thecharacteristics of the result of subtraction. In the second example the content of the ALNdefined by the memory pointer will be compared to the register A content and the resultwill be checked by the same process.

9.3.11 CPI Data Value

� Full form of the Instruction: Compare the immediate data value given by the input devicewith the content of register A.

� Function of the Instruction: This instruction will compare the 8-bit immediate data valuewith the accumulator content by subtracting the content of register or memory pointerfrom accumulator content and the result will be stored in accumulator and the relationbetween the two data values will be checked by the flag register bits i.e. the characteristicsof the result, stored in the accumulator, the characteristics or flag bits are Carry, Zero andSign. The relations are checked by the different combinations of these flag bits for differentrelations as:

Relation between the Two Data Values Carry Flag Bit Zero Flag Bit Sign Flag Bit

Accumulator > Data value 0 0 0

Accumulator < Data value 1 0 1

Accumulator = Data value 0 1 0

� Algorithm of the Instruction: A compare data value → A, result will be checked by thecombinations given in the Table 9.2.



Example: CPI 4CH

In the given example the 8-bit immediate data value 4CH and the content of register Awill be compared and the result will be checked by the flag register content giving thecharacteristics of the result of subtraction.

9.3.12 RLC

� Full form of the Instruction: Rotate the accumulator content left without carry flag bit.

� Function of the Instruction: This instruction will rotate the accumulator content in lefthand side without the help of carry flag bit i.e. the 8 bits of the accumulator will be shifted

Table 9.2: Bit Patterns for Compare Instruction



Notes in left direction and the bit goes off will be sent to the carry flag bit and the same bit willbe transferred to the right most position of the accumulator. It is the process of rotationwhere the goes off bit will rotate to the first bit position.



Example: RLC

Let the accumulator content is 25H and its bit pattern is 00100101 and the carry flag bit ishaving 1. Then after the execution of this instruction the below mentioned path will betaken by the bits of accumulator.

00 10 0 1 0 1C1

And after the execution of the instruction the content of accumulator and carry flag bit willbe:

00 01 1 0 1 0C0

So the content of accumulator is 4AH and carry flag bit is 0 now.

9.3.1 3 RRC

� Full form of the Instruction: Rotate the accumulator content right without carry flag bit.

� Function of the Instruction: This instruction will rotate the accumulator content in righthand side without the help of carry flag bit i.e. the 8 bits of the accumulator will be shiftedin right direction and the bit goes off will be sent to the carry flag bit and the same bit willbe transferred to the left most position of the accumulator. It is the process of rotationwhere the goes off bit will rotate to the last bit position.



Example: RRC

Let the accumulator content is 3CH and its bit pattern is 00111100 and the carry flag bit ishaving 1. Then after the execution of this instruction the below mentioned path will betaken by the bits of accumulator.

1 01 01100 C1




Notes

10 00 1 1 1 0C0

So the content of accumulator is 1EH and carry flag bit is 0 now.

9.3.14 RAL

� Full form of the Instruction: Rotate the accumulator content left with carry flag bit.

� Function of the Instruction: This instruction will rotate the accumulator content in lefthand side with the help of carry flag bit i.e. the 8 bits of the accumulator will be shifted inleft direction and the bit goes off will be sent to the carry flag bit and the carry flag bit willbe transferred to the right most position of the accumulator.

Did u know? It is the process of rotation where the goes off bit will rotate to the carry flagbit and the carry flag bit will be transferred to the first bit position.



Example: RAL

Let the accumulator content is 25H and its bit pattern is 00100101 and the carry flag bit ishaving 1. Then after the execution of this instruction the below mentioned path will betaken by the bits of accumulator.

00 10 0 1 0 1C1


00 01 1 0 1 1C0

So the content of accumulator is 4BH and carry flag bit is 0 now.

9.3.15 RAR

� Full form of the Instruction: Rotate the accumulator content right with carry flag bit.

� Function of the Instruction: This instruction will rotate the accumulator content in righthand side with the help of carry flag bit i.e. the 8 bits of the accumulator will be shifted inright direction and the bit goes off will be sent to the carry flag bit and the carry flag bitwill be transferred to the left most position of the accumulator. It is the process of rotationwhere the goes off bit will rotate to the carry flag bit and the carry flag bit will betransferred to the last bit position.



Notes � Type of the Instruction: 1-byte instruction.


Example: RAR

Let the accumulator content is 3CH and its bit pattern is 00111100 and the carry flag bit ishaving 1. Then after the execution of this instruction the below mentioned path will betaken by the bits of accumulator.

1 01 01100 C1


11 00 1 1 1 0C0

So the content of accumulator is 9EH and carry flag bit is 0 now.

Task Check the functions of instructions by executing them on microprocessor kit.

Self Assessment

Fill in the blanks:

6. …………………… specifies the instructions which are used to perform logical functions ofthe microprocessor.

7. The instruction …………………… will give the compliment or invert the content of theaccumulator that means all the bits of accumulator will be converted as 0 will become 1and 1 will become 0.

9.4 Branch Group

This group specifies the instructions which are used to perform branching functions of themicroprocessor. In 8085 there is a provision for taking our control of execution from the currentlocation to any other location where a small program named as Sub-Program is stored and willbe used in the main execution, going to the new location is known as the Sub-Routine. To followthe sub-routine in any execution is known as the Branching operation. For executing thesebranching operations we have these instructions.

9.4.1 JMP ALN

� Full form of the Instruction: Jump to the specified address location number.

� Function of the Instruction: This instruction will take all the control of execution to thespecified ALN and the execution will start from the new ALN specified i.e. the jump



Notesinstruction will load the specified ALN to the program counter register and the executionwill start from the same ALN.

� Algorithm of the Instruction: ALN → Program counter



Example: JMP 302CH

In the given example the given address location number 302CH will be loaded to the PCregister and after the execution of this instruction the execution control will be transferredto the 302CH ALN.

9.4.2 Conditional JMP

� Full form of the Instruction: Jump to the specified address location number if the givencondition is true else there will be no jump function.

� Function of the Instruction: This instruction will take all the control of execution to thespecified ALN and the execution will start from the new ALN specified if the givencondition is satisfied else there will be no jump function i.e. the jump instruction will loadthe specified ALN to the program counter register and the execution will start from thesame ALN if the conditions given by the flag bits are satisfied.

� Algorithm of the Instruction: ALN → Program counter, if the condition is satisfied

No jump, if the condition is not satisfied



� Conditional Jump Instructions with their Conditions:

Opcode Full-Form Condition for Jump

JZ Jump if Zero Zero Flag = 1

JNZ Jump if not Zero Zero Flag = 0

JP Jump if Positive Sign Flag = 0

JPO Jump if Parity Odd Parity Flag = 0

JPE Jump if Parity Even Parity Flag = 1

JM Jump if Minus Sign Flag = 1

JC Jump if Carry Carry Flag = 1

JNC Jump if not Carry Carry Flag = 0

9.4.3 CALL ALN

� Full form of the Instruction: Call the specified address location number.

� Function of the Instruction: This instruction will take all the control of execution to thespecified ALN and the execution will start from the new ALN specified i.e. the callinstruction will load the specified ALN to the program counter register and the stackpointer register will be decremented by 2.

Table 9.3: Conditional Jump Instructions



Notes � Algorithm of the Instruction: ALN → Program counter

SP → SP-2



Example: CALL 302CH


9.4.4 Conditional CALL

� Full form of the Instruction: Call the specified address location number if the givencondition is true else there will be no call function.

� Function of the Instruction: This instruction will take all the control of execution to thespecified ALN and the execution will start from the new ALN specified if the givencondition is satisfied else there will be no jump function i.e. the call instruction will loadthe specified ALN to the program counter register and the SP will be decremented by 2and the execution will start from the same ALN if the conditions given by the flag bits aresatisfied.

� Algorithm of the Instruction: ALN → Program counter and SP → SP-2, if the condition issatisfied

No call, if the condition is not satisfied



� Conditional Jump Instructions with their Conditions

Opcode Full-Form Condition for Call

CZ Call if Zero Zero Flag = 1

CNZ Call if not Zero Zero Flag = 0

CP Call if Positive Sign Flag = 0

CPO Call if Parity Odd Parity Flag = 0

CPE Call if Parity Even Parity Flag = 1

CM Call if Minus Sign Flag = 1

CC Call if Carry Carry Flag = 1

CNC Call if not Carry Carry Flag = 0

9.4.5 RET ALN

� Full form of the Instruction: Return to the specified address location number.

� Function of the Instruction: This instruction will take all the control of execution to thespecified ALN and the execution will start from the new ALN specified i.e. the return

Table 9.4: Conditional Call Instructions



Notesinstruction will load the specified ALN to the program counter register and the executionwill start from the same ALN. This instruction is used to take back the program control tothe main program after the call function.

� Algorithm of the Instruction: ALN → Program counter



Example: RET 302CH


9.4.6 Conditional RET

� Full form of the Instruction: Return to the specified address location number if the givencondition is true else there will be no return function.

� Function of the Instruction: This instruction will take all the control of execution to thespecified ALN and the execution will start from the new ALN specified if the givencondition is satisfied else there will be no jump function i.e. the jump instruction will loadthe specified ALN to the program counter register and the execution will start from thesame ALN if the conditions given by the flag bits are satisfied.

� Algorithm of the Instruction: ALN → Program counter, if the condition is satisfied

No jump, if the condition is not satisfied



� Conditional Jump Instructions with their Conditions

Opcode Full-Form Condition for Return

RZ Return if Zero Zero Flag = 1

RNZ Return if not Zero Zero Flag = 0

RP Return if Positive Sign Flag = 0

RPO Return if Parity Odd Parity Flag = 0

RPE Return if Parity Even Parity Flag = 1

RM Return if Minus Sign Flag = 1

RC Return if Carry Carry Flag = 1

RNC Return if not Carry Carry Flag = 0

Self Assessment

Fill in the blanks:

8. …………………… specifies the instructions which are used to perform branching functionsof the microprocessor.

Table 9.5: Conditional Return Instructions



Notes 9. …………………… instruction Jump to the specified address location number if the givencondition is true else there will be no jump function.

10. …………………… instruction calls the specified address location number if the givencondition is true else there will be no call function.

9.5 Machine Control Group

This group specifies the instructions which are used to perform machine control functions of themicroprocessor. In 8085 the machine term is used for the whole microprocessor unit includingthe peripheral devices and this group is defined for the controlling of the whole machinesystem. For machine controlling these instructions are defined for 8085.

9.5.1 NOP

� Full form of the Instruction: No operation.

� Function of the Instruction: This instruction will stop all the functioning and executionsof the processor except the execution of the data stored in the ALN stored in PC register.



9.5.2 HLT

� Full form of the Instruction: Halt or stop the operation.

� Function of the Instruction: This instruction will halt the microprocessor system i.e. theexecution will be stopped by this instruction.



9.5.3 EI

� Full form of the Instruction: Enable the Interrupt flip-flop.

� Function of the Instruction: This instruction will enable or set the interrupt flip-flop i.e.this will enable all the maskable interrupts.



9.5.4 DI

� Full form of the Instruction: Disable the Interrupt flip-flop.

� Function of the Instruction: This instruction will disable or reset the interrupt flip-flop i.e.this will disable all the maskable interrupts.





Notes9.5.5 RIM

� Function of the Instruction: This instruction will copy the status of the interrupts and theSID pin of serial comm. Controller to the accumulator where each bit is defined for statusof different functions as the given format:

D7 D6 D5 D4 D3 D2 D1 D0

SID I7.5 I6.5 I5.5 IE M7.5 M6.5 M5.5

Here,

D0 – D2 → These bits are defined for the masking of RST 7.5, RST 6.5 and RST 5.5 interruptsfor 1 these are masked and for 0 these are unmasked or bypassed.

D3 → This bit is defined for the status of Interrupt enable flip-flop for 1 the flip-flop isenabling and for 0 it will be disabled.

D4 – D6 → These bits are defined for the status of pending RST7.5, RST6.5 and RST5.5interrupts for 1 the interrupts are active and pending for operation and for 0 the interruptsare disabled.

D7 → This bit is defined to show the status of the SID pin whether it is enable or disable for1 the pin is enable and taking input data and for 0 it is disabled.



9.5.6 SIM

� Function of the Instruction: This instruction will give the status of the masking of theinterrupts and the SOD pin of serial comm. controller given by the accumulator whereeach bit is defined for status of different functions as the given format:

D7 D6 D5 D4 D3 D2 D1 D0

SOD SDE X RST 7.5 MSE M7.5 M6.5 M5.5

Here,

D0 – D2 → These bits are defined for the masking of RST 7.5, RST 6.5 and RST 5.5 interruptsfor 1 these are masked and for 0 these are unmasked or bypassed.

D3 → This bit is defined for the mask set enable if it is 1 the Masking of different interruptsis enabled and for 0 it will be disabled.

D4 → This bit is defined for the reset conditions of the RST7.5 interrupt for 1 the interruptis reset and for 0 there will be no effect on the interrupt.

D5 → This bit is defined for don’t care condition.

D6 → This bit is defined to show the status of the SDE pin which allows the enablecondition of the serial port for 1 the serial port is enable and for 0 it is disabled.

D7 → This bit is defined to show the status of the SOD pin whether it is enable or disablefor 1 the pin is enable and giving output data and for 0 it is disabled.





Notes 9.5.7 IN 8-bit Address

� Full form of the Instruction: Input the data from the input device connected to the inputport.

� Function of the Instruction: This instruction will take data from the external devices to themicroprocessor memory for this it will copy the 8-bit port address into the accumulator asthis address is of the port from which the external device is connected which is defined by8-bit address.

� Algorithm of the Instruction: 8-bit address of port → A



Example: IN 20H

In the given example the 8-bit address 20H is giving the information of the port fromwhere the data is to be taken inside the processor.

9.5.8 OUT 8-bit Address

� Full form of the Instruction: Out the data from the processor memory to the output port.

� Function of the Instruction: This instruction will take data from the memory to the externaldevice for this it will copy the 8-bit port address into the accumulator as this address is ofthe port from which the external device is connected which is defined by 8-bit address.

� Algorithm of the Instruction: A → 8-bit address of port



Example: OUT 20H

In the given example the 8-bit address 20H is giving the information of the port where thedata is to be taken outside the processor.

9.5.9 RST n

� Full form of the Instruction: Restart the processor from the given address location.

� Function of the Instruction: This instruction will transfer the program control to thespecified memory location which is defined by the term ‘n’ in the instruction. n rangesfrom 0 to 7 and the address location number can be defined by multiplying n to 8 (nx8) inhex codes and the result will be the address location number where the program controlwill be transferred.

� Algorithm of the Instruction: n x 8 (Hex codes) → PC





NotesExample: RST 5

In the given example the n is 5 so 8 × 5 = (40)10 and in hex codes it will be 0028H so for thegiven instruction the program control will now restart from the 0028H address locationnumber.

Self Assessment

Fill in the blanks:

11. …………………… group is defined for the controlling of the whole machine system.

12. …………………… instruction will transfer the program control to the specified memorylocation which is defined by the term ‘n’ in the instruction.

9.6 Stack I/O Operations

This group specifies the instructions which are used to perform stack control functions of themicroprocessor. In 8085 the stacks are defined for a given set of data collected together for theexecution and these instructions will define the controlling of stack operations. For stackcontrolling these instructions are defined for 8085.

9.6.1 SPHL

� Full form of the Instruction: Stack pointer is loaded with the H-L pair content.

� Function of the Instruction: This instruction will load the content of H-L pair into thestack pointer register.

� Algorithm of the Instruction: H-L → SP



Example: SPHL

In the given example if the content of H-L pair is 2062H then after execution of thisinstruction the SP register will be loaded to this value and the execution will be startedfrom the 2062H ALN.

9.6.2 PUSH RP

� Full form of the Instruction: Push the content of the register pair into the stack.

� Function of the Instruction: This instruction will transfer data values of the specifiedregister pair into the stack defined by the SP register i.e. after the execution the higherorder content of the register pair will be transferred to the address location defined by theSP-1 content and the lower order data will be transferred to the address location definedby the SP-2 content in the stack that means the first and the second addresses of the stackdefined by the SP register. The register pair can be B-C, D-E, and H-L.

� Algorithm of the Instruction: Higher Byte of register pair → SP-1

Lower Byte of register pair → SP-2




Notes � Addressing Mode: Register Indirect Addressing Mode.

Example: PUSH B

In the given example the content of register B will be transferred to the SP-1 location i.e. ifthe SP content is 2010H then at 2009H and the content of register C will be transferred tothe SP-2 location i.e. 2008H location.

9.6.3 PUSH PSW

� Full form of the Instruction: Push the content of program status word into the stack.

� Function of the Instruction: This instruction will transfer data values of the programstatus word (PSW) which is register A and flag register in combined form where registerA is defined as the higher byte and flag register is defined as the lower byte into the stackdefined by the SP register i.e. after the execution the content of the register A will betransferred to the address location defined by the SP-1 content and the content of flagregister will be transferred to the address location defined by the SP-2 in the stack thatmeans the first and the second addresses of the stack defined by the SP register.

� Algorithm of the Instruction: A → SP-1

Flag Register → SP-2



Example: PUSH PSW

In the given example the content of register A will be transferred to the SP-1 location i.e.if the SP content is 2010H then at 2009H and the content of Flag register will be transferredto the SP-2 location i.e. 2008H location.

9.6.4 POP RP

� Full form of the Instruction: POP the content of the stack into the register pair.

� Function of the Instruction: This instruction will transfer data values of the specifiedaddress location defined by the stack register into the register pair i.e. after the executionthe content of SP+1 address will be transferred to the lower byte of register pair and thecontent of SP+2 address will be transferred to the higher byte of register pair. The registerpair can be B-C, D-E, H-L.

� Algorithm of the Instruction: SP + 2 → Higher Byte of register pair

SP + 1 → Lower Byte of register pair



Example: POP B

In the given example the content of SP + 2 will be transferred to the register B i.e. if the SPcontent is 2010H then from 2012H and the content of SP + 1 i.e. 2008H location will betransferred to the register C.



Notes9.6.5 POP PSW

� Full form of the Instruction: Push the content of stack into the program status word.

� Function of the Instruction: This instruction will transfer data values of stack defined bythe SP register into the program status word (PSW) which is register A and flag register incombined form where register A is defined as the higher byte and flag register is definedas the lower byte i.e. after the execution the content of the SP+2 location will be transferredto register A and the content of SP+1 location will be transferred to the flag register.

� Algorithm of the Instruction: A → SP+2

Flag Register → SP+1



Example: PUSH PSW

In the given example the content of the SP+2 location i.e. if the SP content is 2010H then at2012H will be transferred to register A and the content of the SP+1 location i.e. 2011Hlocation will be transferred to Flag register.

9.6.6 XTHL

� Full form of the Instruction: Exchange the contents of H-L pair to the ALN stored in theStack Pointer register.

� Function of the Instruction: This instruction will exchange data values of address locationnumber defined by the SP register and SP+1 address location number to the H-L registerpair i.e. after the execution of the instruction the content of the ALN stored in SP will beexchanged with the register H and the content of the ALN stored in SP+1 will be exchangedwith the register L.


H ↔ SP+1

L ↔ SP



Self Assessment

Fill in the blanks:

13. …………………… instruction will load the content of H-L pair into the stack pointerregister.

14. …………………… instruction pops the content of the stack into the register pair.


As we know that the alphanumeric codes are converted into hexadecimal codes and eachinstruction has its own unique hex coding but the length of hex codes are different depending



Notes upon the instructions. According to the length of instructions three types of instructions aredefined

� One-byte (1-byte) instruction

� Two-byte (2-byte) instruction

� Three-byte (3-byte) instruction

9.7.1 One-Byte (1-Byte) Instruction

These are the instructions which have one-byte length of hex code which includes operand andopcode both. The register addressing mode, register indirect addressing mode and implicitaddressing mode will give 1-byte instructions.

Example: MOV D, C

This instruction will have the hex code length of 1-byte length which includes the wholeinstruction.

Other examples are:

� STC

� ADD B

� ADC D

9.7.2 Two-Byte (2-Byte) Instruction

These are the instructions which have two-byte length of hex code which includes 1-byte foropcode and 1-byte for data values defined in the instruction.

!Caution The immediate addressing mode will give 2-byte instructions.

Example: MVI D, 02H

This instruction will have the hex code length of 2-byte length out of which 1-byte isdefined for MVI D and 1-byte is defined for the data value 02H.

Other examples are:

� MVI C, 8CH

� ADI 03H

� ACI 7DH

9.7.3 Three-Byte (3-Byte) Instruction

These are the instructions which have three-byte length of hex code which includes 1byte foropcode and 2-bytes for operand which is an address location number of 16-bit or 2-bytes lengthdefined in the instruction. The direct addressing mode will give 3-byte instructions.



NotesExample: MOV D, 5C00H

This instruction will have the hex code length of 3-byte length out of which first byte isdefined for MOV D, second byte is defined for the data value 5CH and third byte is definedfor data value 00H i.e. 2-bytes length is defined for the address location number 5C00Hdefined in the operand of the given example.

Other examples are:

� MOV 7CABH, H

� ADD 0300H

� ADC 007DH

Did u know? The number of bytes defined for instructions vary according to the processors.

Self Assessment

Fill in the blanks:

15. …………………… instructions which have one-byte length of hex code which includesoperand and opcode both.

16. …………………… instructions which have three-byte length of hex code which includes1byte for opcode and 2-bytes for operand.

�Case Study The History of Intel Organization

Intel began in 1968. It was founded by Gordon E. Moore who is also a physicist andchemist. He was accompanied by Robert Noyce, also a fellow physicist and co-creatorof integrated circuitry, after they both had left Fairchild Semiconductor. During the

1980’s Intel was run by a chemical engineer by the name of Andy Grove, who was the thirdmember of the original Intel family. Many other Fairchild employees participated inother Silicon Valley companies. Andy Grove today is considered to be one of the company’sessential business and strategic leaders. As the 1990’s concluded, Intel had become one ofthe largest and by far the most successful businesses in the entire world. Intel has gonethrough many faces and phases. In the beginning Intel was set apart by its ability primarilyto create memory chips or SRAM.

When the firm was founded, Gordon Moore and Robert Noyce had the idea to name theircompany Moore Noyce. However when the name is spoken it is heard as “More Noise”This idea was quickly abandoned and the pursuit of a more suitable name – one which wasnot associated with a bad interface. The name NM Electronics was shortly thereafterchosen and used for nearly a year, when the company experienced a name change toIntegrated Electronics, or INTEL for short. The rights to the name however had to bepurchased as it was already in use by a fairly well known hotel chain.

Though Intel had mastered the first microprocessor called the Intel 4004 in 1971 and alsoone of the world’s very first microcomputers in 1972, in the early 80’s the focus wasprimarily on Random Access Memory chips. A new client in the early 70’s from Japan

Contd...



Notes wanted to enlist the services of Intel to design twelve chips for their calculators. Knowingthat they did not have the manpower or the resources to complete this job effectively, TedHoff agreed to the job just the same. His idea was: What if we can design one computerchip which could function the same as twelve microchips? Hoof’s idea was completelyembraced by Moore and Noyce. If this project were successful the chip would have theability to receive command functions. This is where the 4004 model came from. After apainstaking 9 months. It measured 1/8th inch by 1/6th inch long and contained 2,300transistors. History was made and changed that day.

The Pentium Pro processor had 5.5 million transistors, making the chip so affordable thatit could be imbedded in common household appliances. After this success Intel decided tocompletely embrace this and to pursue its production. Some notable dates in the history ofIntel are:

� 1968 Robert Noyce and Gordon Moore incorporate NM Electronics

� 1970 The development of DRAM and dynamic RAM

� 1971 The world’s first microcomputer is introduced

� 1974 The first general purpose microprocessor is introduced to the world

� 1980 The Intel microprocessor is chosen by IBM for the first ever personal computer.1992 Intel’s net income tops the one billion dollar point

� 1993 The Pentium is introduced, a fifth generation chip

� 1996 Intel’s revenue exceeds twenty billion dollars and the net income surpassesfive billion dollars

� 1997, The Pentium 11 microprocessor is introduced to the world

� 1999 Intel is added to Dow Jones Averages.

� 2000 The world’s very first Intel 1 gigahertz processor hits the shelves.

To this day Intel continues to make strides in the computing and micro computing world.

Questions:

1. Name the founder of Intel Company?

2. Give the year name when Intel launches first processor.

Source: http://www.webhostingreport.com/learn/intel.html

9.8 Summary

� Data transfer group specifies the instructions which are used to transfer data from onepoint to another.

� Arithmetic Group specifies the instructions which are used to perform arithmetic functionsof the microprocessor.

� Logical group specifies the instructions which are used to perform logical functions of themicroprocessor.

� Branch group specifies the instructions which are used to perform branching functions ofthe microprocessor.

� Machine Control Group specifies the instructions which are used to perform machinecontrol functions of the microprocessor.



Notes� Stack I/O Operations group specifies the instructions which are used to perform stackcontrol functions of the microprocessor.

� One-Byte (1-byte) Instructions are the instructions which have one-byte length of hex codewhich includes operand and opcode both.

� Two-Byte (2-Byte) Instructions are the instructions which have two-byte length of hexcode which includes 1-byte for opcode and 1-byte for data values defined in the instruction.

� Three-Byte (3-Byte) Instructions are the instructions which have three-byte length of hexcode which includes 1byte for opcode and 2-bytes for operand.

9.9 Keywords

Arithmetic Group: Arithmetic Group specifies the instructions which are used to perform arithmeticfunctions of the microprocessor.

Branch Group: Branch group specifies the instructions which are used to perform branchingfunctions of the microprocessor.

Data Transfer Group: Data transfer group specifies the instructions which are used to transferdata from one point to another.

Logical Group: Logical group specifies the instructions which are used to perform logical functionsof the microprocessor.

Machine Control Group: Machine Control Group specifies the instructions which are used toperform machine control functions of the microprocessor.

One-Byte (1-byte) Instructions: One-Byte (1-byte) Instructions are the instructions which haveone-byte length of hex code which includes operand and opcode both.

Stack I/O Operations: Stack I/O Operations group specifies the instructions which are used toperform stack control functions of the microprocessor.

Three-Byte (3-Byte) Instructions: Three-Byte (3-Byte) Instructions are the instructions whichhave three-byte length of hex code which includes 1-byte for opcode and 2-bytes for operand.

Two-Byte (2-Byte) Instructions: Two-Byte (2-Byte) Instructions are the instructions which havetwo-byte length of hex code which includes 1-byte for opcode and 1-byte for data values definedin the instruction.


1. What are Data Transfer Operations? Discuss.

2. Explain the instructions specified by the data transfer group.

3. Make distinction between the instructions MOV Rd, Rs and MOV M, R.

4. Discuss the instructions specified by arithmetic group.

5. Describe the function of the instruction DAD RP with example.

6. Differentiate between arithmetic and logical group of instructions.

7. Which instruction is used instruction to rotate the accumulator content in left hand sidewithout the help of carry flag bit? Discuss.

8. Give the proper functions of IN and OUT instructions with all the specifications associatedto them.



Notes 9. Give the proper functions of PUSH, POP, SPHL and PCHL instructions with all thespecifications associated to them.

10. Describe the instructions used for executing branching operations.

11. Explain different types of instructions with example.


1. Data Transfer 2. SHLD ALN

3. XCHG 4. Arithmetic

5. DAD RP 6. Logical group

7. CMA 8. Branch group

9. Conditional JMP 10. Conditional CALL

11. Machine control 12. RST n

13. SPHL 14. POP RP

15. One byte 16 Three-Byte


Books A.P. Mathur. (1989), Introduction to Microprocessors, Tata McGraw-Hill Education

D.A. Godse. (2010), Microprocessors & Microcontrollers, Technical Publications

K. Udaya Kumar. (2008), The 8085 Microprocessor: Architecture, Programming andInterfacing, Pearson Education India

N.K. Srinath. (2005), 8085 Microprocessor: Programming and Interfacing, PHI LearningPvt. Ltd

Online links http://information.hostei.com/codes/8085-mnemonics.html

http://microprocessor-8085.blogspot.in/2009/01/introduction-to-8085-microprocessor.html

http://www.daenotes.com/electronics/digital-electronics/instruction-set-intel-8085

http://www.utem.edu.my/myweb/khairulazha/Microprocessor%20Technology/CHAPTER%206.pdf


Unit 10: Programming Techniques with Additional Instructions

NotesUnit 10: Programming Techniques withAdditional Instructions

CONTENTS

Objectives

Introduction

10.1 Looping, Counting and Indexing

10.1.1 Introduction to Counting

10.2 Additional Data Transfer Instructions

10.2.1 16-Bit Data Transfer

10.3 Additional Arithmetic Operations

10.3.1 16-Bit Addition Instructions

10.4 Advanced Logical Operations

10.4.1 Rotating Instructions

10.5 Summary

10.6 Keywords



Objectives


� Explain the concept of Looping, Counting and Indexing

� Discuss Additional Data Transfer Instructions

� Discuss Additional Arithmetic Operations

� Discuss Advanced Logical Operations

Introduction

If a computer is used for any special purpose or for sometimes, there are some applications andexecutions in which there will be a need of repetitions of some of the programs or some specialexecutions. There are two functions which can be used for such functions. These functions arelooping and recursion. For the looping, there will be the same function repeated again andagain to achieve any desired output. For recursive action, there will be any execution which iscalled by any function more than once for the desired output.

10.1 Looping, Counting and Indexing

Till now, we have checked the instructions which have been used for the simple and singleoperations which has a single execution for the desired output. But, in some cases we need tohave the same execution or function executed repeatedly for the output. It can be used for the



Notes complex calculations, transferring heavy data bits, etc. The process of making processor to haverepeating executions is known as Looping. The loops can be made by the help of some instructions(like, JUMP). Counting is also included in these types of instructions. That is, by means ofcounting we can find out the number of times the task is repeated. Also indexing allows us tokeep track of the sequential execution after the jump. According to the requirement, the loopoperation can be defined for two types:

� Continuous Loop: It is basically the loop operation in which the loop operation is donecontinuously till the desired output. It is set-up by the unconditional jump instructions.After starting a continuous loop, the execution will not stop till the system is reset or off,as there are no conditions defined for the given loop. The unconditional or continuousloop can have the logical or flow chart as given in the Figure 10.1.

Start

PerformTask

Go backand

Repeat

Did u know? Continuous loop is also known as unconditional loop.

� Conditional Loop: It is basically the loop operation in which the loop operation is doneaccording to the conditions given to the processor. The conditions are defined by the useof conditional jump instructions and the conditions given to the processor will be definedby the conditions or statuses of the flag register bits or flag bits. Counting and indexingare included in this loop.

As we know that the conditional jumps are defined by the flag bits, the conditional loopswill also be defined by the flag bits.

Notes These loops will check the conditions first and the looping process will be startedwhen the condition is satisfied and repeat the executions till the conditions are defined.

Example: This conditional loop operation can be defined by an example of car racing, inwhich, the cars have to go again and again till the distance or number of laps are not completedand this can be shown by the given flow diagram in Figure 10.2.

Figure 10.1: Flowchart of Continuous Loop



Notes

no

yes

Start

Perform Task for 50 laps

Go for the race

Are 50 lapscompleted?

Stop

Task Give a program for the continuous looping process, to define the process clearly.

10.1.1 Introduction to Counting

The counting function is a special application of conditional loops; the counting operation isdone for the counting of the operations which is going on for the repetitions in the loopingprocess. This can be easily understood by the help of a flow chart given in the Figure 10.3.

Set the counter for the desired number of operations

Task performed and counter reduced by one

Is the counterzero?

no

yes

Start

Stop

Figure 10.2: Flowchart of Conditional Loop

Figure 10.3: Flowchart of Counting



Notes Self Assessment

Fill in the blanks:

1. The process of making processor to have repeating executions is known as…………………….

2. By means of …………………… we can find out the number of times the task is repeated.

3. …………………… allows us to keep track of the sequential execution after the jump.

4. …………………… is basically the loop operation in which the loop operation is donecontinuously till the desired output.

5. Continuous loop is also known as …………………….

6. …………………… is basically the loop operation in which the loop operation is doneaccording to the conditions given to the processor.

7. Conditional jumps are defined by the ……………………

10.2 Additional Data Transfer Instructions

Additional Data Transfer Instructions are discussed below:

10.2.1 16-Bit Data Transfer

� LHLD 16 Bit Address

This instruction is used to copy the contents of the memory location pointed out by the 16-bit address into register L and copies the contents of the next memory location intoregister H. The contents of source memory locations are not altered.

Example:

LHLD C050

It loads data from C050 memory location to Register L and loads data from C051 memorylocation to Register H.

� SHLD 16 Bit Address

The register L contents are stored into the memory location specified by the 16-bit addressin the operand and the contents of H register are stored into the next memory location byincrementing the operand. This is a 3-byte instruction, the second byte specifies the low-order address and the third byte defines the high-order address.

Example:

SHLD C050

It stores the Register L data to memory location C050 and stores Register H data tomemory location C051.

!Caution The contents of registers HL are not altered.



Notes� XCHG: This instruction exchanges the content of HL and DE Register Pair

Source: http://www.aust.edu/cse/moinul/mp_d2.pdf

Did u know? The contents of register H are exchanged with the contents of register D, andthe contents of register L are exchanged with the contents of register E.

Example: Memory Location 2050H and 2051H contains 3FH and 47H respectively.Register pair DE comprises 856FH. Write assembly code to exchange the content of DE with thecontent of the memory locations

Solution:

LHLD 2050

XCHG

SHLD 2050

Self Assessment

Fill in the blanks:

8. The instruction …………………… copies the contents of the memory location pointed outby the 16-bit address into register L and copies the contents of the next memory locationinto register H.

9. The instruction …………………… exchanges the content of HL and DE Register Pair.

10.3 Additional Arithmetic Operations

Additional arithmetic operations are discussed below:

10.3.1 16-Bit Addition Instructions

DAD Rp: This instruction adds the content of the HL register with the content of the Register pairspecified by Rp and stores the result in the HL register pair

The contents of the source register pair are not altered. If the result is larger than 16 bits, the CYflag is set. No other flags are affected.

Example: DAD B

It adds the content of the HL register with the content of the BC register pair stores theresult in the HL register pair.

HL HL+BC

Figure 10.4: Exchanging the Content of HL and DE Register Pair



Notes

DAD B will result in

DAD B does the following:

Self Assessment

Fill in the blanks:

10. The instruction …………………… adds the content of the HL register with the content ofthe Register pair specified by Rp and stores the result in the HL register pair.

11. In case of DAD RP instruction, the contents of the source …………………… are not altered.

10.4 Advanced Logical Operations

Advanced logical operations include rotating instructions which are discussed as below:

10.4.1 Rotating Instructions

� RLC

� RRC

� RAL

� RAR

RLC (Rotate Accumulator Left)

RLC is an instruction in which every bit of the Accumulator is shifted one bit left and the MSB bitof the Accumulator is copied into the Carry flag and into the A0th bit.


After the RLC instruction is executed, the content of the Accumulator and the carry flag will be:

Figure 10.5: RLC



Notes


Notes Bit A7 is placed in the position of A0 as well as in the Carry flag. CY is modifiedaccording to bit A7.

RRC (Rotate Accumulator Right)

RRC is an instruction in which every bit of the Accumulator is shifted one bit Right and the LSBbit of the Accumulator is copied into the Carry flag and into the A7th bit.


After the RRC instruction is executed, the content of the Accumulator and the carry flag will be:


RAL (Rotate Accumulator Left through Carry)

RAL is an instruction in which every bit of the Accumulator is shifted one bit left and the MSB bitof the Accumulator is copied into the Carry flag and the Carry flag value is copied into the A0thbit.

Figure 10.6: Content of the Accumulator and the Carry Flag after theExecution of RLC Instruction

Figure 10.7: RRC

Figure 10.8: Content of the Accumulator and the Carry Flag after theExecution of RRC Instruction



Notes


After the RAL instruction is executed, the content of the Accumulator and the carry flag will be:


RAR (Rotate Accumulator Right through Carry)

RAR is an instruction in which every bit of the Accumulator is shifted one bit Right and the LSBbit of the Accumulator is copied into the Carry flag and the Carry flag value is copied into theA7th bit.


After the RAR instruction is executed, the content of the Accumulator and the carry flag will be:


Figure 10.9: RAL

Figure 10.10: Content of the Accumulator and the Carry Flag after theExecution of RAL Instruction

Figure 10.11: RAR

Figure 10.12: Content of the Accumulator and the Carry Flag after theExecution of RAR Instruction



Notes

Task Compare and contrast RAL and RAR.

Self Assessment

Fill in the blanks:

12. …………………… is an instruction in which every bit of the Accumulator is shifted one bitleft and the MSB bit of the Accumulator is copied into the Carry flag and into the A0th bit.

13. …………………… is an instruction in which every bit of the Accumulator is shifted one bitRight and the LSB bit of the Accumulator is copied into the Carry flag and into the A7th bit.

14. …………………… is an instruction in which every bit of the Accumulator is shifted one bitleft and the MSB bit of the Accumulator is copied into the Carry flag and the Carry flagvalue is copied into the A0th bit.

15. …………………… is an instruction in which every bit of the Accumulator is shifted one bitRight and the LSB bit of the Accumulator is copied into the Carry flag and the Carry flagvalue is copied into the A7th bit.

�Case Study Human-Computer Interaction (HCI)

Human-computer interaction (HCI) is an area of research and practice that emergedin the early 1980s, initially as a specialty area in computer science. HCI hasexpanded rapidly and steadily for three decades, attracting professionals from

many other disciplines and incorporating diverse concepts and approaches. To aconsiderable extent, HCI now aggregates a collection of semi-distinct fields of researchand practice in human centred informatics. However, the continuing synthesis of disparateconceptions and approaches to science and practice in HCI has produced a dramatic exampleof how different epistemologies and paradigms can be reconciled and integrated.

Until the late 1970s, the only humans who interacted with computers were informationtechnology professionals and dedicated hobbyists. This changed disruptively with theemergence of personal computing around 1980. Personal computing, including bothpersonal software (productivity applications, such as text editors and spreadsheets, andinteractive computer games) and personal computer platforms (operating systems,programming languages, and hardware), made everyone in the developed world apotential computer user, and vividly highlighted the deficiencies of computers with respectto usability for those who wanted to use computers as tools.

The challenge of personal computing became manifest at an opportune time. The broadproject of cognitive science, which incorporated cognitive psychology, artificial intelligence,linguistics, cognitive anthropology, and the philosophy of mind, had formed at the end ofthe 1970s. Part of the programme of cognitive science was to articulate systematic andscientifically-informed applications to be known as “cognitive engineering”. Thus, at justthe point when personal computing presented the practical need for HCI, cognitive sciencepresented people, concepts, skills, and a vision for addressing such needs. HCI was one ofthe first examples of cognitive engineering.

Contd...



Notes Other historically fortuitous developments contributed to establishment of HCI. Softwareengineering, mired in unmanageable software complexity in the 1970s, was starting tofocus on non-functional requirements, including usability and maintainability, and onnon-linear software development processes that relied heavily on testing. Computergraphics and information retrieval had emerged in the 1970s, and rapidly came to recognizethat interactive systems were the key to progressing beyond early achievements. Allthese threads of development in computer science pointed to the same conclusion: Theway forward for Notes computing entailed understanding and better empowering users.

Finally human factors engineering, which had developed many techniques for empiricalanalysis of human-system interactions in so-called control domains such as aviation andmanufacturing, came to see HCI as a valuable and challenging domain in which humanoperators regularly exerted greater problem-solving discretion. These forces of need andopportunity converged around 1980, focusing a huge burst of human energy, and creatinga highly visible interdisciplinary project.

From Cabal to Community

The original and abiding technical focus of HCI is on the concept of usability. This conceptwas originally articulated naively in the slogan “easy to learn, easy to use”. The bluntsimplicity of this conceptualization gave HCI an edgy and prominent identity in computing.It served to hold the field together, and to help it influence computer science and technologydevelopment more broadly and effectively. However, inside HCI the concept of usabilityhas been reconstructed continually, and has become increasingly rich and intriguinglyproblematic.

Usability now often subsumes qualities like fun, well-being, collective efficacy, aesthetictension, enhanced creativity, support for human development, and many others. A moredynamic view of usability is that of a programmatic objective that should continue todevelop as our ability to reach further toward it improves.

Although the original academic home for HCI was computer science, and its originalfocus was on personal productivity applications, mainly text editing and spreadsheets, thefield has constantly diversified and outgrown all boundaries. It quickly expanded toencompass visualization, information systems, collaborative systems, the systemdevelopment process, and many areas of design. HCI is taught now in many departments/faculties that address information technology, including psychology, design,communication studies, cognitive science, information science, science and technologystudies, geographical sciences, management information systems, and industrial,manufacturing, and systems engineering. HCI research and practice draws upon andintegrates all of these perspectives.

A result of this growth is that HCI is now less singularly focused with respect to coreconcepts and methods, problem areas and assumptions about infrastructures, applications,and types of users. Indeed, it no longer makes sense to regard HCI as a specialty ofcomputer science; HCI has grown to be broader, larger and much more diverse thancomputer science. It expanded from individual and generic user behaviour to includesocial and organizational computing, creativity, and accessibility for the elderly, thecognitively impaired, and for all people. It expanded from desktop office applications toinclude games, e-learning, e-commerce, military systems, and process control. It expandedfrom early graphical user interfaces to include myriad interaction techniques and devices,multi-modal interactions, and host of emerging ubiquitous, handheld and context-awareinteractions.

There is no unified concept of an HCI professional. In the 1980s, people often contrasts thecognitive science side of HCI with the software tools and user interface side of HCI.

Contd...



NotesThe HCI landscape is far more differentiated and complex now. HCI academic programstrain many different types of professionals now: user experience designers, interactiondesigners, user interface designers, application designers, usability engineers, user interfacedevelopers, application developers, technical communicators/online informationdesigners, and more.

And indeed, many of the sub-communities of HCI are themselves quite diverse. Forexample, ubiquitous computing (aka ubicomp) is subarea of HCI, but it is also asuperordinate area integrating several mutually diverse subareas (e.g., mobile computing,geo-spatial information systems, in-vehicle systems, community informatics, distributedsystems, handhelds, wearable devices, ambient intelligence, sensor networks, andspecialized views of usability evaluation, programming tools and techniques, applicationinfrastructures, etc.). The relationship between ubiquitous computing and HCI is becomingparadigmatic: HCI is the name for a community of communities.

In the early 1980s, HCI was a small and focused specialty area. It was a cabal trying toestablish what a heretical view of computing was then. Today, largely due to the successof that endeavour, HCI is a vast and multifaceted community, loosely bound by theevolving concept of usability, and the integrating commitment to value human concernsas the primary consideration in creating interactive systems.

Questions:

1. Describe brief about Human-computer interaction (HCI).

2. What are the concepts of usability of Human-computer interaction (HCI)?

Source: http://www.interaction-design.org/encyclopedia/human_computer_interaction_hci.html#heading_SIGGROUP_-_Conference_on_Supporting_Group_Work_html_pages_35313

10.5 Summary

� The process of making processor to have repeating executions is known as Looping.

� By means of counting, we can find out the number of times the task is repeated.

� Indexing allows us to keep track of the sequential execution after the jump.

� Continuous Loop is basically the loop operation in which the loop operation is donecontinuously till the desired output.

� Conditional Loop is basically the loop operation in which the loop operation is doneaccording to the conditions given to the processor.

� The counting function is a special application of conditional loops; the counting operationis done for the counting of the operations which is going on for the repetitions in thelooping process.

� Instruction DAD Rp adds the content of the HL register with the content of the Registerpair specified by Rp and stores the result in the HL register pair.

� Advanced logical operations consist of rotating instructions such as RLC, RRC, RAL, andsRAR.

10.6 Keywords

Conditional Loop: Conditional Loop is basically the loop operation in which the loop operationis done according to the conditions given to the processor.



Notes Continuous Loop: Continuous Loop is basically the loop operation in which the loop operationis done continuously till the desired output.

Counting: By means of counting, we can find out the number of times the task is repeated.

Indexing: Indexing is a process; which allows us to keep track of the sequential execution afterthe jump.

Looping: The process of making processor to have repeating executions is known as Looping.

RAL: It is an instruction in which every bit of the Accumulator is shifted one bit left and the MSBbit of the Accumulator is copied into the Carry flag and the Carry flag value is copied into theA0th bit.

RLC: It is an instruction in which every bit of the Accumulator is shifted one bit left and the MSBbit of the Accumulator is copied into the Carry flag and into the A0th bit.

RRC: It is an instruction in which every bit of the Accumulator is shifted one bit Right and theLSB bit of the Accumulator is copied into the Carry flag and into the A7th bit.


1. What do you mean by the programming techniques and how they are useful for theprocessor executions?

2. Explain the concept of looping and recursive processes.

3. Discuss looping and its different types of operations.

4. What is a conditional loop? Illustrate it with an example.

5. After starting a continuous loop, the execution will not stop till the system is reset or off.Comment.

6. Explain the concept of counting process with example.

7. Make distinction between counting and indexing.

8. Illustrate the use of counting function in conditional loops.

9. Explain the function of LHLD and SHLD instructions with example.

10. Describe the execution of RLC and RRC instruction.


1. Looping 2. Counting

3. Indexing 4. Continuous Loop

5. unconditional loop. 6. Conditional Loop

7. flag bits 8. LHLD

9. XCHG 10. DAD Rp

11. register pair 12. RLC

13. RRC 14. RAL

15. RAR



Notes10.8 Further Readings





Online links http://194.81.104.27/~brian/microprocessor/Rotate.pdf

http://engeletrica.sobral.ufc.br/professores/marcelo/Micro/8085_is_details.pdf

http://www.niceindia.com/qbank/xcs_234_microprocessors.pdf



Notes Unit 11: Counters and Time Delays

CONTENTS

Objectives

Introduction

11.1 Program Counter

11.2 Time Delays

11.2.1 Time Delay Using a Register Pair

11.2.2 Time Delay by Loop in a Loop

11.3 Illustrative Program: Hexadecimal Counter

11.4 Summary

11.5 Keywords



Objectives


� Explain the concept of Counters

� Discuss Time-Delays

� Discuss the concept of Hexadecimal Counter

Introduction

The counter is basically a device by which the counting operation is done. A program counter isdefined as a register in a computer processor that includes the address (location) of the instructionbeing executed at the current time. In the programming, this operation can be done by the use ofa register loaded with any data value and this can be incremented or decremented by the use ofinstructions to make the counting process. As every instruction gets fetched, the stored value isincreased by 1. After each instruction is fetched, the program counter points to the next instructionin the sequence. When the computer restarts or is reset, the program counter normally reverts to0. The counting can be done by the use of loops.

11.1 Program Counter

Program counter is also known as an instruction address register, PC, or instruction pointer. Aprogram counter is defined as a type of register found in CPU of a computer system. Theobjective of the counter is to offer the temporary housing for the next instruction that is to beexecuted in a string of instructions. As one instruction is retrieved and implemented, the programcounter queues up the next instruction in the string, effectually minimising delays in the executionof steps required to finish a task. By always pointing at the next instruction, the process is keptmoving forward in an efficient manner.


Unit 11: Counters and Time Delays

NotesWhile there are differences, the operation of a program counter inside the CPU (central processingunit) is quite straightforward. When a new task is ordered, the instructions required to managethat task is retrieved from the memory. This is usually carried out by the CPU creating anaddress that is then sent to the memory, which responds by sending the instructions back to theunit as data through a data bus.

The program counter, as one of numerous different registers built into the CPU, performs thetask of receiving every instruction in task sequence. Maintaining the logical sequence simplifiesthe forward progression to every step, eventually completing the task.

Notes This logical progression is maintained by pointing to the data that is to be usednext even as the previous data is in use, and then quickly pointing to the next data in thesequence as every instruction is executed in turn.

Depending on the program counter configuration, the register may actually serve as the pointerfor more than one instruction involved with a specified process presently under execution. Withsome register designs, the program counter not only points toward the process that is next in thesequence, but also toward the just released instruction that is now in the process of beingimplemented. This particular design is considered to aid in keeping track of the balance ofresources and helping to defend the forward movement of the instructions with a higher levelof efficiency.

The function of a program counter is necessary to the successful execution of the instructionsincluded in any task. By pointing the way toward every instruction in the sequence, the counterassists i providing a logical execution of those steps that eventually lead to completing the taskrapidly and proficiently. Without the use of this type of register, the potential for the sequenceto be disrupted would be improved, and the chances for finishing the task would be quite few.

Notes By adding organisation to the incremental step by step completion of everyinstruction, the program counter serves as the channel that minimises anomalies andkeeps the process moving forward properly.

Program counter contains the address of either the first byte of the next instruction to be fetchedfor execution or the address of the next byte of instruction which has been totally fetched. In boththe cases it gets incremented automatically one after another as the instruction byte gets fetched.

Did u know? Program register holds the address of next instruction.

Self Assessment


1. A program counter is a type of register that is found in the central processing unit (CPU)of a computer system.

2. When a new task is ordered, the instructions necessary to manage that task retrieved fromthe memory.



Notes 3. Program register does not keep the address of next instruction.

4. As one instruction is retrieved and implemented, the program counter queues up the nextinstruction in the string.

11.2 Time Delays

The time delay is a specific type of counting operation in which, the registers are loaded with thegiven data value and will be decremented one by one. This decrement is done by the conditionaljump instructions and the loops defined by these jump instructions. The time delays are definedby the time utilized by the processor to make the given executions which will be defined in thegiven loops.

Example: A program is given here,

MVI B, FF H

LOOP: DCR B

JNZ LOOP

HLT

In this program, the register B will be decremented to zero from FF value till then the loopwill get executed again and again and for this time there will be a time delay in theexecutions and the processor.

11.2.1 Time Delay Using a Register Pair

Time delays can be generated by the use of data values defined and decremented.

If the data value is less the delay will be less and if the data value is high the delay will be more,so now we are going to use the register pair which will have 16-bit data value instead of 8-bitdata of single register.

!Caution For the register pairs we need the 16-bit instructions for the loops and furthertime delays.

Example:

LXI B, FF H

LOOP: DCX B

JNZ LOOP

HLT

11.2.2 Time Delay by Loop in a Loop

For the higher time delay now the loops defined within a loop will be used for the executions.

Did u know? The time delays are basically increased by the high data values defined forthe executions.



NotesExample:

MVI B, 44 H

LOOP2: MVI C, FF H

LOOP1: DCR C

JNZ LOOP1

DCR B

JNZ LOOP2

HLT

Example: Let us write an assembly language program to generate time delay and executethe program using 8085 microprocessor kit.

Apparatus Required: 8085 microprocessor kit, power supply.

Algorithm:

Step1: Move the outer loop count to the C register.

Step 2: Load the inner loop count to DE register pair.

Step 3: Decrement DE reg pair content.

Step 4: Check whether DE register pair content is 0, if not go to step 3.

Step 5: Decrement C register.

Step 6: If C register content is not 0, go to step 2.

Calculation:

DCX D —6T

MOV A, E—4T

ORA D —4T

JNZ loop—10T

=24T

24 × N × 0.33 × 10-6 = 0.5

N = 63132

= (F69C)H

For delay of 10 s loop is called 20 times.

(20)10 = 14H

Program:

Memory Location Machine Code Label Mnemonics Comments

4100 0E,14 MVI C,14 Initialize outer loop count

4102 11,9C,F6 Loop 1 LXI D,F69C Initialize inner loop count

Contd...



Notes 4105 1B Loop DCX D Decrement inner loop count

4106 7B MOV A,E Move the contents of E register to accumulator

4107 B2 ORA D Check whether DE register pair contents are zero.

4108 C2,05,41 JNZ Loop If [DE] not zero go to loop

410B 0D DCR C Decrement outer loop count

410C C2,02,41 JNZ Loop1 If [C]not zero go to loop1

410F C7 RST Reset

Thus the time delay of 10 seconds has been generated using microprocessor 8085 kit andthe output has been verified.

Task Illustrate the different ways of using time-delay with example.

Self Assessment

Fill in the blanks:

5. The …………………… is a specific type of counting operation in which, the registers areloaded with the given data value and will be decremented one by one.

6. Time delays can be generated by the use of …………………… defined and decremented.

7. If the data value is less the delay will be …………………….

8. The time delays are basically …………………… by the high data values defined for theexecutions.

11.3 Illustrative Program: Hexadecimal Counter

A hex counter is basically a counter used for the counting of operations by the use of hex codes.Hex codes can count from 00H to FFH.

This designing can be easily understood by the use of given program.

MVI B, 00 H

LOOP1: DCR B

MVI C, FFH (or any hex number to be counted)

LOOP2: DCR C

INZ LOOP2

MOV A, B

JMP LOOP1

HLT

Example: Write an assembly language program to realize a hexadecimal counter andexecute the program using 8085 microprocessor kit.



NotesApparatus required: 8085 microprocessor kit, power supply.

Algorithm:

Step 1: Initialize L register with 00.

Step 2: Store the contents of ‘L’register in 4200.

Step 3: Call monitor program to display L register in data field.

Step 4: Call delay program to give a delay of two sec.

Step 5: Copy the contents of 4200 to L register through A

Step 6: Increment contents of Lregister and go to step 2.

Subroutine:

Step1: Move the outer loop count to the C register.

Step 2: Load the inner loop count to DE register pair.

Step 3: Decrement DE reg pair content.

Step 4: Check whether DE register pair content is 0, if not go to step 3.

Step 5: Decrement C register.

Step 6: If C register content is not 0, go to step 2.

Calculation:

DCX D —6T

MOV A,E—4T

ORA D —4T

JNZ loop—10T

=24T

24 × N × 0.33 × 10-6 = 0.5

N = 63132

= (F69C)H

For delay of 2 s loop is called 4 times.

(4)10 = 4H


4300 2E,00 MVI L,00 Initialize L register with 00

4302 7D Loop 1 MOV A,L Move the contents of L register to accumulator.

4303 32,00,42 STA 4200 Store the accumulator contents to 4200

4306 3E,0B MVI A,0B Initialize accumulator with 0B

4308 0E,02 MVI C,02 Initialize C register with 02

Contd...



Notes 430A CD,05,00 CALL 0005 Call monitor program to display L register contents

430D CD,00,41 CALL delay Call delay program

4310 3A,00,42 LDA 4200 Load accumulator with 4200 contents

4313 6F MOV L,A Move accumulator to L register contents

4314 2C INR L Increment L register contents

4315 C3,02,43 JMP Loop Jump to loop

Subroutine:


4100 0E,04 MVI C,04 Initialize outer loop count

4102 11,9C,F6 Loop 1 LXI D,F69C Initialize inner loop count

4105 1B Loop DCX D Decrement inner loop count

4106 7B MOV A,E Move the contents of E register to accumulator

4107 B2 ORA D Check whether DE register pair contents are zero.

4108 C2,05,41 JNZ Loop If [DE] not zero go to loop

410B 0D DCR C Decrement outer loop count

410C C2,02,41 JNZ Loop1 If [C]not zero go to loop1

410F C9 RET Return to main program

Thus the hexadecimal counter has been realized using 8085 microprocessor kit and theresult has been verified.

Task Make a counter for decimal counting.

Self Assessment

Fill in the blanks:

9. A …………………… is basically a counter used for the counting of operations by the use ofhex codes.

10. Hex …………………… can count from 00H to FFH.

�Case Study Performance Analysis and Monitoring Using

Hardware Counters

The UltraSPARC and Pentium microprocessors contain hardware performancecounters that allow counting a series of processor events, such as cache misses,pipeline stalls and floating-point operations. Statistics of processor events can be

Contd...



Notescollected in hardware with little or no overhead, making these counters a powerful meansto monitor an application and analyse its performance. Such counters, to their advantage,are non-intrusive, do not to require recompilation of applications and are available inevery UltraSPARC-based system that Sun Microsystems currently ships. Nonetheless,these counters are not widely used beyond hardware specialists because of the lack ofprogramming interfaces and sparse documentation.

Starting with release 8 of the Solaris OE, there is an increasing support of hardwarecounters, with the availability of utility tools and public programming interfaces. Thissupport for hardware counters at the operating system level is a major milestone for theSolaris software developer community but is not a direct answer to its needs. Applicationprogrammers work at a higher level where the common metrics are a combination of thelow-level event counts accumulated in hardware. There is a need for higher-level toolsthat hide the complexity of the underlying hardware design and present in a uniformmanner the common metrics the programmers expect: million instructions per second(MIPS), floating-point operations per second (FLOPS), cache miss rate.

In this study, the Solaris 8 platform’s support for hardware performance counters is covered,and a tool, the Hardware Activity Reporter that builds on the new Solaris interfaces andaims to address the needs of application programmers is introduced.

Solaris 8 OE Support for Hardware Performance Counters

In February 2000, Sun Microsystems announced a new release of the Solaris OperatingEnvironment, Solaris 8. With the latest release of Solaris 8 OE, Sun began to deliver publicinterfaces to the UltraSPARC and Pentium hardware performance counters. A series ofapplication programming interfaces (APIs) have been made available as shared libraries,to program various hardware counters and the utility tools cpustat and cputrack to accessthe microprocessor (CPU) hardware counters from the command line. The Solaris 8 platformalso provides similar libraries and tools to access the hardware counters of the system busand I/O boards.

Solaris 8 OE Libraries

Solaris 8 software ships with two libraries directly related to the usage of the CPUperformance counters: libcpc, to access CPU counters and libpctx, to track a process. Usingthese APIs, one can instrument code to access the performance hardware counters andcollect performance information. The steps to instrument a piece of code are:

1. Check the versions and accessibility of the hardware performance counters withcpc_version() and cpc_access();

2. Initialize a cpc_event_t data structure, using cpc_getcpuver() and cpc_strtoevent(),to be used in conjunction with the counters;

3. Bind the data structure to the CPU using cpc_bind_event();

4. Read the counters, as desired, using cpc_take_sample(); Notes

5. Release the CPU using cpc_rele() when finished.

The attractive aspect of these interfaces is their simplicity. Once the counters are initialized,a program reads them by a single call to cpc_take_sample(). No matter how easy-to-usethese APIs are, however, people are usually reluctant to instrument code. To avoidincrementing code, Solaris 8 software also ships with a couple of command-line basedutilities, cpustat and cputrack, that report on CPU performance counters.

Solaris 8 OE Utility Tools

The cpustat utility reports on CPU performance counters in a system-wide fashion. cpustatis invoked from the command line, and a pair of processor events to monitor must be

Contd...



Notes passed as an argument. Events go by pair because the current UltraSPARC and Pentiummicroprocessors have two hardware performance counters that must be programmedsimultaneously. Optional arguments are the sampling interval and count, i.e., the frequencyat which the counters are read and the number of times the counters are read. Multiplepairs of events can be specified; in that case, the system alternates between the multiplepairs. Because cpustat is a systemwide utility, it must be run as root.

Questions:

1. Discuss UltraSPARC and Pentium microprocessors.

2. Differentiate between MIPS and FLOPS.

Source: http://fineit.net/tools/opt/har_1.5/article.html

11.4 Summary

� A program counter is a type of register that is found in the central processing unit (CPU)of a computer system.

� Counters are used to count the number of executions in any looping process.

� The function of a program counter is essential to the successful execution of the instructionsinvolved in any task.

� Time delays are basically the time taken by the processor to execute the programs givento it.

� The time delay is a specific type of counting operation in which, the registers are loadedwith the given data value and will be decremented one by one.

� For the register pairs we need the 16-bit instructions for the loops and further time delays.

� The time delays are basically increased by the high data values defined for the executions.

� A hex counter is basically a counter used for the counting of operations by the use of hexcodes which can count from 00H to FFH.

11.5 Keywords

Counter: A program counter is a type of register that is found in the central processing unit(CPU) of a computer system.

Hex Counter: A hex counter is basically a counter used for the counting of operations by the useof hex codes which can count from 00H to FFH.

Time Delays: Time delays are basically the time taken by the processor to execute the programsgiven to it.


1. What is a program counter? Discuss the concept.

2. Describe the functions of program counter.

3. Explain the concept of time delay with example.

4. Define the time delays generated by different types.

5. Explain the use of jump instructions in time delay.



Notes6. Explain how to generate time delay using a register pair.

7. For the higher time delay now the loops defined within a loop will be used for theexecutions. Comment.

8. What is a Hexadecimal Counter? Illustrate the concept with example.

9. Discuss the steps used for generating time delay and executing the program using 8085microprocessor kit.


1. True 2. True

3. False 4. True

5. time delay 6. data values

7. less 8. Increased

9. hex counter 10. codes






Online links http://www.gecassets.co.in/8085%20Microprocessor%20-%20Ramesh%20Gaonkar.pdf

http://www.iitg.ernet.in/asahu/cs421/Lects/Lec04.pdf

http://www.nptel.iitm.ac.in/courses/Webcourse-contents/IISc-BANG/Microprocessors%20and%20Microcontrollers/pdf/Lecture_Notes/LNm1.pdf



Notes Unit 12: Stacks

CONTENTS

Objectives

Introduction

12.1 Concept of Stack

12.1.1 Stack Pointer

12.1.2 Stack Register

12.2 PUSH & POP

12.2.1 Stack Instruction

12.2.2 PSW Register Pair

12.3 Summary

12.4 Keywords



Objectives


� Explain the concept of Stack

� Discuss Stack Pointer

� Discuss Stack Register

� Explain PUSH & POP instructions

Introduction

Stack is one of the most significant things we must know when programming. We can considerthe stack as a deck of cards. When we put a card on the deck, it will be the top card. Then we putanother card, and soon. When we remove the cards, we remove them backwards, the last cardfirst and so on. The stack functions in the similar way; we put (push) words on the stack. Then, weremove (pop) them backwards. This is known as Last In First Out (LIFO). Most microprocessorsmake use of a stack-based architecture. When a function is called, the return address and argumentsof a function are pushed onto a stack and when that function terminates; those values areremoved (popped off) from the stack. These operations of stack are built into microprocessors.

12.1 Concept of Stack

Stack is considered as a group of memory locations in the Read/Write memory. Stack is utilisedfor binary information storage during program execution. The stack is defined a memory areawhich is used for the temporary storage of information. In 8085 microprocessor, stack is consideredas a set of memory location in the read/write memory which is specified in the main programby the programmer. Those memory locations are utilised to store binary information temporarilyduring the program execution.


Unit 12: Stacks

NotesThe stack is considered as an area in the memory, where data is pushed in and popped outwhenever needed. It includes data that has to be stored on a temporary basis and which isrequired to be accessed in the near future.

Let us suppose that we have a subprogram inside a program. Both the parent as well as childprograms require registers. By registers, we mean every general purpose register and the segmentregister. Initially, the registers are used by the parent for some calculations. Now, when thesubprogram is called, the registers are over written whenever a new calculation is done. Then,some registers hold the values of the parent program and the other registers hold values of thechild program or hold corrupt values.

This problem always takes place on the existence of a sub-program. Thus, we use stack datastructure in order to overcome this problem. When a sub-program is called, the caller pushesevery essential data into the stack, saves its state and then the called (sub program) takes over.

Notes When the sub-program is completed, the parent program loads its state and popsthe data out of the stack and resumes operation.

Source: http://imbhargav.wordpress.com/category/professional/microprocessors/

12.1.1 Stack Pointer

As we know, a stack is an array of registers which is organized in a LIFO manner. Stack signifiesa set of memory location in R/W memory and pointer signifies a pointing something.Alternatively, stack pointer signifies a 16-bit register which point the stack’s R/W memorylocation. The element’s top is always showed by a special purpose register known as stackpointer (SP).

!Caution The size of the stack pointer is equal to the length of the address.

The stack pointer (SP) is a register within the µP that includes the address of the next locationavailable for the stack.

The internal logic of µP causes the SP to decrease automatically when data is stored in the stackand to automatically increment when it is removed. Thus, the SP must firstly be set to thehighest address in the stack area.

Example: If the stack is to occupy locations $0200 to $02FF then make use of LDS #$02FFinstruction as initialization before making use of the stack.

Figure 12.1: Stack



Notes SP instructions are:

� DES SP - 1 → SP

� INS SP + 1 → SP

� LDS M:M + 1 → SP (in immediate, direct, extended and indexed modes)

� STS SP → M:M + 1 (in direct, extended and indexed modes)

� TXS IX - 1 → SP

� TSX SP + 1 → IX

� TYS IY - 1 → SP

� TSY SP + 1 → IY

We define the beginning of the stack in the program by using the following instruction:

LXI SP

This instruction is used to load a 16 bit memory address in the microprocessor’s stack pointerregister (SP). After defining the SP, storing of data bytes starts at the memory address that is oneless than the address in the SP. The information is stored in reversed numerical order.

Data bytes in the microprocessor’s register pair can be stored in the stack in reversed order bymaking use of the instruction, RSH. By using the POP instruction, data bytes can be transferredfrom the stack to representative register. As two data bytes are being stored at a time, the 16 bitmemory address in the SP is decremented by 2. On the retrieval of data types, the address isincremented by 2.

The stack is initialized at the highest available memory location in order to prevent the programfrom being removed by the stack information.

Example: If we stored memory address 2050H in stack pointer with LXI SP 2050Hinstruction then storing of data bytes start at 2049H and continue reverse numerical order thatmeans decreasing memory address in Stack.

Did u know? It is required to define highest available memory for beginning stack pointerto overcome conflict with main program address.

12.1.2 Stack Register

In terms of computers, a stack register is a memory location (generally on the CPU or relatedprocessing hardware) that holds the current address of the top of a region of separate computermemory known as the stack. The stack register is significant because absence of it will requirecomputer to implement a slower, more error-prone method of tracing the program flow ofexecution. In most system architectures, the stack register is considered as a dedicated register.Thus, it is not accidentally accessed when working with other memory registers. More rarely, astack register can be a general register that usually is accessible by a program but that deliberatelyis not used as its use is defined by the manufacturer. When a computer system consists of two ormore stack registers, meaning there is potentially more than one stack, the architecture isknown as a stack machine.

At the lowest level of computer programming, a stack is an area of memory having a well-defined type of behaviour. The stack can have information added to it in a process known aspushing, or it can have information retrieved from it, which is known as popping. The model for


Unit 12: Stacks

Notesa stack is LIFO, meaning that if various pieces of information are pushed into the stack, then thefirst element pushed in will be the last one to be popped out, while the last element pushed inwill be the first one to be retrieved with a pop command. A stack register keeps track of the topof the stack, which is always the last item pushed into it.

When a computer program is executing, every instruction ‘which is being executed consists of aspecific memory address where it is temporarily stored for the program duration. If a programcalls a subroutine or a procedure, function or method, depending on the programming language,then the program must jump to the memory address of the subroutine code in order to executeit. The address where the program control flow breaks to branch to the subroutine is pushedonto the stack so it is remembered.

Notes When the subroutine has completed executing, the program knows to where itshould return in the main code by popping the code address from the top of the stack,where the stack register is pointing.

Even though there are other techniques that can be utilised to attain the same results, using astack and stack register permits for a significant programming concept called recursion. Arecursive function is a function that, within its own code, calls itself. Generally, this process isutilised in sorting algorithms and for certain mathematical functions. The stack register iskeeping track of every last address where the execution is branching. Thus, a function can safelyexecute recursion with the knowledge that, finally, control will return to the origin point. Onecomplication takes place if the full stack becomes full and no room is there in memory, in whichcase a stack overflow occurs, ceasing the program execution.

Self Assessment

Fill in the blanks:

1. Stack is a group of memory locations in the …………………… memory.

2. The …………………… is an area in the memory, where data is pushed in and popped outwhenever required.

3. The top of the element is always indicated by a special purpose register called…………………….

4. Data bytes in the register pair of the microprocessor can be stored in the stack in reversedorder by using the instruction, …………………….

5. Data bytes can be transferred from the stack to representative register by using theinstruction, …………………….

6. A …………………… is a memory location that holds the current address of the top of aregion of separate computer memory known as the stack.

7. The stack can have information added to it in a process called …………………….

8. A …………………… is a function that, within its own code, calls itself.

12.2 PUSH & POP

We use push and pop instructions to “push” bytes on the stack and then take them off. Onpushing something, the stack counter will decrease with 2 and then the register pair is loadedonto the stack. When we pop, the register pair is first lifted of the stack, and then SP increases



Notes by 2. The push (PSH) and pull (PUL) instructions are used to store and load data to and from thestack.

!Caution Push and Pop only operate on words (2 bytes i.e., 16 bits).

The stack is a reserved memory area in RAM where temporary information may be stored. An8-bit stack pointer is used to hold the address of the last stack entry. This location which has thelast entry is known as the top of the stack.

When the information is written on the stack, the operation is known as PUSH. When theinformation is read from the stack, the operation is known as POP.

We can push (and pop) every register pairs: BC, DE, HL and PSW (Register A and Flags). Whenwe pop PSW, keep in mind that all flags may be changed. We can’t push an immediate value. Ifwe want, it is required to load a register pair with the value and then push it. When we pushsomething, the contents of the registers will still be the same; they won’t be erased or something.Moreover, if we push DE, we can pop it back as HL.

PSHA (or B or X or Y) instruction writes the contents of the specified register in the stack at theSP location (at the location whose address is contained in SP) and then decrements the SP once(for PSHA and PSHB) or twice (for PSHX and PSHY) as the original stack location is no longervacant however contains the pushed data.

PULA (or B or X or Y) instruction first increments the SP once to point to the last item that hasbeen inserted into the stack and then transfers the contents of the stack appropriately to thespecified register.

Note that once the contents of a stack location have been pulled, the location is consideredvacant, although the data is still there. It will be overwritten by the next PUSH or other use of thestack. The stack acts as a LIFO (Last-In-First-Out) structure. The information that was last pushedonto the stack is retrieved by a pull instruction.


Figure 12.2: Stack Structure and Stack Operations


Unit 12: Stacks

NotesHere we will give pseudo code for stack operations.

(a) Push Operation

Algorithm push(newElement)

//increment index to the top element;

topElementIndex ← topElementIndex + 1

stack[topElementIndex] ← newElement

(b) Pop Operation

Algorithm pop()

elementToReturn = stack[topElementIndex]

topElementIndex ← topElementIndex - 1

return elementToReturn

(c) isEmpty Operation

Algorithm isEmpty()

if topElementIndex = -1

return true

else

return false

Task Compare and contrast push and pop operation.

12.2.1 Stack Instruction

1. In order to create the stack, initialize the SP register. This can be done by using thefollowing instruction.

LXI SP, 16 bit address

This instruction loads SP register with the 16 bit address

2. The following instruction inserts element into the stack.

PUSH Rp

where Rp symbolizes register pair. This instruction copies the content specified by theregister pair into the stack.

Example:

PUSH B

PUSH D

PUSH H

When PUSH Rp is encountered the SP is decremented and the content of higher orderregister, B, D or H are copied in the locations shown by SP. The SP is again decrementedand the lower order register content will be copied into the stack.



Notes 3. In order to delete an element from the stack we use the following instruction:

POP Rp

This instruction copies the content of top two memory locations of the stack into thespecified register pair, Rp. First content of the memory location showed by the SP iscopied into the lower order register and then the SP is incremented by 1. Now this contentis copied into higher order register. Stack instructions belong to data transfer group.Therefore, content of source are not affected and no flags are affected.

Example:

POP B

POP D

POP H

12.2.2 PSW Register Pair

PSW symbolizes “program status word” or the status register that is concerned with the presentstate of a particular processor. It comprises various flag bits for a processor. Therefore, PSW issometimes referred to as a “flag register”.

Did u know? Some people also refer to the Program Status Word as the “condition coderegister”.

Flag bits are what describe the actual as well as current state of the processor. These bits consistof details like recent arithmetic operations that may have produced either zero, negative, orpositive result. Like in the case of an instruction with a “branch on zero” result making use of thesubtraction method, this particular branch will be taken if the processor status flag provides azero value as the end-product of the subtraction process.

PSW also includes details on the microprocessor’s process state. The status flags are written bymachine code instructions that are presently running on the processor. In basic processor designs,there are three standard flags i.e. the “zero” flag, “carry flag, and “overflow” flag. The zero flagstates that the result of a logical or arithmetic operation is zero. The carry flag meanwhile refersto the ability of large numbers to carry a binary digit from a bit that is considered the leastimportant.

The overflow flag literally signifies that a logical operation result cannot fit in the involvedregister and thus overflows. Other common status flags in microprocessors comprise the S/Nflag and the P flag. S/N flag is short for sign/negative flag and this flag is used when the resultis negative. However, there are also processors that make use of the S and N flags individuallywith distinct meanings from each other. The N flag symbolizes a negative result while the S orsign flag involves an addition or subtraction in the process.

PUSH PSW and POP PSW Register Pair

PUSH PSW (PUSH Processor Status Word) and POP PSW (POP Processor Status Word) instructionswill permit the programmer to save the contents of the A register and of the condition flags onthe stack, or to retrieve them from the stack. The Processor Status Word (PSW) of the 8085 isdefined as a “Flag Byte” which includes the condition flag bits in a particular sequence:


Unit 12: Stacks

NotesSZ0AC0P1C

Furthermore, the contents of the A register is also saved as part of the PSW. When the PUSH PSWis encountered, the contents of the A register is pushed onto the stack first, followed by the Flagbyte. The SP is then updated. When the POP is executed, the Flag byte is retrieved first, and thebits are loaded into their proper flip-flops. The A register is then loaded with the next byteretrieved. This permits programmers to save conditions at the beginning of subroutines. So, theexecution of the instructions inside the routines will not alter the conditions under which theoriginal program was operating.

Task Make distinction between PUSH PSW and POP PSW.

Self Assessment

Fill in the blanks:

9. When the information is written on the stack, the operation is called …………………….

10. When the information is read from the stack, the operation is called …………………….

11. The stack acts as a …………………… structure.

12. …………………… stands for “program status word” or the status register that pertains tothe current state of a particular processor.

13. …………………… are what describe the actual and current state of the processor.

14. The …………………… flags are written by machine code instructions that are currentlyrunning on the processor.

15. The …………………… flag literally means that the result of a logical operation cannot fitin the involved register and therefore overflows.

�Case Study Automated Stacking System

An international building products company that provides support to generalcontractors, architects, engineers and governmental agencies needed an automatedway to stack flat and tapered boards to both increase speed and alleviate large

turnover in manpower.

Before working with Motion Controls Robotics, the company had no automation.Employees manually lifted and stacked the boards, often leading to injuries. The companyalso had a high employee turnover rate and used some temporary staff. In addition, the

Contd...



Notes stacks created manually were often uneven, making it difficult to keep the products fromleaning.

Solution: Motion Controls Robotics recommended a system using a robot with a vacuumpowered end-of-arm tool to position, square and pick up the boards from the existingequipment. The robot lifts the board and sets it onto a chain conveyor, rotating everyother board. At a pre-determined count, the stacks are sent out to handling conveyors thatmove them to down-line equipment.

Motion Controls Robotics installed tested and provided training and support during thestart up to familiarize the associates on how to operate the equipment. Motion ControlsRobotics technicians directly supervised start-up, eventually turning over operation tothe newly trained employees.

Details: The system used two Fanuc M-410iB robots, HandlingTool software and customwritten software to handle the robot motion. Peripheral equipment included an AllenBradley 505 plc, and Panel View Plus 1000 HMI.

Result: According to the company, this system allowed for three fewer employees pershift.

By decreasing the number of employees, the company reduced manpower turnover andinjuries. Straighter and neater stacks could not be achieved using the original manualsystem. With the automated system the robots can stack precisely and also rotate taperedboards every other part which allows for more even and straighter stacks.

Questions:

1. Explain the basic challenges which occur in automated stacking system.

2. How automated stacking systems overcome the manpower problems?

Source: http://www.motioncontrolsrobotics.com/casestudy_boardhandling.cfm


Unit 12: Stacks

Notes12.3 Summary

� The stack is an area of memory used for the temporary storage of information.

� Stack pointer means a 16-bit register which point the R/W memory location of Stack.

� LXI SP instruction loads a 16 bit memory address in the stack pointer register (SP) of themicroprocessor.

� A stack register is a memory location, usually on the central processing unit (CPU) orrelated processing hardware that holds the current address of the top of a region of separatecomputer memory known as the stack.

� The stack can have information added to it in a process called pushing, or it can haveinformation retrieved from it, which is called popping.

� A recursive function is a function that, within its own code, calls itself. This processcommonly is used in sorting algorithms and for certain mathematical functions.

� The push (PSH) and pull (PUL) instructions store and load data to and from the stack.

� PSW stands for “program status word” or the status register that pertains to the currentstate of a particular processor.

12.4 Keywords

LXI SP: LXI SP instruction loads a 16 bit memory address in the stack pointer register (SP) of themicroprocessor.

POP: When the information is read from the stack, the operation is called POP.

PSW: PSW stands for “program status word” or the status register that pertains to the currentstate of a particular processor.

PUSH: When the information is written on the stack, the operation is called PUSH.

Recursive Function: A recursive function is a function that, within its own code, calls itself.

Stack: The stack is an area of memory used for the temporary storage of information.

Stack Pointer: Stack pointer means a 16-bit register which point the R/W memory location ofStack.

Stack Register: A stack register is a memory location, usually on the central processing unit(CPU) or related processing hardware that holds the current address of the top of a region ofseparate computer memory known as the stack.


1. Explain the concept of stack with example.

2. What is a stack pointer? Illustrate with example.

3. Define the instruction which represents the beginning of the stack.

4. Elucidate the significance of stack pointer.

5. Illustrate the use of push (PSH) and pull (PUL) instructions in storing and loading data toand from the stack.



Notes 6. Once the contents of a stack location have been pulled, the location is considered vacant,although the data is still there. Comment.

7. Discuss the instruction used for storing register pair data bytes of the microprocessor inthe stack.

8. Describe the instructions used for inserting element into the stack and deleting an elementfrom the stack.

9. What do you mean by top of the stack? Illustrate.

10. Explain the concept of PSW Register Pair.


1. Read/Write 2. stack

3. stack pointer (SP) 4. RSH

5. POP 6. stack register

7. pushing 8. recursive function

9. PUSH 10. POP

11. LIFO 12. PSW

13. Flag bits 14. Status

15. overflow






Online links http://microprocessorguide.blogspot.in/2012/09/what-is-stack-pointer.html

http://people.cs.pitt.edu/~mock/cs2210/handouts/itanium-register-convention.pdf

http://whatis.techtarget.com/definition/stack-pointer

h t t p : / / w w w . g e c a s s e t s . c o . i n / 8 0 8 5 % 2 0 M i c r o p r o c e s s o r % 2 0 -%20Ramesh%20Gaonkar.pdf


Unit 13: Subroutines

NotesUnit 13: Subroutines

CONTENTS

Objectives

Introduction

13.1 Subroutine

13.1.1 Definition

13.1.2 Calling a Subroutine

13.1.3 Exiting a Subroutine

13.2 Restart Sequence

13.3 Conditional Call Instruction

13.3.1 Subroutine Call

13.3.2 Trap Subroutine Call Activation/Deactivation

13.4 Return Instruction

13.5 Summary

13.6 Keywords



Objectives


� Discuss the concept of a subroutine

� Show the process of creating a subroutine

� Analyse how to call a subroutine

� Elaborate upon the restart sequence

� Explain the conditional call instruction and its uses

� Describe the return instruction

Introduction

Structured programming is a subset of procedural programming that enforces a logical structureon the program being written to make it more efficient and easier to understand and modify.Structured programming frequently employs a top-down design model, in which developersmap out the overall program structure into separate subsections. A structured program iscomposed of Main Program and Subroutines (aka. functions and procedures).

A subroutine is a unit of code (or a fragment of a program) that can be called from a point in aprogram and executed, and a return made to the instruction after the calling point. A subroutineis called to perform some task or function that is used frequently in the program.



Notes 13.1 Subroutine

We will now discuss about subroutines in detail.

13.1.1 Definition

Branches and jumps are important program control constructs, but another important extensionof program control are procedure calls, often referred to as subroutines. Three basic steps formof a subroutine call:

Step 1: Program control is changed:

� from the current routine

� to the beginning of the subroutine code.

Step 2: Subroutine code is executed.

Step 3: Program control is changed:

� from end of subroutine

� to the calling routing immediately after subroutine call instruction.

We can illustrate how subroutine calls change program flow as follows:

Source: http://users.ece.gatech.edu/~jeff/ece2030/lectures/procedure_calls.pdf

The program counter (PC) stores the address of the 1st instruction of subroutine. When thecontrol is returned from a subroutine call then PC holds the address of instruction after subroutinecall instruction. The idea is to save the state of the machine. In the most basic microprocessor,saving the state means to save the PC in a known location. Some microprocessors also saveother registers during a procedure call.

13.1.2 Calling a Subroutine

When the same function is required more than once in a program, it is frequently written as asubroutine, that is, a subprogram that can be used any number of times by the main program.This capability is provided by the following three instructions;

� JSR (jump to subroutine)

Figure 13.1: Subroutine Call



Notes� BSR (branch to subroutine)

� RTS (return from subroutine)

The following figure illustrates the use of the same subroutine by two different parts of the mainprogram. The subroutine located at $0200 can be entered from either location $0011 or $00CC byplacing a JSR (opcode = $BD) instruction at these addresses.


JSR $0200 has the machine code “BD 02 00” in the extended addressing mode. After the subroutineis completed (i.e., when a return from subroutine RTS instruction is executed), the programresumes from the instruction following the location where it called the subroutine. The exampleshows that in the first jump (a), the program returns back to $0014 when it executes the RTS andin the second jump (b), the program returns back to $00CF following the execution of the RTS.Because the subroutine must return to one of several locations, depending on which one causedit to be entered, the original contents of the PC must be preserved so that the subroutine knowswhere to return.

Notes The JSR instruction has both indexed and extended modes. With the completeexecution of JSR, the address of the next instruction to be executed (the one following theJSR) is stored automatically in the stack and the PC is changed appropriately according tothe addressing mode used for JSR, i.e. the PC is changed to have the address of the firstinstruction in the subroutine.

Figure 13.2: Subroutine Use



Notes


BSR (branch to subroutine) has only the relative addressing mode and the subroutine startaddress is calculated by the CPU by using the offset value provided in the program memoryafter the opcode of the BSR.

13.1.3 Exiting a Subroutine

In the example above, each subroutine must have RTS (return from subroutine) as the lastinstruction of the subroutine. With the execution of the RTS, the CPU restores the PC from thestack automatically and therefore the program returns back to the instruction where it has leftbefore the jump or branch to the subroutine has occurred. The following example is for theextended case in the above Figure:


Self Assessment


1. Structured programming is less efficient and difficult to understand and modify.

2. Structured programming frequently employs a bottom up design model

3. A subroutine is called to perform some task or function that is used frequently in theprogram.

4. The program counter (PC) stores the address of the last instruction of subroutine.

Figure 13.3: Subroutine Operations

Figure 13.4: Subroutine Use



Notes13.2 Restart Sequence

The RST instruction is equivalent to a 1-byte call instruction to one of eight memory locationsdepending upon the number. The instructions are generally used in conjunction with interruptsand inserted using external hardware. However these can be used as software instructions in aprogram to transfer program execution to one of the eight locations. The addresses are:

Instruction Restart Address

RST 0 0000H

RST 1 0008H

RST 2 0010H

RST 3 0018H

RST 4 0020H

RST 5 0028H

RST 6 0030H

RST 7 0038H

The 8085 has four additional interrupts and these interrupts generate RST instructions internallyand thus do not require any external hardware. These instructions and their Restart addressesare:

Interrupt Restart Address

TRAP 0024H

RST 5.5 002CH

RST 6.5 0034H

RST 7.5 003CH

Self Assessment

Fill in the blanks:

5. The RST instruction is equivalent to a …………………… byte call instruction.

6. The …………………… instruction can be used as software instructions in a program totransfer program execution to one of the eight locations.

7. The 8085 has …………………… additional interrupts.

8. The restart address of TRAP interrupt is …………………….

13.3 Conditional Call Instruction

We have two types of calls:

Unconditional Subroutine Call

The general form of the subroutine is:

CALL 16-bit address



Notes The program sequence is transferred to the memory location specified by the 16-bit addressgiven in the operand. Before the transfer, the address of the next instruction after CALL (thecontents of the program counter) is pushed onto the stack.

Example: CALL 2034 or CALL XYZ

Call Conditionally

Operand: 16-bit address

The program sequence is transferred to the memory location specified by the 16-bit addressgiven in the operand based on the specified flag of the PSW as described below. Before thetransfer, the address of the next instruction after the call (the contents of the program counter) ispushed onto the stack.

Example: CZ 2034 or CZ XYZ

Opcode Description Flag Status

CC Call on Carry CY = 1

CNC Call on no Carry CY = 0

CP Call on positive S = 0

CM Call on minus S = 1

CZ Call on zero Z = 1

CNZ Call on no zero Z = 0

CPE Call on parity even P = 1

CPO Call on parity odd P = 0

13.3.1 Subroutine Call

A subroutine is referenced by a CALL statement. The form of a CALL statement is:

CALL sub [([a [,a]...])]

� where: sub is the symbolic name of a subroutine or dummy procedure

� a is an actual argument

When we execute a CALL statement, it results in:

� evaluation of actual arguments that are expressions,

� association of actual arguments with the corresponding dummy arguments, and

� the actions specified by the referenced subroutine.

Return of control from the referenced subroutine completes execution of the CALL statement. Asubroutine specified in a subprogram may be referenced within any other procedure subprogramor the main program of the executable program. A subprogram must not reference itself, eitherdirectly or indirectly. When a CALL statement is executed, the referenced subroutine must beone of the subroutines specified in subroutine subprograms or by other means in the executableprogram.



NotesProcessing State Information is SAVED during Function and Subroutine Calls

Exceptions and hardware interrupts ISRs have a very special restriction: they must preserve thestate of the CPU. In particular, these ISRs must preserve all registers they modify.

Example: Consider the following extremely simple ISR:

SimpleISR proc farmov ax, 0iretSimpleISR endp

This ISR obviously does not preserve the machine state; it explicitly disturbs the value inax and then returns from the interrupt. Suppose you were executing the following codesegment when a hardware interrupt transferred control to the above ISR:

mov ax, 5add ax, 2; Suppose the interrupt occurs here.puti..

The interrupt service routine would set the ax register to zero and your program would printzero rather than the value five. Worse yet, hardware interrupts are generally asynchronous,meaning they can occur at any time and rarely do they occur at the same spot in a program.Therefore, the code sequence above would print seven most of the time; once in a great while itmight print zero or two (it will print two if the interrupt occurs between the mov ax, 5 and addax, 2 instructions). Bugs in hardware interrupt service routines are very difficult to find, becausesuch bugs often affect the execution of unrelated code.

The solution to this problem, of course, is to make sure you preserve all registers you use in theinterrupt service routine for hardware interrupts and exceptions. Since trap calls are explicit, therules for preserving the state of the machine in such programs is identical to that for procedures.Writing an ISR is only the first step to implementing an interrupt handler. You must alsoinitialize the interrupt vector table entry with the address of your ISR. There are two commonways to accomplish this – store the address directly in the interrupt vector table or call DOS andlet DOS do the job for you.

13.3.2 Trap Subroutine Call Activation/Deactivation

A trap is a software-invoked interrupt. To execute a trap, you use the 80x86 int (software interrupt)instruction 3. There are only two primary differences between a trap and an arbitrary farprocedure call: the instruction you use to call the routine (int vs. call) and the fact that a trappushes the flags on the stack so you must use the iret instruction to return from it. Otherwise,there really is no difference between a trap handler’s code and the body of a typical far procedure.

The main purpose of a trap is to provide a fixed subroutine that various programs can callwithout having to actually know the run-time address. MS-DOS is the perfect example. The int21h instruction is an example of a trap invocation. Your programs do not have, to know theactual memory address of DOS’ entry point to call DOS. Instead, DOS patches the interrupt 21hvector when it loads into memory. When you execute int 21h, the 80x86, automatically transferscontrol to DOS’ entry point, where ever in memory that happens to be.



Notes There is a long list of support routines that use the trap mechanism to link application programsto themselves. DOS, BIOS and the mouse drivers are a few examples. Generally, you would usea trap to call a resident program function. Resident programs (see “Resident Programs” on page1025) load themselves into memory and remain resident once they terminate. By patching aninterrupt vector to point at a subroutine within the resident code, other programs that run afterthe resident program terminates can call the resident subroutines by executing the appropriateint instruction. Most resident programs do not use a separate interrupt vector entry for eachfunction they provide. Instead, they usually patch a single interrupt vector and transfer controlan appropriate routine using a function number that the caller passes in a register. By convention,most resident programs expect the function number in the ah register. A typical trap handlerwould execute a case statement on the value in the ah register and transfer control to theappropriate handler function.

Self Assessment

Fill in the blanks:

9. In an unconditional subroutine call, the program sequence is transferred to the memorylocation specified by the …………………… bit address given in the operand

10. In an unconditional subroutine call, before the transfer, the address of the next instructionafter CALL is pushed onto the …………………….

11. Return of control from the referenced subroutine completes execution of the…………………… statement.

12. A trap is a ……………………-invoked interrupt.

13.4 Return Instruction

A RETURN statement causes return of control to the referencing program unit and may appearonly in a function subprogram or subroutine subprogram. The form of a RETURN statement ina function subprogram is:

RETURN

The form of a RETURN statement in a subroutine subprogram is:

RETURN [e]

where e is an integer expression.

Execution of a RETURN statement terminates the reference of a function or subroutinesubprogram. Such subprograms may contain more than one RETURN statement; however, asubprogram need not contain a RETURN statement. Execution of an END statement in a functionor subroutine subprogram has the same effect as executing a RETURN statement in thesubprogram.

In the execution of an executable program, a function or subroutine subprogram must not bereferenced a second time without the prior execution of a RETURN or END statement in thatprocedure. Execution of a RETURN statement in a function subprogram causes return of controlto the currently referencing program unit. The value of the function must be defined and isavailable to the referencing program unit. Execution of a RETURN statement in a subroutinesubprogram causes return of control to the currently referencing program unit. Return of controlto the referencing program unit completes execution of the CALL statement. Execution of aRETURN statement terminates the association between the dummy arguments of the externalprocedure in the subprogram and the current actual arguments.



NotesIf e is not specified in a RETURN statement, or if the value of e is less than one or greater than thenumber of asterisks in the SUBROUTINE or subroutine ENTRY statement that specifies thecurrently referenced name, control returns to the CALL statement that initiated the subprogramreference and this completes the execution of the CALL statement.

If 1 <= e <= n, where n is the number of asterisks in the SUBROUTINE or subroutine ENTRYstatement that specifies the currently referenced name, the value of e identifies the eth asterisk inthe dummy argument list. Control is returned to the statement identified by the alternate returnspecified in the CALL statement that is associated with the eth asterisk in the dummy argumentlist of the currently referenced name. This completes the execution of the CALL statement.

Execution of a RETURN statement (or END statement) within a subprogram causes all entitieswithin the subprogram to become undefined, except for the following:

� Entities specified by SAVE statements

� Entities in blank common

� Initially defined entities that have neither been redefined or become undefined

� Entities in a named common block that appears in the subprogram and appears in at leastone other program unit that is referencing, either directly or indirectly, the subprogram

Notes If a named common block appears in the main program, the entities in the namedcommon block do not become undefined at the execution of any RETURN statement in theexecutable program.

�Case Study Subroutine History

Language Support

In the (very) early assemblers, subroutine support was limited. Subroutines were notexplicitly separated from each other or from the main program, and indeed the sourcecode of a subroutine could be interspersed with that of other subprograms. Some assemblerswould offer predefined macros to generate the call and return sequences. Later assemblers(1960s) had much more sophisticated support for both in-line and separately assembledsubroutines that could be linked together.

Self-modifying Code

The first use of subprograms was on early computers that were programmed in machinecode or assembly language, and did not have a specific call instruction. On those computers,each subroutine call had to be implemented as a sequence of lower level machineinstructions that relied on self-modifying code. By replacing the operand of a branchinstruction at the end of the procedure’s body, execution could then be returned to theproper location (designated by the return address) in the calling program (usually just afterthe instruction that jumped into the subroutine).

Subroutine Libraries

Even with this cumbersome approach, subroutines proved very useful. For one thing theyallowed the same code to be used in many different programs. Moreover, memory was a

Contd...



Notes very scarce resource on early computers, and subroutines allowed significant savings inprogram size.

In many early computers, the program instructions were entered into memory from apunched paper tape. Each subroutine could then be provided by a separate piece of tape,loaded or spliced before or after the main program; and the same subroutine tape couldthen be used by many different programs. A similar approach was used in computerswhich main input was through punched cards. The name subroutine library originallymeant a library, in the literal sense, which kept indexed collections of such tapes or carddecks for collective use.

Return by Indirect Jump

To remove the need for self-modifying code, computer designers eventually provided anindirect jump instruction, which operand, instead of being the return address itself, was thelocation of a variable or processor register containing the return address.

On those computers, instead of modifying the subroutine’s return jump, the calling programwould store the return address in a variable so that when the subroutine completed, itwould execute an indirect jump that would direct execution to the location given by thepredefined variable.

Jump to Subroutine

Another advance was the jump to subroutine instruction, which combined the saving of thereturn address with the calling jump, thereby minimizing overhead significantly.

In the IBM System/360, for example, the branch instructions BAL or BALR, designed forprocedure calling, would save the return address in a processor register specified in theinstruction. To return, the subroutine had only to execute an indirect branch instruction(BR) through that register. If the subroutine needed that register for some other purpose(such as calling another subroutine), it would save the register’s contents to a privatememory location or a register stack.

In the HP 2100, the JSB instruction would perform a similar task, except that the returnaddress was stored in the memory location that was the target of the branch. Execution ofthe procedure would actually begin at the next memory location. In the HP 2100 assemblylanguage, one would write, for example

...JSB MYSUB (Calls subroutine MYSUB.)BB ... (Will return here after MYSUB is done.)

to call a subroutine called MYSUB from the main program. The subroutine would becoded as

MYSUB NOP (Storage for MYSUB’s return address.)AA ... (Start of MYSUB’s body.)...JMP MYSUB,I (Returns to the calling program.)

The JSB instruction placed the address of the NEXT instruction (namely, BB) into thelocation specified as its operand (namely, MYSUB), and then branched to the NEXT locationafter that (namely, AA = MYSUB + 1). The subroutine could then return to the mainprogram by executing the indirect jump JMP MYSUB,I which branched to the locationstored at location MYSUB.

Compilers for Fortran and other languages could easily make use of these instructionswhen available. This approach supported multiple levels of calls; however, since the

Contd...



Notesreturn address, parameters, and return values of a subroutine were assigned fixed memorylocations, it did not allow for recursive calls.

Incidentally, a similar method was used by Lotus 1-2-3, in the early 1980s, to discover therecalculation dependencies in a spreadsheet. Namely, a location was reserved in each cellto store the return address. Since circular references are not allowed for natural recalculationorder, this allows a tree walk without reserving space for a stack in memory, which wasvery limited on small computers such as the IBM PC.

Call Stack

Most modern implementations use a call stack, a special case of the stack data structure, toimplement subroutine calls and returns. Each procedure call creates a new entry, called astack frame, at the top of the stack; when the procedure returns, its stack frame is deletedfrom the stack, and its space may be used for other procedure calls. Each stack framecontains the private data of the corresponding call, which typically includes the procedure’sparameters and internal variables, and the return address.

The call sequence can be implemented by a sequence of ordinary instructions (an approachstill used in reduced instruction set computing (RISC) and very long instruction word(VLIW) architectures), but many traditional machines designed since the late 1960s haveincluded special instructions for that purpose.

The call stack is usually implemented as a contiguous area of memory. It is an arbitrarydesign choice whether the bottom of the stack is the lowest or highest address within thisarea, so that the stack may grow forwards or backwards in memory; however, manyarchitectures chose the latter.

Some designs, notably some Forth implementations, used two separate stacks, one mainlyfor control information (like return addresses and loop counters) and the other for data.The former was, or worked like, a call stack and was only indirectly accessible to theprogrammer through other language constructs while the latter was more directly accessible.

When stack-based procedure calls were first introduced, an important motivation was tosave precious memory. With this scheme, the compiler does not have to reserve separatespace in memory for the private data (parameters, return address, and local variables) ofeach procedure. At any moment, the stack contains only the private data of the calls thatare currently active (namely, which have been called but haven’t returned yet). Because ofthe ways in which programs were usually assembled from libraries, it was (and still is)not uncommon to find programs that include thousands of subroutines, of which only ahandful are active at any given moment. For such programs, the call stack mechanismcould save significant amounts of memory. Indeed, the call stack mechanism can be viewedas the earliest and simplest method for automatic memory management.

However, another advantage of the call stack method is that it allows recursive subroutinecalls, since each nested call to the same procedure gets a separate instance of its privatedata.

Delayed Stacking

One disadvantage of the call stack mechanism is the increased cost of a procedure call andits matching return. The extra cost includes incrementing and decrementing the stackpointer (and, in some architectures, checking for stack overflow), and accessing the localvariables and parameters by frame-relative addresses, instead of absolute addresses. Thecost may be realized in increased execution time, or increased processor complexity, orboth.

Contd...



Notes This overhead is most obvious and objectionable in leaf procedures or leaf functions, whichreturn without making any procedure calls themselves. To reduce that overhead, manymodern compilers try to delay the use of a call stack until it is really needed.

For example, the call of a procedure P may store the return address and parameters of thecalled procedure in certain processor registers, and transfer control to the procedure’sbody by a simple jump. If procedure P returns without making any other call, the call stackis not used at all. If P needs to call another procedure Q, it will then use the call stack to savethe contents of any registers (such as the return address) that will be needed after Qreturns.

Questions:




Source: http://enc.tfode.com/Subroutine

Self Assessment


13. A RETURN statement causes return of control to the referencing program unit.

14. Execution of a RETURN statement does not terminate the reference of a function orsubroutine subprogram.

15. A subprogram can have only one RETURN statement.

16. Execution of an END statement in a function or subroutine subprogram has the same effectas executing a RETURN statement in the subprogram.

13.5 Summary

� Structured programming is a subset of procedural programming that enforces a logicalstructure on the program being written.

� Subroutine is called to perform some task or function that is used frequently in the program.

� Program counter (PC) stores the address of the 1st instruction of subroutine.

� RST instruction is equivalent to a 1-byte call instruction to one of eight memory locationsdepending upon the number.

� Call is used to refer to a subroutine.

� The main purpose of a trap is to provide a fixed subroutine that various programs can callwithout having to actually know the run-time address.

� A RETURN statement causes return of control to the referencing program unit and mayappear only in a function subprogram or subroutine subprogram.

13.6 Keywords

BSR: It results the control to branch to a subroutine.

Call: It is used to refer to a subroutine.



NotesJSR: Causes the control to jump to a subroutine.

Program Counter (PC): It stores the address of the 1st instruction of subroutine.

RST: This instruction is equivalent to a 1-byte call instruction to one of eight memory locationsdepending upon the number.

RTS: It is used to return from subroutine.

Structured Programming: It is a subset of procedural programming that enforces a logicalstructure on the program being written.

Subroutine: It is called to perform some task or function that is used frequently in the program.

Trap: It is a software-invoked interrupt.


1. Explain the advantages of using structured programming.

2. Define a subroutine.

3. Explain the use of a subroutine.

4. What is a program counter?

5. Write a note on the RST instruction.

6. Give the basic syntax of a Call statement.

7. Differentiate between unconditional and conditional subroutine call.

8. Discuss the trap instruction.

9. What do you mean by saving the state of a program instruction?

10. Why do we need the return statement?


1. False 2. False

3. True 4. False

5. 8 6. RST

7. 4 8. 0024H

9. 16 10. Stack

11. CALL 12. Software

13. True 14. False

15. False 16. True



Ramesh S. Gaonkar, Microprocessor Architecture, Programming, and Applications withthe 8085.



Notes Sunil Mathur, Microprocessor 8085 and Its Interfacing.


Online links http://engeletrica.sobral.ufc.br/professores/marcelo/Micro/8085_is_details.pdf

http://www.fortran.com/F77_std/rjcnf0001-sh-15.html

http://www.kilowattsoftware.com/tutorial/rexx/call.htm

http://www.uotechnology.edu.iq/dep-cse/lectures/3/control/mico.pdf


Unit 14: Interrupts

NotesUnit 14: Interrupts

CONTENTS

Objectives

Introduction

14.1 Interrupt

14.1.1 Types of Interrupts

14.1.2 8085 Microprocessor Interrupts


14.2.1 Vectored Interrupts

14.2.2 Interrupt Vectors and the Vector Table

14.3 Summary

14.4 Keywords



Objectives


� Explain interrupts and its various types

� Discuss interrupts in 8085 Microprocessor

� Define interrupt controller

� Discuss about Interrupt Vectors and the Vector Table

Introduction

Interrupt is a process by which an I/O or an instruction can suspend the usual execution ofprocessor and get itself serviced. When a program obtains an interrupt signal, it takes a particularactivity (which can be to disregard the signal). In this unit, you will learn about Interrupts andits various types. Later in the unit, you will learn about interrupts in microprocessor 8085.Finally, interrupts vectors and vector table will be discussed.

14.1 Interrupt

Interrupt signals can cause a program to suspend itself for the time being to service the interrupt.Interrupt starts from I/O device and is asynchronous in nature. The process of ending anyinterrupt is known as Interrupt Service.

Interrupt pointers can arrive from different kind of sources. For example, every keystrokegenerates an interrupt signal. Interrupts can also be developed by other devices, such as aprinter, to show that something has appeared. These are called hardware interrupts. Interruptsignals started by programs are called software interrupts. A software interrupt is also known asa trap or an exception.



Notes PCs support 256 types of software and 15 types of hardware interrupts. Each software interruptis affiliated with an interrupt handler known as routine which takes control the moment aninterrupt takes place. For example, when you press a key on your keyboard, this routine triggersa specified interrupt handler. The complete list of interrupts and related interrupt handlers isretained in a table called the interrupt vector table, which stays in the first 1 K of addressablememory.

14.1.1 Types of Interrupts

The Interrupts are of two basic types:

� Maskable Interrupt: The interrupts which can be Masked-off or can be made pending fora while are known as Maskable Interrupts. These interrupts can be handled after theexecutions will be completely done so it is clear that they will have the coding of loweremergency levels so these are used to interface or connect peripheral devices.

� Non-maskable Interrupt: The interrupts which cannot be Masked-off or cannot be madepending for a while are known as Non-Maskable Interrupts. These interrupts should behandled quickly at the time when they are introduced to the microprocessor terminal soit is clear that they will have the coding of the highest emergency levels so these are usedfor emergency purposes like power failure, smoke detector etc.

As we have seen above that the maskable interrupts will have low emergency condition andnon-maskable interrupts will have the highest emergency condition so the interrupt servicefunction of non-maskable interrupts should be first compared to the maskable interrupts thisconditioning or preference of solving any interrupt is known as Priority of the interrupt andhere maskable interrupt will have lower priority than the non-maskable interrupt.

Interrupts can also be classified as:

� Vectored Interrupt: In this type of interrupt the address of the service routine is hard-wired.

� Non-vectored: In this type of interrupt the address of the service routine needs to be giventhrough external device.

When the Microprocessor receives an interrupt signal, it suspends the program which is currentlyexecuting and jumps to an Interrupt Service Routine (ISR) to reply to the incoming interrupt.Generally each interrupt have its own ISR. Depending on the type of interrupt (maskable ornon-maskable) it may be handled immediately or with delay.

14.1.2 8085 Microprocessor Interrupts

There are 6 pins available in 8085 for interrupt. They are named TRAP, RST 7.5, RST 6.5, RST 5.5and INTR and an acknowledgement signal named INTA .

Figure 14.1: 8085 Microprocessor Interrupts


Unit 14: Interrupts

Notes� TRAP Interrupt: It is a non-maskable interrupt so will have the highest priority among allthe interrupts. It can be triggered using edge triggering or level triggering at the inputline. When this interrupt is introduced to the microprocessor the microprocessor willtransfer its control to location number 0024H in the memory. This interrupt is used for thehighest emergency conditions like power failure or smoke detectors.

� RST 7.5 (Reset 7.5): It is a maskable interrupt and will have the second highest priorityamong all the interrupts. It can be triggered using positive edge triggering or triggered atthe rising edge of the signal. When this interrupt is introduced to the microprocessor themicroprocessor will transfer its control to location number 003CH in the memory. Thiscan be enabled by EI instruction and can be disabled by SIM and DI instructions.

� RST 6.5 (Reset 6.5): It is a maskable interrupt and will have the third highest priorityamong all the interrupts. It can be triggered using level triggering. When this interrupt isintroduced to the microprocessor the microprocessor will transfer its control to locationnumber 0034H in the memory. This can be disabled by SIM and EI instructions.

� RST 5.5 (Reset 5.5): It is a maskable interrupt and will have the fourth highest priorityamong all the interrupts. It can be triggered using level triggering. When this interrupt isintroduced to the microprocessor the microprocessor will transfer its control to locationnumber 002CH in the memory. This can be disabled by SIM and EI instructions.

� INTR (Interrupt Request) and INTA (Interrupt Acknowledgement): Interrupt request is amaskable interrupt and will have the last priority among all the interrupts. It can betriggered using level triggering. This interrupt is introduced to the microprocessor fromthe external devices to give the information about the upcoming interrupt from the deviceas it is sent from the microprocessor for any of the above mentioned interrupts so that themicroprocessor can make itself ready for the interrupt.

After receiving this interrupt microprocessor will make it ready and sends a signal back to thedevice named Interrupt Acknowledgement which is a receiving signal for the INTR and afterreceiving this signal the concerned device will send its corresponding interrupt.

Self Assessment

Fill in the blanks:

1. …………………… is a process by which an I/O or an instruction can suspend the usualexecution of processor and get itself serviced.

2. When a …………………… obtains an interrupt signal, it takes a particular activity.

3. When the Microprocessor receives an interrupt signal, it suspends the program which iscurrently executing and jumps to an …………………… to reply to the incoming interrupt.

4. In …………………… type of interrupt the address of the service routine is hard-wired.

5. In …………………… type of interrupt the address of the service routine needs to be giventhrough external device.

6. TRAP Interrupt is a …………………… interrupt so will have the highest priority amongall the interrupts.

7. …………………… is a maskable interrupt and will have the third highest priority amongall the interrupts.



Notes 14.2 Interrupt Controller

It is the block which controls different interrupts coming from the external devices associated tothe 8085 microprocessor by checking their priority order and sends different interrupts one byone to the 8085 microprocessor for interrupt service.

INTA

TRAP

RST 7.5

RST 6.5

RST 5.5

INTR

TO

MIC

RO

PR

OC

ESS

OR

INT

ER

RU

PT

CO

NT

RO

LL

ER

14.2.1 Vectored Interrupts

Whenever any interrupt introduces at the microprocessor terminal it will direct themicroprocessor control to the defined address location so that the microprocessor can executethe interrupt service function which is uniquely defined for different interrupts. These memorylocations will have a number of locations associated together for the interrupt service executionprogram which is known as routine. This collection of memory locations are known as VectorLocation and the interrupts which use these vectors are known as Vectored Interrupts. This canbe seen in the Table 14.1.

Interrupt Name Vector Address Triggering Priority Type Vectored

TRAP 0024H Edge and Level 1st Non-Maskable Yes

RST 7.5 003CH Level 2nd Maskable Yes

RST 6.5 0034H Level 3rd Maskable Yes

RST 5.5 002CH Level 4th Maskable Yes

INTR No Location Level 5th Maskable No

14.2.2 Interrupt Vectors and the Vector Table

An interrupt vector is a pointer to where the ISR is retained in memory. All interrupts aremapped up on a memory area called the Interrupt Vector Table (IVT). The IVT is generallylocated in memory page 00 (0000H - 00FFH). The aim of the IVT is to contain the vectors thatforward the microprocessor to the right location when an interrupt arrives.

Figure 14.2: Interrupt Controller

Table 14.1: Vectored Interrupts


Unit 14: Interrupts

NotesExample: Let a device interrupts the microprocessor device using the RST 7.5 interrupt

line. As the RST 7.5 interrupt is vectored, microprocessor knows using a call instruction in whichmemory location it has to go. RST7.5 is knows as Call 003Ch to Microprocessor. Microprocessorgoes to 003C location and will get a JMP (jump) instruction to the actual ISR address. TheMicroprocessor will then, jump to the location of ISR.

The 8085 Non-Vectored Interrupt Process

1. To enable the interrupt process, use the EI instruction.

2. During the execution of every instruction microprocessor 8085 checks for an interrupt.

3. If INTR is high, microprocessor completes current instruction, disables the interrupt andsends INTA (Interrupt acknowledge) signal to the device that caused interruption.

4. INTA allows the I/O device to send a RST instruction through data bus.

5. Upon receiving the INTA signal, microprocessor saves the memory location of the nextinstruction on the stack and the program is then transferred to call location (ISR Call)given by the RST instruction.

6. Microprocessor performs the ISR.

7. ISR must include the ‘EI’ instruction to enable the further interruption within the program.

8. RET instruction at the end of the ISR allows the MP to retrieve the return address from thestack and the program is transferred back to where the program was interrupted.

Software Interrupts

There are eight Software interrupts in 8085 Microprocessor. They are from RST0 to RST7.

For calculation, Vector Address = Interrupt Number * 8.

Restart Instruction Equivalent to

RST0 CALL 0000H

RST1 CALL 0008H

RST2 CALL 0010H

RST3 CALL 0018H

RST4 CALL 0020H

RST5 CALL 0028H

RST6 CALL 0030H

RST7 CALL 0038H

Issues in Implementing INTR Interrupts

� The INTR must remain active for 17.5 T states.

� INTR should be turned off as soon as the INTA signal is received.

� If the EI instruction is placed early in the ISR, other interrupt may occur before the ISR isdone.

Before we wind up the chapter, let us see an example of Interrupt usage.

Table 14.2: Restart Instructions



NotesExample: Set the interrupt masks so that RST5.5 is enabled, RST6.5 is masked, and RST7.5

is enabled. First let us determine the contents of the accumulator:

� Enable 5.5 bit 0 = 0

� Disable 6.5 bit 1 = 1

� Enable 7.5 bit 2 = 0

� Allow setting the masks bit 3 = 1

� Don’t reset the flip flop bit 4 = 0

� Bit 5 is not used bit 5 = 0

� Don’t use serial data bit 6 = 0

� Serial data is ignored bit 7 = 0

Contents of accumulator are: 0AH

Here,

EI: Enable interrupts including INTR

MVI A, 0A is used to prepare the mask to enable RST 7.5, and 5.5, disable 6.5

SIM is used to apply the settings RST masks

SIM and RIM

SIM and RIM for interrupts:

� The 8085 provide additional masking facility for RST 7.5, RST 6.5 and RST 5.5 using SIMinstruction.

Source: http://www.8085projects.info/images/Interrupt-Pic3-Pic49.png

Figure 14.3: Format of 8-bit Data to be Loaded in Accumulator before Executing Instruction


Unit 14: Interrupts

Notes� The status of these interrupts can be read by executing RIM instruction.

� The masking or unmasking of RST 7.5, RST 6.5 and RST 5.5 interrupts can be performed bymoving an 8-bit data to accumulator and then executing SIM instruction.

� The status of pending interrupts can be read from accumulator after executing RIMinstruction.

� When RIM instruction is executed an 8-bit data is loaded in accumulator, which can beinterpreted as shown in Figure 14.4.

Source: http://www.8085projects.info/images/Interrupt-Pic4-Pic50.png

Self Assessment

Fill in the blanks:

8. …………………… is the block which controls different interrupts coming from the externaldevices associated to the 8085 microprocessor by checking their priority order and sendsdifferent interrupts one by one to the 8085 microprocessor for interrupt service.

9. To enable the interrupt process, use the …………………… instruction.

10. An …………………… is a pointer to where the ISR is retained in memory.

11. All interrupts are mapped up on a memory area called the …………………….

12. The aim of the …………………… is to contain the vectors that forward the microprocessorto the right location when an interrupt arrives.

13. The 8085 provide additional …………………… for RST 7.5, RST 6.5 and RST 5.5 using SIMinstruction.

14. The status of …………………… interrupts can be read from accumulator after executingRIM instruction.

15. When RIM instruction is executed an …………………… data is loaded in accumulator.

Figure 14.4: 8-bit Data when RIM is Executed



Notes

�Case Study Automatic Verification of External Interrupt

Behaviours for Microprocessor Design

Interrupt behaviours, particularly the external ones, are difficult to verify in amicroprocessor. Because the external interrupt arrival time and the microprocessorresponse time must be precise, verification requires sophisticated hardware and

software design. This paper proposes a computer-aided design tool, called processorexception verification tool (PEVT), to verify the external interrupt behaviours ofmicroprocessors, including individual, multiple, and nested interrupts. An architecturedescription language extension, called Exception Description Language (EXPDL), isdeveloped for the designer to capture the external interrupt behaviours for themicroprocessor under verification. PEVT is responsible for generating the verificationcases, consisting of both the hardware and software modules, which are then used totrigger the expected behaviours. A monitor is also generated from the EXPDL descriptionto verify these cases. PEVT has been applied to the verification of an academicimplementation of the ARM7 microprocessor core and a public domain scalable processorarchitecture (SPARC) microprocessor core. The ARM7 has had a system-on-a-chip test chipand software porting including multimedia applications (MP3/JPEG/...) and a real timeoperating system muC-OSII. PEVT successfully identified several sophisticated remainingbugs with 527 lines of EXPDL description and took only 4 204 961 cycles of register transferlanguage simulation with execution time of 4.5 h in a SUN Blade2000 workstation. Theexperiment shows that PEVT could generate highly focused verification cases, less than 98cycles per case on the average, which identify potential bugs with much less simulationcycles at the early verification stage, compared with traditional manual-based approaches.

Questions:

1. What did you understand to PEVT?

2. Explain the concept of interrupts behaviour.

14.3 Summary

� Interrupt is a process by which an I/O or an instruction can suspend the usual execution ofprocessor and get itself serviced.

� Interrupt signals can cause a program to suspend itself for the time being to service theinterrupt.

� The process of ending any interrupt is known as Interrupt Service.

� PCs support 256 types of software and 15 types of hardware interrupts.

� Maskable Interrupt are the interrupts which can be Masked-off or can be made pending fora while are known as Maskable Interrupts.

� Non-Maskable Interrupt are the interrupts which cannot be Masked-off or cannot be madepending for a while are known as Non-Maskable Interrupts.

� When TRAP interrupt is introduced to the microprocessor the microprocessor will transferits control to location number 0024H in the memory.

� When RST 7.5 (Reset 7.5) interrupt is introduced to the microprocessor the microprocessorwill transfer its control to location number 003CH in the memory.


Unit 14: Interrupts

Notes� When RST 6.5 (Reset 6.5) interrupt is introduced to the microprocessor the microprocessorwill transfer its control to location number 0034H in the memory.

� When RST 5.5 (Reset 5.5) interrupt is introduced to the microprocessor the microprocessorwill transfer its control to location number 002CH in the memory.

� An interrupt vector is a pointer to where the ISR is retained in memory.

14.4 Keywords

Interrupt: A process by which an I/O or an instruction can suspend the usual execution ofprocessor and get itself serviced.

Interrupt Service: The process of ending any interrupt.

Maskable Interrupt: The interrupts which can be Masked-off or can be made pending for a whileare known as Maskable Interrupts.

Non-Maskable Interrupt: The interrupts which cannot be Masked-off or cannot be made pendingfor a while are known as Non-Maskable Interrupts.

RST 5.5 (Reset 5.5): When this interrupt is introduced to the microprocessor the microprocessorwill transfer its control to location number 002CH in the memory.

RST 6.5 (Reset 6.5): When this interrupt is introduced to the microprocessor the microprocessorwill transfer its control to location number 0034H in the memory.

RST 7.5 (Reset 7.5): When this interrupt is introduced to the microprocessor the microprocessorwill transfer its control to location number 003CH in the memory.

TRAP Interrupt: When this interrupt is introduced to the microprocessor the microprocessorwill transfer its control to location number 0024H in the memory.


1. Explain interrupts and its various types.

2. Discuss interrupts in 8085 Microprocessor.

3. Differentiate between maskable and non-maskable interrupts.

4. Define TRAP interrupts.

5. Interrupt pointers can arrive from different kind of sources. Explain.

6. What are vectored and non-vectored interrupts?

7. Write a short note on interrupt controller.

8. Describe different types of Interrupts.

9. What are Issues in Implementing INTR Interrupts?

10. Discuss about Interrupt Vectors and the Vector Table.


1. Interrupt 2. program

3. Interrupt Service Routine (ISR) 4. vectored

5. non-vectored 6. non-maskable



Notes 7. RST 6.5. 8. Interrupt Controller

9. EI 10. Interrupt vector

11. IVT 12. IVT

13. masking facility 14. pending

15. 8-bit





Online links http://www.8085projects.info/

ieeexplore.ieee.org/iel5/43/4603069/04603091.pdf?arnumber=4603091

dylucknow.weebly.com/uploads/6/7/3/1/6731187/8085_interrupts.pdf

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Introduction to Microprocessorsebooks.lpude.in/computer_application/ad/DCAP210_INTRODUCTION… · Interfacing I/O Devices: Basic interfacing Concepts, Interfacing output displays,

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