Hyperstone S6 Flash Memory Controller Specification

Hyperstone S632-Bit Flash Memory Controller

User’s Manual

Revision 06/09 D1A

Specifications and information in this document are subject to change without notice and do not represent a commitment on the part of Hyperstone GmbH. Hyperstone GmbH reserves the right to make changes to improve functioning. Although the information in this document has been carefully reviewed, Hyperstone GmbH does not assume any liability arising out of the use of the product or circuit described herein.

Hyperstone GmbH does not authorize the use of the Hyperstone microprocessor in life support applications wherein a failure or malfunction of the microprocessor may directly threaten life or cause injury. The user of the Hyperstone microprocessor in life support applications assumes all risks of such use and indemnifies Hyperstone AG against all damages.

No part of this manual may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photo-copying and recording, for any purpose without the permission of Hyperstone GmbH.

Hyperstone is a registered trademark of Hyperstone GmbH.

For further information please contact:

Hyperstone GmbH Line-Eid-Strasse 3 78467 Konstanz Germany Phone: +49 7531 98030 Fax: +49 7531 51725 Email: [email protected]

Hyperstone Inc. - USA 465 Corporate Square Drive Winston-Salem, NC 27105 USA Phone: +1 336 744 0724 Fax: +1 336 744 5054 Email: [email protected]

Hyperstone Asia Pacific - Taiwan 3F., No. 501, Sec.2, Tiding Blvd. Neihu District, Taipei City 114 Taiwan, R.O.C. Phone: +886 2 8751 0203 Fax: +886 2 8797 2321 Email: [email protected]

www.hyperstone.com

Copyright 1990, 2009 Hyperstone GmbH

Revision 06/09 D1A

http://www.hyperstone.com/

3

Table of Contents

Revision History ............................................................................................. 5

1. Features ................................................................................................ 6

1.1. Host Interface...........................................................................................6 1.2. Flash Memory Interface ...........................................................................6 1.3. Controller Core ........................................................................................6

2. General Description ............................................................................... 7

3. Pin Configuration ................................................................................... 9

3.1. Hyperstone S6, 128-Pin LQFP Package ..................................................9 3.1.1. Pin Configuration - View from Top Side................................9 3.1.2. Pin Cross Reference by Pin Name ........................................10 3.1.3. Pin Cross Reference by Location..........................................11

3.2. Hyperstone S6, 128-Pin TQFP Package ................................................12 3.2.1. Pin Configuration - View from Top Side..............................12 3.2.2. Pin Cross Reference by Pin Name ........................................13 3.2.3. Pin Cross Reference by Location..........................................14

3.2. Hyperstone S6, 54-Pin LGA Package....................................................15 3.2.1. Pin Configuration - View from Top Side..............................15 3.2.2. Pin Cross Reference by Pin Name ........................................16 3.2.3. Pin Cross Reference by Location..........................................16

3.4. Hyperstone S6, 58-Pin LGA Package....................................................17 3.4.1. Pin Configuration - View from Top Side..............................17 3.4.2. Pin Cross Reference by Pin Name ........................................18 3.4.3. Pin Cross Reference by Location..........................................18

3.5. Hyperstone S6 Die .................................................................................19 3.5.1. Pad Configuration .................................................................19 3.5.2. Pad Cross Reference by Pad Name.......................................20 3.5.3. Pad Cross Reference by Pad Number ...................................22

3.6. Package Dimensions ..............................................................................24 3.6.1. 128-Pin LQFP and TQFP Package .......................................24 3.6.2. 54-Pin LGA Package ............................................................26 3.6.3. 58-Pin LGA Package ............................................................28

3.7. Bus Signals.............................................................................................30 3.7.1. Bus Signals for the S6 Flash Memory Controller .................30 3.7.2. Bus Signal Description .........................................................31

4. Functional Description ......................................................................... 35

4.1. Block Diagram .......................................................................................35 4.2. System Memory Map.............................................................................35 4.3. Flash Memory Interface .........................................................................36 4.4. Reset and ROM Boot .............................................................................36

4.4.1. Boot Selection on Reset ........................................................36 4.4.2. Internal ROM Boot Process ..................................................36

4.5. S6 Controller Revisions .........................................................................38 4.6. Example Schematics ..............................................................................38

5. Electrical Specifications ....................................................................... 40

4

5.1. DC Characteristics .................................................................................40 5.2. AC Characteristics .................................................................................41

5.2.1. SD Interface AC Characteristics, Low Speed Mode ............41 5.2.2. SD Interface AC Characteristics, High Speed Mode ...........41 5.2.3. Flash Memory Interface AC Characteristics ........................42

Ordering Information .................................................................................... 44

5

Revision History Revision Change History Date

10/2006 Initial release October 27, 2006

05/2007 Pin-out information, other small changes May 7, 2007

07/2007 LQFP pin-out error corrected, LGA54 layout change, LGA54 package specs added, VDDC capacitor change, pad 46..58 coordinates changed

November 14, 2007

01/2008 Ordering information updated January 11, 2008

06/2009 Add S6-LAT06Q, S6-LAK06 packages June 19, 2009

6 FEATURES

1. Features

1.1. Host Interface

❒ Compliant to the SD standards rev. 1.01, 1.10 and 2.0

❒ Compliant to the MMC standards rev. 3.31, 4.1 and 4.2

❒ Dual Voltage Support (1.8V and 3.3V)

❒ Four integrated 4 KByte Sector Buffers for fast data transfer

1.2. Flash Memory Interface

❒ Supports all control signal for NAND type flash memory connection

❒ Two separate flash memory channels for fully parallel operation of two flash chips

❒ Supports direct connection of up to 4 flash memory chips

❒ Supports all densities of NAND type flash memories on the market

❒ Flash memory power down logic and flash memory write protect control

❒ Firmware storage in flash memory

❒ Firmware is loaded into internal memory by the boot ROM

❒ Error Correcting Code capable of correcting four bytes in a 512 byte sector

❒ On-chip voltage regulator for 1.8V processor core power supply

❒ On-chip voltage regulator for 1.8V flash memory power supply (optional)

❒ On-chip charge pump for 3.0V flash memory power supply in low voltage hosts

1.3. Controller Core

❒ High performance microprocessor core based on the Hyperstone architecture

❒ Clock frequency from 10 MHz to 60MHz using trimmable internal oscillator

❒ 16 Kbyte internal Boot ROM

❒ 20 Kbyte internal RAM

❒ Automatic power-down mode during wait periods for host data or flash memory operation completion

❒ Automatic sleep mode during host inactivity periods, Icc < 100 µA

❒ 54-pin and 58-pin LGA (7.5×4×0.7 mm) package, 128-pin TQFP (14×14×1.0 mm) package for internal engineering purposes

❒ 0.18 µm CMOS technology

❒ Supply voltage 1.65V to 1.95V and 2.7V to 3.6V (2.0V to 3.6V for identification)

GENERAL DESCRIPTION 7

2. General Description The Hyperstone S6 flash memory controllers are among the most powerful single-chip controllers on the market for designing SD and MMC Flash Memory Cards. The required external component count is reduced to a bare minimum of few passive components enabling the design of very low-cost but high-performance SD and MMC Cards. Highest performance is achieved through the two independent flash memory access channels.

The Hyperstone S6 flash memory controller can operate with flash memory devices from Samsung or compatible chips thereof. It operates with a supply voltage of 1.8V or 3.3V. A highly sophisticated Error Correction Code and a wear-leveling algorithm are implemented. A complete set of development tools is available which enables you to design SD Cards with a very competitive cost/performance ratio.

The main features of Hyperstone S6 flash memory controller are:

❒ Inexpensive single-chip controller for SD and MMC flash memory cards

❒ NAND type flash memory interface

❒ Compatible to SLC and MLC NAND flash memories including Samsung, Hynix, Micron, Toshiba, Intel, and others

❒ Large page buffers enable optimum performance for flash chips with 4KB page size

❒ Supports two independent flash memory access channels

❒ Supports interleaved operation of two flash memory chips on the same memory channel

❒ Built-in 1.8V voltage regulator for flash memory supply (optional)

❒ Built-in 1.8V voltage regulator for processor core supply

❒ Built-in charge pump for 3.0V flash memory power supply in low voltage hosts

❒ Built-in SD and MMC Card Interface

❒ Data transfer rate to flash memories: up to 40 MBytes/s per channel

❒ On-chip ECC and CRC16 units for flash data protection

❒ Hardware support for the C2 encryption and decryption routines (CPRM)

❒ Sophisticated software for wear leveling

❒ Automatic power-down mode and sleep mode

❒ Small 54-pin or 58-pin LGA package

❒ also available as a bare die

❒ Comprehensive equipment available for development and test of hardware and firmware

The Hyperstone S6 single-chip controller for SD and MMC Flash Memory Cards is based on the Hyperstone E1-32X microprocessor core providing a modern 32-bit RISC architecture. The controller’s flash memory interface allows the direct connection of up to four flash memory chips, either connected to a single channel, or up to two flash memory chips on each of two separate flash access channels. The Hyperstone S6 supports NAND type flash memories of any density. Through the sophisticated memory interface of the Hyperstone S6, your flash memory card will achieve a superior performance with a data transfer rate to flash memories of up to 40 MBytes/s per channel. An on-chip ECC and

8 GENERAL DESCRIPTION

CRC16 unit generates the required code bytes for error detection and correction of up to four random bytes per 512 Byte data sector. Code byte generation during write operations as well as error detection during read operation is implemented on the fly without any speed penalties. ECC correction is done in software with special hardware support.

The controller is equipped with 20 KByte internal memory that is used for storage of code and data. The internal memory can also be used as an intermediate memory for storing data blocks during flash memory operations.

Each flash memory channel is equipped with two page buffers of 4KB each, in order to provide optimum read and write performance for flash chips with page sizes up to 4KB.

The Hyperstone S6 controller works at a power supply voltage of 1.65V to 1.95V or 2.7V to 3.3V. It provides a built-in voltage regulator of 1.8V for the processor core power supply. Using the built-in charge pump, 3.0V flash memory power supply is available even in low-voltage host environments.

A 16 KByte internal boot ROM includes basic routines for accessing the flash memories and for loading the main code into the internal memory of the Hyperstone S6. This boot concept offers a high degree of flexibility while keeping the component count small.

The SD and MMC interface provides all required signals and is fully compliant with the SD Card standards rev. 1.01, 1.10 and 2.0, and with the MMC standards rev. 3.31, 4.1 and 4.2. The SD/MMC Card controller part of the Hyperstone S6 includes the SD and MMC card configuration and status registers as well as four 4 KByte sector buffers.

A comprehensive tool kit is also available for developing and testing SD or MMC Flash Memory Cards based on the Hyperstone S6. This includes a hardware/software test environment, pre-format hardware and software, and controller firmware.

PIN CONFIGURATION 9

3. Pin Configuration

3.1. Hyperstone S6, 128-Pin LQFP Package

This package is for Hyperstone internal engineering purposes only. Please contact Hyperstone if you intend to use this package.

3.1.1. Pin Configuration - View from Top Side

hyFlashS6-LAL06

979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128

VDDF

VIN_CP

CFLYN

VDDF_CVCC3HVDDC

VDDC_C

VSSSLETXSLERX

SLEVCCRESET#

VSS

SLERSTVCC3H

SLECLK

90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 659192939495961 2 3 4 6 7 8 9 10 11 125 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

MO

DE

SDD

AT2

SDD

AT0

VC

C3H

SDD

AT1

SDC

LKV

CC

3H

VC

C3H

SDD

AT6

SDD

AT5

F0C

S1#

F0C

S0#

F0O

E#VC

C3F

F0R

DY1

F0R

DY0

F0D

7F0

D6

VCC

3FF0

D5

F0D

4F0

D3

F0D

2F0

D1

F0D

0

SDC

MD

SDD

AT7

60595857565554535251504948474645444342414039383736353433

61626364

VSS

VSSSCANOUT2F0CLEF0ALEF0WE#

CPE

N

VCC3F

VSS

SDD

AT4

VSS

VSS

FWP#

DU

ALM

OD

E2

VDDF

CFLYNVDD_CPVDD_CP

VIN_CPCFLYPCFLYP

VSSVSS

SDD

AT3

VSS

VINFVINF

VSS

VSS

SC

ANO

UT1

VC

C3H

VC

C3H

XTA

LSEL

XTA

LIIN

T4F1

CLE

F1AL

EF1

WE#

F1D

0V

CC

3FF1

D1

F1D

2F1

D3

F1D

4V

CC

3FF1

D5

F1D

6F1

D7

VC

C3F

F1R

DY

0F1

RD

Y1

F1O

E#F1

CS0

#F1

CS1

#U

AR

T_R

XU

AR

T_TX

UA

RT_

CLK

VC

C3H

Figure 7.1: Hyperstone S6, 128-Pin LQFP Package

10 PIN CONFIGURATION

3.1.2. Pin Cross Reference by Pin Name

Signal Location Signal Location Signal Location Signal Location

CFLYN............110 F1D1................. 79 SDDAT6 ........... 15 VDDC ................118 CFLYN............111 F1D2................. 80 SDDAT7 ........... 12 VDDC_C............119 CFLYP ............104 F1D3................. 81 SLECLK.......... 128 VDDF.................114 CFLYP ............105 F1D4................. 82 SLERST.......... 126 VDDF.................115 CPEN.................. 3 F1D5................. 84 SLERX............ 125 VDDF_C ............116 DUAL .................. 2 F1D6................. 85 SLETX ............ 124 VIN_CP .............108 F0ALE............... 36 F1D7................. 86 SLEVCC ......... 120 VIN_CP .............109 F0CLE............... 37 F1OE# .............. 90 UART_CLK....... 95 VINF ..................112 F0CS0# ............ 19 F1RDY0............ 88 UART_RX......... 93 VINF ..................113 F0CS1# ............ 18 F1RDY1............ 89 UART_TX ......... 94 VSS ...................122 F0D0................. 32 F1WE#.............. 76 VCC3F.............. 21 VSS ...................123 F0D1................. 31 FWP#................ 33 VCC3F.............. 26 VSS .....................39 F0D2................. 30 INT4.................. 73 VCC3F.............. 34 VSS .....................40 F0D3................. 29 MODE................. 4 VCC3F.............. 78 VSS .....................41 F0D4................. 28 MODE2............... 1 VCC3F.............. 83 VSS .....................42 F0D5................. 27 RESET#.......... 121 VCC3F.............. 87 VSS .....................64 F0D6................. 25 SCANOUT1...... 68 VCC3H ............... 6 VSS .....................65 F0D7................. 24 SCANOUT2...... 38 VCC3H ............. 10 VSS .....................66 F0OE# .............. 20 SDCLK.............. 13 VCC3H ............. 14 VSS .....................97 F0RDY0............ 23 SDCMD .............. 8 VCC3H ............. 69 VSS .....................98 F0RDY1............ 22 SDDAT0 ............. 9 VCC3H ............. 70 VSS .....................99 F0WE#.............. 35 SDDAT1 ........... 11 VCC3H ............. 96 XTALI ..................72 F1ALE............... 75 SDDAT2 ............. 5 VCC3H ........... 117 XTALSEL.............71 F1CLE............... 74 SDDAT3 ............. 7 VCC3H ........... 127 n.c.................43...63 F1CS0# ............ 91 SDDAT4 ........... 17 VDD_CP......... 106 n.c........................67 F1CS1# ............ 92 SDDAT5 ........... 16 VDD_CP......... 107 n.c.............100...103 F1D0................. 77

PIN CONFIGURATION 11

3.1.3. Pin Cross Reference by Location

Location Signal Location Signal Location Signal Location Signal

1............... MODE2 28................. F0D4 74 .............. F1CLE 100…103........... n.c. 2.................. DUAL 29................. F0D3 75 .............. F1ALE 104 .............. CFLYP 3.................. CPEN 30................. F0D2 76 ............. F1WE# 105 .............. CFLYP 4................. MODE 31................. F0D1 77 ................ F1D0 106 ........... VDD_CP 5..............SDDAT2 32................. F0D0 78 ............. VCC3F 107 ........... VDD_CP 6................VCC3H 33................ FWP# 79 ................ F1D1 108 .............VIN_CP 7..............SDDAT3 34.............. VCC3F 80 ................ F1D2 109 .............VIN_CP 8...............SDCMD 35.............. F0WE# 81 ................ F1D3 110 .............. CFLYN 9..............SDDAT0 36............... F0ALE 82 ................ F1D4 111 .............. CFLYN 10..............VCC3H 37...............F0CLE 83 ............. VCC3F 112 ..................VINF 11............SDDAT1 38...... SCANOUT2 84 ................ F1D5 113 ..................VINF 12............SDDAT7 39...................VSS 85 ................ F1D6 114 ................ VDDF 13.............. SDCLK 40...................VSS 86 ................ F1D7 115 ................ VDDF 14..............VCC3H 41...................VSS 87 ............. VCC3F 116 ........... VDDF_C 15............SDDAT6 42...................VSS 88 ........... F1RDY0 117 ..............VCC3H 16............SDDAT5 43...63............. n.c. 89 ........... F1RDY1 118 ................VDDC 17............SDDAT4 64...................VSS 90 ..............F1OE# 119 ........... VDDC_C 18.............F0CS1# 65...................VSS 91 ............ F1CS0# 120 ........... SLEVCC 19.............F0CS0# 66...................VSS 92 ............ F1CS1# 121 ............RESET# 20...............F0OE# 67.................... n.c. 93 ........ UART_RX 122 ...................VSS 21.............. VCC3F 68...... SCANOUT1 94 .........UART_TX 123 ...................VSS 22............ F0RDY1 69..............VCC3H 95 ...... UART_CLK 124 ...............SLETX 23............ F0RDY0 70..............VCC3H 96 .............VCC3H 125 .............. SLERX 24................. F0D7 71.......... XTALSEL 97 .................. VSS 126 ............SLERST 25................. F0D6 72................ XTALI 98 .................. VSS 127 ..............VCC3H 26.............. VCC3F 73.................. INT4 99 .................. VSS 128 ............ SLECLK 27................. F0D5


3.2. Hyperstone S6, 128-Pin TQFP Package

This package is for Hyperstone internal engineering purposes only. Please contact Hyperstone if you intend to use this package.


hyFlashS6-LAT06Q

979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128

VDDF

VDD_CP

VDDF_CVCC3HVDDC

VDDC_C

VSS

SLETXSLERX

SLEVCCRESET#

VSS

SLERSTSLECLK

90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 659192939495961 2 3 4 6 7 8 9 10 11 125 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

SDD

AT2

SDD

AT0

VC

C3H

SDD

AT1

SDC

LKV

CC

3H

VC

C3H

SDD

AT6

SDD

AT5

F0C

S1#

F0C

S0#

F0O

E#VC

C3F

F0R

DY1

F0R

DY0

F0D

7F0

D6

VCC

3FF0

D5

F0D

4F0

D3

F0D

2F0

D1

F0D

0

SDC

MD

SDD

AT7

60595857565554535251504948474645444342414039383736353433

61626364

VSS

VSSSCANOUT2F0CLEF0ALEF0WE#

VSS

SDD

AT4

VSS

CFLYN

VIN_CPCFLYP

VSSVSS

SDD

AT3

VSS

VINF

SC

ANO

UT1

SC

ANIN

2

VC

C3H

XTA

LSEL

XTA

LIIN

T4S

CAN

MO

DE

F1AL

EF1

WE#

F1D

0V

CC

3FF1

D1

F1D

2F1

D3

F1D

4V

CC

3FF1

D5

F1D

6F1

D7

VC

C3F

F1R

DY

0F1

RD

Y1

F1O

E#F1

CS0

#F1

CS1

#

FWP#

VCC

3F

VSS

VSSVSS

B_TEST

B_SHDRB_RUN

B_MRSIB_MBRUN

B_M

RSO

SC

ANEN

VC

C3H

SC

ANIN

1

F1C

LEVCC3H

UART_RXUART_TX

UART_CLK

VSS

MODE2DUALCPENMODE

Figure 7.2: Hyperstone S6, 128-Pin TQFP Package




B_MBRUN........ 61 F1CS0# ............ 93 SDDAT1 ............. 7 VDD_CP............107 B_MRSI ............ 62 F1CS1# ............ 94 SDDAT2 ............. 1 VDDC ................113 B_MRSO .......... 65 F1D0................. 79 SDDAT3 ............. 3 VDDC_C ...........114 B_RUN ............. 64 F1D1................. 81 SDDAT4 ........... 13 VDDF.................110 B_SHDR........... 63 F1D2................. 82 SDDAT5 ........... 12 VDDF_C............111 B_TEST............ 60 F1D3................. 83 SDDAT6 ........... 11 VIN_CP .............106 CFLYN............ 108 F1D4................. 84 SDDAT7 ............. 8 VINF ..................109 CFLYP............ 105 F1D5................. 86 SLECLK.......... 120 VSS .....................37 CPEN.............. 127 F1D6................. 87 SLERST ......... 119 VSS .....................38 DUAL .............. 126 F1D7................. 88 SLERX............ 118 VSS .....................39 F0ALE............... 34 F1OE# .............. 92 SLETX ............ 117 VSS .....................40 F0CLE .............. 35 F1RDY0............ 90 SLEVCC......... 115 VSS .....................57 F0CS0# ............ 17 F1RDY1............ 91 UART_CLK....... 99 VSS .....................58 F0CS1# ............ 16 F1WE# ............. 78 UART_RX......... 97 VSS .....................59 F0D0................. 30 FWP#................ 31 UART_TX......... 98 VSS ...................101 F0D1................. 29 INT4.................. 74 VCC3F.............. 19 VSS ...................102 F0D2................. 28 MODE............. 128 VCC3F.............. 24 VSS ...................103 F0D3................. 27 MODE2........... 125 VCC3F.............. 32 VSS ...................121 F0D4................. 26 RESET# ......... 116 VCC3F.............. 80 VSS ...................122 F0D5................. 25 SCANEN .......... 67 VCC3F.............. 85 VSS ...................123 F0D6................. 23 SCANIN1.......... 70 VCC3F.............. 89 XTALI ..................73 F0D7................. 22 SCANIN2.......... 69 VCC3H ............... 2 XTALSEL.............72 F0DRY0............ 21 SCANMODE..... 75 VCC3H ............... 6 n.c..................14..15 F0OE# .............. 18 SCANOUT1...... 66 VCC3H ............. 10 n.c..................41..56 F0RDY1............ 20 SCANOUT2...... 36 VCC3H ............. 68 n.c..................95..96 F0WE#.............. 33 SDCLK ............... 9 VCC3H ............. 71 n.c......................104 F1ALE............... 77 SDCMD .............. 4 VCC3H ........... 100 n.c......................124 F1CLE .............. 76 SDDAT0 ............. 5 VCC3H ........... 112




1..............SDDAT2 30................. F0D0 73................ XTALI 102 ...................VSS 2................VCC3H 31................ FWP# 74.................. INT4 103 ...................VSS 3..............SDDAT3 32.............. VCC3F 75..... SCANMODE 104 .................... n.c. 4...............SDCMD 33.............. F0WE# 76...............F1CLE 105 .............. CFLYP 5..............SDDAT0 34............... F0ALE 77............... F1ALE 106 .............VIN_CP 6................VCC3H 35...............F0CLE 78.............. F1WE# 107 ........... VDD_CP 7..............SDDAT1 36...... SCANOUT2 79................. F1D0 108 ..............CFLYN 8..............SDDAT7 37...................VSS 80.............. VCC3F 109 ..................VINF 9................SDCLK 38...................VSS 81................. F1D1 110 ................VDDF 10..............VCC3H 39...................VSS 82................. F1D2 111 ........... VDDF_C 11............SDDAT6 40...................VSS 83................. F1D3 112 ..............VCC3H 12............SDDAT5 41..56.............. n.c. 84................. F1D4 113 ................VDDC 13............SDDAT4 57...................VSS 85.............. VCC3F 114 ...........VDDC_C 14..15.............. n.c. 58...................VSS 86................. F1D5 115 ........... SLEVCC 16.............F0CS1# 59...................VSS 87................. F1D6 116 ............RESET# 17.............F0CS0# 60............ B_TEST 88................. F1D7 117 .............. SLETX 18...............F0OE# 61........ B_MBRUN 89.............. VCC3F 118 ..............SLERX 19.............. VCC3F 62.............B_MRSI 90............ F1RDY0 119 ............SLERST 20............ F0RDY1 63........... B_SHDR 91............ F1RDY1 120 ............SLECLK 21............ F0DRY0 64..............B_RUN 92...............F1OE# 121 ...................VSS 22................. F0D7 65...........B_MRSO 93.............F1CS0# 122 ...................VSS 23................. F0D6 66...... SCANOUT1 94.............F1CS1# 123 ...................VSS 24.............. VCC3F 67...........SCANEN 95..96.............. n.c. 124 .................... n.c. 25................. F0D5 68..............VCC3H 97......... UART_RX 125 .............MODE2 26................. F0D4 69.......... SCANIN2 98..........UART_TX 126 ................ DUAL 27................. F0D3 70.......... SCANIN1 99....... UART_CLK 127 ................CPEN 28................. F0D2 71..............VCC3H 100............VCC3H 128 ...............MODE 29................. F0D1 72.......... XTALSEL 101.................VSS


3.3. Hyperstone S6, 54-Pin LGA Package


1

2

3

4

5

6

7

10 11 12 13 14 15 16 17 18 19

30

31

32

33

505152 43444546474849

F0RDY0

F0D7

F0D6

F0D5

F0D4

F0D3

F0D2

VDDC

VDDF_C

VDDF

VCC3F

FWP#

F0W

E#

F0AL

E

F0C

LE

F1C

LE

F1AL

E

F1W

E#

F1D

0

F1D

1

F1D

2

F0C

S0#

F0O

E#

F0R

DY

1

SD

DAT

1

SD

DAT

7

SD

CLK

SD

DAT

6

SD

DAT

5

SD

DAT

4

F0C

S1#

29 F1CS1#

28 F1CS0#

27 F1OE#

20 21 22 23 24 25 26

F1D

3

F1D

4

F1D

5

F1D

6

F1D

7

F1R

DY

0

F1R

DY

1

404142 36373839

SD

DAT

3

SD

CM

D

SD

DAT

0

MO

DE

2

DU

AL

MO

DE

SD

DAT

2

53

VCC3H

54

VSS

8 9

F0D

1

F0D

0

3435

VD

DC

_C

RE

SET#

Figure 7.3: Hyperstone S6, 54-Pin LGA Package




DUAL ................ 37 F0RDY0.............. 1 F1D7................. 24 SDDAT3 ........... 40 F0ALE............... 12 F0RDY1............ 52 F1OE# .............. 27 SDDAT4 ........... 48 F0CLE............... 13 F0WE#.............. 11 F1RDY0............ 25 SDDAT5 ........... 47 F0CS0# ............ 50 F1ALE............... 15 F1RDY1............ 26 SDDAT6 ........... 46 F0CS1# ............ 49 F1CLE .............. 14 F1WE#.............. 16 SDDAT7 ........... 44 F0D0................... 9 F1CS0# ............ 28 FWP#................ 10 VCC3F.............. 30 F0D1................... 8 F1CS1# ............ 29 MODE............... 38 VCC3H ............. 53 F0D2................... 7 F1D0................. 17 MODE2............. 36 VDDC ............... 33 F0D3................... 6 F1D1................. 18 RESET#............ 35 VDDC_C........... 34 F0D4................... 5 F1D2................. 19 SDCLK.............. 45 VDDF................ 31 F0D5................... 4 F1D3................. 20 SDCMD ............ 41 VDDF_C ........... 32 F0D6................... 3 F1D4................. 21 SDDAT0 ........... 42 VSS .................. 54 F0D7................... 2 F1D5................. 22 SDDAT1 ........... 43 F0OE# .............. 51 F1D6................. 23 SDDAT2 ........... 39



1.............. F0RDY0 15............... F1ALE 29.............F1CS1# 43............SDDAT1 2................... F0D7 16.............. F1WE# 30.............. VCC3F 44............SDDAT7 3................... F0D6 17................. F1D0 31................ VDDF 45.............. SDCLK 4................... F0D5 18................. F1D1 32............VDDF_C 46............SDDAT6 5................... F0D4 19................. F1D2 33................VDDC 47............SDDAT5 6................... F0D3 20................. F1D3 34........... VDDC_C 48............SDDAT4 7................... F0D2 21................. F1D4 35............ RESET# 49.............F0CS1# 8................... F0D1 22................. F1D5 36............. MODE2 50.............F0CS0# 9................... F0D0 23................. F1D6 37.................DUAL 51...............F0OE# 10................FWP# 24................. F1D7 38............... MODE 52............ F0RDY1 11..............F0WE# 25............ F1RDY0 39............SDDAT2 53..............VCC3H 12...............F0ALE 26............ F1RDY1 40............SDDAT3 54................... VSS 13...............F0CLE 27...............F1OE# 41.............SDCMD 14...............F1CLE 28.............F1CS0# 42............SDDAT0


3.4. Hyperstone S6, 58-Pin LGA Package


1

2

3

4

5

6

7

10 11 12 13 14 15 16 17 18 19

30

31

32

33

505152 43444546474849

F0RDY0

F0D7

F0D6

F0D5

F0D4

F0D3

F0D2

VDDC

VDDF_C

VDDF

VCC3F

FWP#

F0W

E#

F0AL

E

F0C

LE

F1C

LE

F1AL

E

F1W

E#

F1D

0

F1D

1

F1D

2

F0C

S0#

F0O

E#

F0R

DY

1

SD

DAT

1

SD

DAT

7

SD

CLK

SD

DAT

6

SD

DAT

5

SD

DAT

4

F0C

S1#

29 F1CS1#

28 F1CS0#

27 F1OE#

20 21 22 23 24 25 26

F1D

3

F1D

4

F1D

5

F1D

6

F1D

7

F1R

DY

0

F1R

DY

1

404142 36373839

SD

DAT

3

SD

CM

D

SD

DAT

0

MO

DE

2

DU

AL

MO

DE

SD

DAT

2

53

VCC3H

54

VSS

8 9

F0D

1

F0D

0

3435

VD

DC

_C

RE

SET#

55

56 57

58

n.c.

n.c. n.c.

n.c.

Figure 7.4: Hyperstone S6, 58-Pin LGA Package




DUAL ................ 37 F0RDY0.............. 1 F1D7................. 24 SDDAT3 ........... 40 F0ALE............... 12 F0RDY1............ 52 F1OE# .............. 27 SDDAT4 ........... 48 F0CLE............... 13 F0WE#.............. 11 F1RDY0............ 25 SDDAT5 ........... 47 F0CS0# ............ 50 F1ALE............... 15 F1RDY1............ 26 SDDAT6 ........... 46 F0CS1# ............ 49 F1CLE .............. 14 F1WE#.............. 16 SDDAT7 ........... 44 F0D0................... 9 F1CS0# ............ 28 FWP#................ 10 VCC3F.............. 30 F0D1................... 8 F1CS1# ............ 29 MODE............... 38 VCC3H ............. 53 F0D2................... 7 F1D0................. 17 MODE2............. 36 VDDC ............... 33 F0D3................... 6 F1D1................. 18 RESET#............ 35 VDDC_C........... 34 F0D4................... 5 F1D2................. 19 SDCLK.............. 45 VDDF................ 31 F0D5................... 4 F1D3................. 20 SDCMD ............ 41 VDDF_C ........... 32 F0D6................... 3 F1D4................. 21 SDDAT0 ........... 42 VSS .................. 54 F0D7................... 2 F1D5................. 22 SDDAT1 ........... 43 n.c............... 55..58 F0OE# .............. 51 F1D6................. 23 SDDAT2 ........... 39



1.............. F0RDY0 15............... F1ALE 29.............F1CS1# 43............SDDAT1 2................... F0D7 16.............. F1WE# 30.............. VCC3F 44............SDDAT7 3................... F0D6 17................. F1D0 31................ VDDF 45.............. SDCLK 4................... F0D5 18................. F1D1 32............VDDF_C 46............SDDAT6 5................... F0D4 19................. F1D2 33................VDDC 47............SDDAT5 6................... F0D3 20................. F1D3 34........... VDDC_C 48............SDDAT4 7................... F0D2 21................. F1D4 35............ RESET# 49.............F0CS1# 8................... F0D1 22................. F1D5 36............. MODE2 50.............F0CS0# 9................... F0D0 23................. F1D6 37.................DUAL 51...............F0OE# 10................FWP# 24................. F1D7 38............... MODE 52............ F0RDY1 11..............F0WE# 25............ F1RDY0 39............SDDAT2 53..............VCC3H 12...............F0ALE 26............ F1RDY1 40............SDDAT3 54................... VSS 13...............F0CLE 27...............F1OE# 41.............SDCMD 55..58 ............. n.c. 14...............F1CLE 28.............F1CS0# 42............SDDAT0


3.5. Hyperstone S6 Die

3.5.1. Pad Configuration

SLE

VC

CV

SS

VD

DC

_C

VC

C3H

VD

DF_

CV

DD

F

CFL

YN

VD

D_C

P

VIN

_CP

SCANOUT2F0CLEF0ALEF0WE#VCC3F

F0D0F0D1F0D2

VCC3F

F0D6F0D7F0RDY0 (IO1)F0RDY1VCC3FVSSF0OE#F0CS0#F0CS1#SDDAT4SDDAT5SDDAT6

464749505253565758

81828384

87

8586

8889909192939495

107

9796

9899

100101102103104105106

109

110

111

VCC3HVSSSDCLKSDDAT7SDDAT1VCC3HVSSSDDAT0SDCMDSDDAT3VCC3HVSSVSS

MODE (IO3)CPEN (IO4)

6667

108

68

80

7069

717273747576777879

VSSVCC3H

DUAL (IO5)

60

61

62

VS

S

CFL

YP

48R

ES

ET#

59

SDDAT2VCC3H

F0D4F0D3

FWP# (IO2)VSS

Die size:X = 4120 µmY = 1820 µmnot including seal ringand scribe line

Seal ring width: 8.76 µmScribe line width: 100 µm

Pad openingpads 46..52: 90 x 51 µmother pads: 51 x 51 µm

636465

MODE2 (IO6)

SLERSTSLERXSLETX

VSS

SLECLK

VIN

F

5154

VD

DC

55

24232221

18

2019

1716151413121110

89

76

393837

25

3536

343332313029282726

45

44

43

424140

5

3

4

2

1

VCC3HVSS

UART_CLKUART_TXUART_RX

F1CS1#F1CS0#F1OE#

F1RDY1F1RDY0VCC3F

VSSF1D7F1D6F1D5

VCC3FVSS

F1D4F1D3F1D2F1D1

VCC3FVSS

F1D0F1WE#F1ALEF1CLE

SCANMODEINT4

XTALIXTALSEL

VCC3HVSS

SCANIN1SCANIN2

VCC3HVSS

SCANENSCANOUT1

B_MRSOB_RUN

B_SHDRB_MRSI

B_MBRUNB_TEST

F0D5

Figure 7.5: Hyperstone S6 Die


3.5.2. Pad Cross Reference by Pad Name

Signal Location X Y Signal Location X Y

B_MBRUN .......... 2 ...... 110.000 ..... 28.000 SCANEN.............8 ...... 570.000...... 28.000 B_MRSI .............. 3 ...... 190.000 ..... 28.000 SCANIN1 ..........12 ...... 870.000...... 28.000 B_MRSO ............ 6 ...... 420.000 ..... 28.000 SCANIN2 ..........11 ...... 795.000...... 28.000 B_RUN ............... 5 ...... 345.000 ..... 28.000 SCANMODE .....18 .... 1395.000...... 28.000 B_SHDR ............. 4 ...... 270.000 ..... 28.000 SCANOUT1 ........7 ...... 495.000...... 28.000 B_TEST .............. 1 ........ 30.000 ..... 28.000 SCANOUT2 ....111 ........ 30.000.. 1792.000 CFLYN.............. 50 .... 4092.000 ... 826.405 SDCLK..............82 .... 2166.000.. 1792.000 CFLYP .............. 46 .... 4092.000 ... 327.585 SDCMD.............76 .... 2700.000.. 1792.000 CPEN................ 68 .... 3310.000 . 1792.000 SDDAT0............77 .... 2599.000.. 1792.000 DUAL ................ 67 .... 3375.000 . 1792.000 SDDAT1............80 .... 2368.000.. 1792.000 F0ALE.............109 ...... 190.000 . 1792.000 SDDAT2............70 .... 3162.000.. 1792.000 F0CLE.............110 ...... 110.000 . 1792.000 SDDAT3............75 .... 2801.000.. 1792.000 F0CS0# ............ 89 .... 1570.000 . 1792.000 SDDAT4............87 .... 1733.000.. 1792.000 F0CS1# ............ 88 .... 1635.000 . 1792.000 SDDAT5............86 .... 1834.000.. 1792.000 F0D0...............104 ...... 530.000 . 1792.000 SDDAT6............85 .... 1935.000.. 1792.000 F0D1...............103 ...... 595.000 . 1792.000 SDDAT7............81 .... 2267.000.. 1792.000 F0D2...............102 ...... 660.000 . 1792.000 SLECLK ............65 .... 3505.000.. 1792.000 F0D3...............101 ...... 725.000 . 1792.000 SLERST............62 .... 3714.000.. 1792.000 F0D4...............100 ...... 790.000 . 1792.000 SLERX ..............61 .... 3794.000.. 1792.000 F0D5................. 99 ...... 855.000 . 1792.000 SLETX...............60 .... 3874.000.. 1792.000 F0D6................. 96 .... 1115.000 . 1792.000 SLEVCC............58 .... 4092.000.. 1443.905 F0D7................. 95 .... 1180.000 . 1792.000 UART_CLK .......43 .... 3395.000...... 28.000 F0OE# .............. 90 .... 1505.000 . 1792.000 UART_RX .........41 .... 3245.000...... 28.000 F0RDY0............ 94 .... 1245.000 1792. 000 UART_TX..........42 .... 3320.000...... 28.000 F0RDY1............ 93 .... 1310.000 . 1792.000 VCC3F ..............24 .... 1870.000...... 28.000 F0WE#............108 ...... 270.000 . 1792.000 VCC3F ..............30 .... 2320.000...... 28.000 F1ALE............... 20 .... 1570.000 ..... 28.000 VCC3F ..............35 .... 2770.000...... 28.000 F1CLE............... 19 .... 1495.000 ..... 28.000 VCC3F ..............92 .... 1375.000.. 1792.000 F1CS0# ............ 39 .... 3070.000 ..... 28.000 VCC3F ..............98 ...... 920.000.. 1792.000 F1CS1# ............ 40 .... 3145.000 ..... 28.000 VCC3F ............107 ...... 335.000.. 1792.000 F1D0................. 22 .... 1720.000 ..... 28.000 VCC3H..............10 ...... 720.000...... 28.000 F1D1................. 25 .... 1945.000 ..... 28.000 VCC3H..............14 .... 1095.000...... 28.000 F1D2................. 26 .... 2020.000 ..... 28.000 VCC3H..............45 .... 3545.000...... 28.000 F1D3................. 27 .... 2095.000 ..... 28.000 VCC3H..............54 .... 4092.000.. 1163.905 F1D4................. 28 .... 2170.000 ..... 28.000 VCC3H..............63 .... 3634.000.. 1792.000 F1D5................. 31 .... 2395.000 ..... 28.000 VCC3H..............71 .... 3079.000.. 1792.000 F1D6................. 32 .... 2470.000 ..... 28.000 VCC3H..............74 .... 2884.000.. 1792.000 F1D7................. 33 .... 2545.000 ..... 28.000 VCC3H..............79 .... 2451.000.. 1792.000 F1OE# .............. 38 .... 2995.000 ..... 28.000 VCC3H..............84 .... 2018.000.. 1792.000 F1RDY0............ 36 .... 2845.000 ..... 28.000 VDD_CP ...........49 .... 4092.000.... 717.585 F1RDY1............ 37 .... 2920.000 ..... 28.000 VDDC................55 .... 4092.000.. 1223.905 F1WE#.............. 21 .... 1645.000 ..... 28.000 VDDC_C ...........56 .... 4092.000.. 1283.905 FWP#..............105 ...... 465.000 . 1792.000 VDDF ................52 .... 4092.000.. 1024.405 INT4.................. 17 .... 1320.000 ..... 28.000 VDDF_C............53 .... 4092.000.. 1103.905 MODE............... 69 .... 3245.000 . 1792.000 VIN_CP.............48 .... 4092.000.... 587.585 MODE2............. 66 .... 3440.000 . 1792.000 VINF..................51 .... 4092.000.... 925.405 RESET#............ 59 .... 4092.000 . 1574.000 VSS.....................9 ...... 645.000...... 28.000


3.5.2. Pad Cross Reference by Pad Name (continued)


VSS .................. 13.....1020.000 ......28.000 VSS...................73 .... 2949.000.. 1792.000 VSS .................. 23.....1795.000 ......28.000 VSS...................78 .... 2516.000.. 1792.000 VSS .................. 29.....2245.000 ......28.000 VSS...................83 .... 2083.000.. 1792.000 VSS .................. 34.....2695.000 ......28.000 VSS...................91 .... 1440.000.. 1792.000 VSS .................. 44.....3470.000 ......28.000 VSS...................97 ...... 985.000.. 1792.000 VSS .................. 47.....4092.000 ....457.585 VSS.................106 ...... 400.000.. 1792.000 VSS .................. 57.....4092.000 ..1363.905 XTALI................16 .... 1245.000...... 28.000 VSS .................. 64.....3570.000 ..1792.000 XTALSEL ..........15 .... 1170.000...... 28.000 VSS .................. 72.....3014.000 ..1792.000


3.5.3. Pad Cross Reference by Pad Number


B_TEST .............. 1 ........ 30.000 ..... 28.000 VIN_CP.............48 .... 4092.000.... 587.585 B_MBRUN .......... 2 ...... 110.000 ..... 28.000 VDD_CP ...........49 .... 4092.000.... 717.585 B_MRSI .............. 3 ...... 190.000 ..... 28.000 CFLYN ..............50 .... 4092.000.... 826.405 B_SHDR ............. 4 ...... 270.000 ..... 28.000 VINF..................51 .... 4092.000.... 925.405 B_RUN ............... 5 ...... 345.000 ..... 28.000 VDDF ................52 .... 4092.000.. 1024.405 B_MRSO ............ 6 ...... 420.000 ..... 28.000 VDDF_C............53 .... 4092.000.. 1103.905 SCANOUT1 ........ 7 ...... 495.000 ..... 28.000 VCC3H..............54 .... 4092.000.. 1163.905 SCANEN............. 8 ...... 570.000 ..... 28.000 VDDC................55 .... 4092.000.. 1223.905 VSS..................... 9 ...... 645.000 ..... 28.000 VDDC_C ...........56 .... 4092.000.. 1283.905 VCC3H ............. 10 ...... 720.000 ..... 28.000 VSS...................57 .... 4092.000.. 1363.905 SCANIN2 .......... 11 ...... 795.000 ..... 28.000 SLEVCC............58 .... 4092.000.. 1443.905 SCANIN1 .......... 12 ...... 870.000 ..... 28.000 RESET#............59 .... 4092.000.. 1574.000 VSS................... 13 .... 1020.000 ..... 28.000 SLETX...............60 .... 3874.000.. 1792.000 VCC3H ............. 14 .... 1095.000 ..... 28.000 SLERX ..............61 .... 3794.000.. 1792.000 XTALSEL.......... 15 .... 1170.000 ..... 28.000 SLERST............62 .... 3714.000.. 1792.000 XTALI................ 16 .... 1245.000 ..... 28.000 VCC3H..............63 .... 3634.000.. 1792.000 INT4.................. 17 .... 1320.000 ..... 28.000 VSS...................64 .... 3570.000.. 1792.000 SCANMODE..... 18 .... 1395.000 ..... 28.000 SLECLK ............65 .... 3505.000.. 1792.000 F1CLE............... 19 .... 1495.000 ..... 28.000 MODE2 .............66 .... 3440.000.. 1792.000 F1ALE............... 20 .... 1570.000 ..... 28.000 DUAL ................67 .... 3375.000.. 1792.000 F1WE#.............. 21 .... 1645.000 ..... 28.000 CPEN................68 .... 3310.000.. 1792.000 F1D0................. 22 .... 1720.000 ..... 28.000 MODE ...............69 .... 3245.000.. 1792.000 VSS................... 23 .... 1795.000 ..... 28.000 SDDAT2............70 .... 3162.000.. 1792.000 VCC3F.............. 24 .... 1870.000 ..... 28.000 VCC3H..............71 .... 3079.000.. 1792.000 F1D1................. 25 .... 1945.000 ..... 28.000 VSS...................72 .... 3014.000.. 1792.000 F1D2................. 26 .... 2020.000 ..... 28.000 VSS...................73 .... 2949.000.. 1792.000 F1D3................. 27 .... 2095.000 ..... 28.000 VCC3H..............74 .... 2884.000.. 1792.000 F1D4................. 28 .... 2170.000 ..... 28.000 SDDAT3............75 .... 2801.000.. 1792.000 VSS................... 29 .... 2245.000 ..... 28.000 SDCMD.............76 .... 2700.000.. 1792.000 VCC3F.............. 30 .... 2320.000 ..... 28.000 SDDAT0............77 .... 2599.000.. 1792.000 F1D5................. 31 .... 2395.000 ..... 28.000 VSS...................78 .... 2516.000.. 1792.000 F1D6................. 32 .... 2470.000 ..... 28.000 VCC3H..............79 .... 2451.000.. 1792.000 F1D7................. 33 .... 2545.000 ..... 28.000 SDDAT1............80 .... 2368.000.. 1792.000 VSS................... 34 .... 2695.000 ..... 28.000 SDDAT7............81 .... 2267.000.. 1792.000 VCC3F.............. 35 .... 2770.000 ..... 28.000 SDCLK..............82 .... 2166.000.. 1792.000 F1RDY0............ 36 .... 2845.000 ..... 28.000 VSS...................83 .... 2083.000.. 1792.000 F1RDY1............ 37 .... 2920.000 ..... 28.000 VCC3H..............84 .... 2018.000.. 1792.000 F1OE# .............. 38 .... 2995.000 ..... 28.000 SDDAT6............85 .... 1935.000.. 1792.000 F1CS0# ............ 39 .... 3070.000 ..... 28.000 SDDAT5............86 .... 1834.000.. 1792.000 F1CS1# ............ 40 .... 3145.000 ..... 28.000 SDDAT4............87 .... 1733.000.. 1792.000 UART_RX......... 41 .... 3245.000 ..... 28.000 F0CS1#.............88 .... 1635.000.. 1792.000 UART_TX ......... 42 .... 3320.000 ..... 28.000 F0CS0#.............89 .... 1570.000.. 1792.000 UART_CLK....... 43 .... 3395.000 ..... 28.000 F0OE#...............90 .... 1505.000.. 1792.000 VSS................... 44 .... 3470.000 ..... 28.000 VSS...................91 .... 1440.000.. 1792.000 VCC3H ............. 45 .... 3545.000 ..... 28.000 VCC3F ..............92 .... 1375.000.. 1792.000 CFLYP .............. 46 .... 4092.000 ... 327.585 F0RDY1 ............93 .... 1310.000.. 1792.000 VSS................... 47 .... 4092.000 ... 457.585 F0RDY0 ............94 .... 1245.000.. 1792.000


3.5.3. Pad Cross Reference by Pad Number (continued)


F0D7................. 95.....1180.000 ..1792.000 F0D0 ...............104 ...... 530.000.. 1792.000 F0D6................. 96.....1115.000 ..1792.000 FWP#..............105 ...... 465.000.. 1792.000 VSS .................. 97.......985.000 ..1792.000 VSS.................106 ...... 400.000.. 1792.000 VCC3F.............. 98.......920.000 ..1792.000 VCC3F ............107 ...... 335.000.. 1792.000 F0D5................. 99.......855.000 ..1792.000 F0WE#............108 ...... 270.000.. 1792.000 F0D4............... 100.......790.000 ..1792.000 F0ALE.............109 ...... 190.000.. 1792.000 F0D3............... 101.......725.000 ..1792.000 F0CLE.............110 ...... 110.000.. 1792.000 F0D2............... 102.......660.000 ..1792.000 SCANOUT2 ....111 ........ 30.000.. 1792.000 F0D1............... 103.......595.000 ..1792.000


3.6. Package Dimensions

3.6.1. 128-Pin LQFP and TQFP Package

b

D

D1

E1Index

A1

A2

L

E

e

Figure 7.6: Hyperstone S6 TQFP and LQFP Package-Outline

Symbol Term Definition

A1 Standoff height Height from ground plane to bottom edge of package

A2 Package height Height of package itself

E, D Overall length & width Length and width including leads

E1, D1 Package length & width Length and width of package

L Lead footprint Length of flat lead section

E Lead pitch Lead pitch

B Lead width Width of a lead


3.6.1. 128-Pin LQFP and TQFP Package (continued)

Hyperstone S6, 128-Pin Package

Symbol Dimensions in Millimeters Dimensions in Inches

Min. Nom. Max. Min. Nom. Max

A1 0.05 0.10 0.15 (.002) (.004) (.006)

A2 TQFP 0.95 1.00 1.05 (.037) (.039) (.041)

A2 LQFP 1.35 1.40 1.45 (.053) (.055) (.057)

E, D 15.80 16.00 16.20 (.622) (.630) (.638)

E1, D1 13.00 14.00 14.10 (.547) (.551) (.555)

L 0.45 0.60 0.75 (.018) (.024) (.030)

B 0.13 0.18 0.23 (.005) (.007) (.009)

e 0.40 (.0157)


3.6.2. 54-Pin LGA Package

AA1

a1

BB1

Bottom view:

Side view:

C

a3b5

L

a2

b2

b4

b3

b1

a4

Figure 7.7: Hyperstone S6 LGA54 Package-Outline


3.6.2. 54-Pin LGA Package (continued)

Hyperstone S6, 54-Pin LGA Package



A 7.45 7.50 7.55

A1 6.84

B 3.95 4.00 4.05

B1 2.28

C 0.60 0.69 0.78

a1 0.38

a2 0.13 0.18 0.23

a3 0.20

a4 0.00 0.05 0.10

b1 2.57

b2 1.65 1.70 1.75

b3 1.14

b4 1.45 1.50 1.55

b5 0.65 0.70 0.75

L 0.225 0.275 0.325


3.6.3. 58-Pin LGA Package

AA1

a1

BB1

Bottom view:

Side view:

C

b2

L

a2

b1

b3

L

b4

b6

b5

Figure 7.8: Hyperstone S6 LGA58 Package-Outline


. 54-Pin LGA Package (continued)

Hyperstone S6, 58-Pin LGA Package



A 7.40 7.50 7.60 (0.291) (0.295) (0.299)

A1 6.84 (0.269)

B 3.90 4.00 4.10 (0.154) (0.157) (0.161)

B1 2.28 (0.090)

C 0.70 (0.028)

a1 0.38 (0.015)

a2 0.13 0.18 0.23 (0.005) (0.007) (0.009)

b1 1.70 (0.067)

b2 0.65 0.70 0.75 (0.026) (0.028) (0.030)

b3 1.40 1.50 1.60 (0.055) (0.059) (0.063)

b4 4.60 (0.181)

b5 1.20 (0.047)

b6 0.45 0.50 0.55 (0.018) (0.020) (0.022)

L 0.225 0.325 0.425 (0.009) (0.013) (0.017)


3.7. Bus Signals

3.7.1. Bus Signals for the S6 Flash Memory Controller

The following table is an overview of the bus signals of the Hyperstone S6 flash memory controller. The signal states are defined as I = input, O = output, pu = pullup, pd = pulldown, h = hold and s = strong.

Status Pins LQFP 128

Pins TQFP 128

Pins LGA 54 LGA 58

Signal Name Description

Flash Memory, Channel 0 O 2 2 2 F0CS0..1# Flash Chip Select, Chips 0..1 O 1 1 1 F0WE# Flash Write Enable O 1 1 1 F0OE# Flash Output Enable O 1 1 1 F0CLE Flash Command Latch Enable O 1 1 1 F0ALE Flash Address Latch Enable I/O 8 8 8 F0D0..7 Flash Data Bus

I/pu/s 2 2 2 F0RDY0..1 Flash Ready/Busy, Chips 0..1 O/pd 1 1 1 FWP# Flash Reset/Write Protect (IO2)

Flash Memory, Channel 1 O 2 2 2 F1CS0..1# Flash Chip Select, Chips 0..1 O 1 1 1 F1WE# Flash Write Enable O 1 1 1 F1OE# Flash Output Enable O 1 1 1 F1CLE Flash Command Latch Enable O 1 1 1 F1ALE Flash Address Latch Enable I/O 8 8 8 F1D0..7 Flash Data Bus

I/pu/s 2 2 2 F1RDY0..1 Flash Ready/Busy, Chips 0..1

SD/MMC Card Interface I 1 1 1 SDCLK SD/MMC Clock

I/O/pu 1 1 1 SDCMD SD/MMC Command I/O/pu 8 8 8 SDDAT0..7 SD/MMC Data 0..7

General Control I/pu 1 1 1 MODE SD/MMC Select (IO3) I/pu 1 1 - CPEN Charge Pump Enable (IO4) I/pu 1 1 1 DUAL Dual Voltage Support Select (IO5) I/pu 1 1 1 MODE2 SD 2.0 Support Select (IO6)

I 1 1 1 RESET# Reset

General Purpose I/O I/O 1 1 - SLECLK GPIO, ISO UART Clock I/O 1 1 - SLERST GPIO, ISO UART Reset I/O 1 1 - SLERX GPIO, ISO UART Receive I/O 1 1 - SLETX GPIO, ISO UART Transmit O 1 1 - SLEVCC Power Switch Output


Status Pins LQFP 128

Pins TQFP 128

Pins LGA 54 LGA 58

Signal Name Description

Debugging I/pd 1 1 - UART_CLK Debugging UART Clock I/pu 1 1 - UART_RX Debugging UART Receive Data O 1 1 - UART_TX Debugging UART Transmit Data

Test I/pd 1 1 - INT4 Interrupt 4, Boot Select (for Test) I/pu 1 1 - XTALI Test Clock Input I/pu 1 1 - XTALSEL Test Clock Select I/pd - 1 - SCANEN Scan Test Enable I/pd - 1 - SCANMODE Scan Mode Select I/pd - 2 - SCANIN1..2 Scan Path Input O/pd 2 2 - SCANOUT1..2 Scan Path Output I/pd - 1 - B_TEST Memory BIST Multiplexer Control I/pd - 1 - B_MBRUN Memory BIST Start Signal I/pd - 1 - B_SHDR Memory BIST Shift Data Register I/pd - 1 - B_MRSI Memory BIST Mode Register Data Input O - 1 - B_MRSO Memory BIST Mode Register Data Output O - 1 - B_RUN Memory BIST Is Running Indication

Flash Memory and Core Voltage Regulators 2 1 - VINF 1.8V Flash Power Supply Input 2 1 1 VDDF 1.8V Flash Power Supply Output 1 1 1 VDDF_C 1.8V Flash Regulator Capacitor 1 1 1 VDDC 1.8V Core Power Supply Output 1 1 1 VDDC_C 1.8V Core Regulator Capacitor

Charge Pump 2 1 - VIN_CP Charge Pump Supply Input 2 1 - VDD_CP 3.0V Charge Pump Output 4 2 - CFLYP, CFLYN Fly-back Capacitor Connection

Power Supply 8 7 1 VCC3H Host Supply Connection 6 6 1 VCC3F Flash Bus I/O Supply 12 13 1 VSS Host Ground Connection 26 22 0/4 Not connected

Total: 128 128 54/58

Table 7.1: Bus Signals for the S6 Flash Memory Controller

3.7.2. Bus Signal Description

The following section describes the bus signals for the Hyperstone S6 controller in detail. In the following signal description, the signal states are defined as I = input, O = output, U = pull-up, D = pull-down. The channel number is shown as “x” here, it can be 0 or 1.


3.7.2. Bus Signal Description (continued)

States Names Use

O FxCS0..1# Flash Chip Select. Connect to the flash CE# pin for two flash chips per channel.

O FxWE# Flash Write Enable. Connect to the flash WE# pin.

O FxOE# Flash Output Enable. Connect to flash RE# pin.

O FxCLE Flash Command Latch Enable. Connect to the flash CLE pin.

O FxALE Flash Address Latch Enable. Connect to the flash ALE pin.

O/I FxD0..7 Flash Data Bus. Connect to the flash I/O0 to I/O7 data bus lines.

I,U FxRDY0..1 Flash Ready/Busy signals. Connect to the flash memory R/B signals, corresponding to the FxCS0..1# connection.

O,D FWP# Flash Write Protect signal. Connect to the flash WP# pin. This signal is common to both flash channels.

I SDCLK SD/MMC Interface Clock input

O/I,U SDCMD SD/MMC Interface Command.

O/I,U SDDAT0..7 SD/MMC Interface Data 0..7.

I,U MODE SD/MMC mode select. If this pin is low, SD mode is selected, if this pin is high (or open), MMC mode is selected.

I,U MODE2 SD 2.0 mode select. If this pin is low, SD 1.01 or SD 1.1 mode is selected, if this pin is high (or open), SD 2.0 mode is selected.

I,U DUAL SD/MMC dual voltage select. If this pin is high (or open), the SD/MMC interface initializes as a high voltage card (2.7V to 3.6V support signaled in the OCR). If this pin is low, the SD/MMC interface initializes as a dual voltage card (additional 1.65V to 1.95V support signaled in the OCR).

I,U CPEN Charge Pump enable. SD/MMC boot mode select. If this pin is high (or open), the charge pump is not used, and not enabled in the boot code. If this pin is low, the charge pump is enabled, and the boot ROM waits until the charge pump stable flag is set before accessing the flash.

I RESET# Reset processor. RESET# low resets the processor to the initial state and halts all activity. RESET# must be low for at least one cycle. On a transition from low to high, a Reset exception occurs and the processor starts execution at the Reset entry determined by the INT4 state. The transition may occur asynchronously to the clock.

If the reset input is not needed, this pin must be high. In this case, an internal voltage detector will generate a reset pulse of about 0.5ms when the supply voltage has reached about 1.5V.

O/I SLECLK GPIO, or Clock line for a ISO 7816-3 like interface.

O/I SLERST GPIO, or Reset line for a ISO 7816-3 like interface.



States Names Use

O/I SLERX GPIO, or Receive line for a ISO 7816-3 like interface.

O/I SLETX GPIO, or Transmit line for a ISO 7816-3 like interface.

O SLEVCC Switchable power supply output

I/U UART_CLK Debugging UART Clock Input.

I/U UART_RX Debugging UART Receive Data Input.

O/U UART_TX Debugging UART Transmit Data Input.

I,D INT4 Boot Select Pin. The INT4 state on a reset exception determines the location of the reset boot procedure. If INT4 is low on reset, the S6 is in normal mode and begins booting from the internal ROM, if INT4 is high on reset, the S6 is in test mode and begins booting from the external MEM3 ROM for testing. MCR bit 19 is initialized to show the selected mode. Controlled by the corresponding FCR bits, this signal may also be used to interrupt the CPU.

I/U XTALI Test Clock Input.

I/U XTALSEL Internal/External Clock Select Input. Connect to GND to use the XTALI pin as clock input. Leave open to use the Internal R/C Oscillator. In this case, the XTALI pin should also be left open.

I/D SCANEN Scan Test Enable signal. Do not connect.

I/D SCANMODE Scan Mode Select signal. Do not connect.

I/D SCANIN1..2 Scan Input 1 and 2 signal. Do not connect.

O SCANOUT1 Scan Output 1 signal in Scan Test mode. If not in Scan Test mode, this output is low in normal mode, or has the CS1# (MEM1 chip select) signal in test mode.

O SCANOUT2 Scan Output 2 signal in Scan Test mode. If not in Scan Test mode, this output shows the inverted value of MCR bit 29 in normal mode, or has the WE# (memory write enable) signal in test mode.

I/D B_TEST Memory BIST signal. Do not connect.

I/D B_MBRUN Memory BIST signal. Do not connect.

I/D B_SHDR Memory BIST signal. Do not connect.

I/D B_MRSI Memory BIST signal. Do not connect.

O B_MRSO Memory BIST signal. Do not connect.

O B_RUN Memory BIST signal. Do not connect.

VINF Flash Memory 1.8V Power Supply Regulator input. Connect to VCC3H if the host supply voltage should be used to supply this regulator, connect to VDD_CP if the charge pump should be used to supply this regulator.



States Names Use

VDDF Flash Memory 1.8V Power Supply Regulator output. Connect to VCC3F if the flash I/O voltage is 1.8V. Connect to the flash power supply as well if the flash supply voltage is 1.8V. Connect a 100nF ceramic capacitor to GND.

VDDF_C Flash Memory 1.8V Power Supply Regulator Stabilizing Capacitor. Connect a 1uF ceramic capacitor to GND.

VDDC Controller Core 1.8V Power Supply Regulator output. Connect a 100nF ceramic capacitor to GND.

VDDC_C Controller Core 1.8V Power Supply Regulator Stabilizing Capacitor. Connect a 1uF ceramic capacitor to GND.

VIN_CP Charge Pump power supply input. Connect to VCC3H.

VDD_CP Charge Pump 3.0V output. If the charge pump is used to power the flash, connect to VCC3F and to the power supply of the flash. Connect a 2.2uF X5R capacitor to GND.

CFLYP, CFLYN Charge Pump fly-back capacitor. Connect a 1uF X5R capacitor between these two pins if the charge pump is used.

VCC3H Controller Regulator and Host I/O power supply. Connect this to the SD/MMC host power supply. If the charge pump is used, connect a 2.2uF X5R capacitor to GND

VCC3F Controller Flash I/O power supply. Connect to the SD/MMC host power supply, to VDDF, or to the Charge Pump output depending on the flash memory I/O levels.

VSS Controller Core and I/O ground. Connect to the SD/MMC host ground.

FUNCTIONAL DESCRIPTION 35

4. Functional Description

4.1. Block Diagram

Instruction Cache

Interrupt

Controller

32 Bit Timer

Watchdog Power Down

Control

Bus Controller

Load/ Store Unit

ALU/Shifter32 Bit

Register File for RISC Unit 96 Registers 32 Bit Wide

Bus Interface On-Chip I/O

RAM 20 KByte

1.8V Core Regulator

1.8V Flash Regulator,

Charge Pump

2 channel Flash Control

2 channel ECC/CRC Unit

Boot ROM 16 KByte

Control Logic

Card Interface

SD/MMCRegisters

4x 4 KByte Sector Buffers

SD/MMC Interface

UART

GPIO Debug

4 Flash Memory Chips

8 Bit Wide

4.2. System Memory Map

The memory address space is divided into six partitions as follows:

Address (Hex) Address Space Memory Type

0000 0000..07FF FFFF IRAM Internal RAM

0800 0000..0FFF FFFF IRAM SD Sector Buffers

1000 0000..17FF FFFF MMIO Memory-Mapped I/O

1800 0000..3FFF FFFF not available

4000 0000..7FFF FFFF MEM1 external SRAM (only in test mode)

8000 0000..BFFF FFFF MEM2 NAND Flash interface

C000 0000..F7FF FFFF not available

F800 0000..FFFF FFFF IROM Internal/external ROM

36 FUNCTIONAL DESCRIPTION

Access to the registers of the SD/MMC and flash memory interface takes place in the processor’s Memory Mapped I/O address space.

4.3. Flash Memory Interface

NAND type flash memory chips are connected to the Hyperstone S6 as described below. x stands for the channel number, 0 or 1.

Flash Chip Signal S6 Signal

CLE FxCLE

ALE FxALE

CE# FxCS0#, FxCS1#

WE# FxWE#

RE# FxOE#

I/O 0 ... I/O 7 FxD0 ... FxD7

WP# FWP#

Ready/Busy# FxRDY0, FxRDY1

Up to four flash memory chips can be connected to the Hyperstone S6. In a two channel configuration, the chips are connected as shown above.

In a single channel configuration, up to four flash chips can be connected to the F0CLE, F0ALE, F0WE#, F0OE# and F0D0..F0D7 signals. In this configuration, the chip selects and ready/busy signals for flash #0 are F0CS0#/F0RDY0, for flash #1 F0CS1#/F0RDY1, for flash #2 F1CS0#/F1RDY0, and for flash #3 they are F1CS1#/F1RDY1.

During reset, FxCLE, FxALE, FxCS0..1#, FxWE# and FxOE# are high, FWP# is low.

4.4. Reset and ROM Boot

4.4.1. Boot Selection on Reset

The S6 uses the INT4 line state at reset to select between booting from internal boot ROM (normal mode) and booting from external MEM3 (test mode, only for test functionality). The INT4 pad has an internal pull-down resistor so that INT4 is low when INT4 is not connected.

If the INT4 line is high at reset, the external MEM3 memory is mapped to the IROM memory area, and the S6 reset begins fetching instructions from external MEM3 address 0xFFFF FFF8. If the INT4 line is low at reset, the internal ROM is mapped to the IROM memory area, and the S6 begins booting from it’s internal boot ROM at address 0xFFFF FFF8.

4.4.2. Internal ROM Boot Process

The S6 has 16 Kbytes of internal ROM at address 0xF800 0000 with a wraparound modulo 16 Kbytes up to 0xFFFF FFFF. In normal mode, the reset trap begins executing the internal boot ROM code at 0xFFFF FFF8.


4.4.2. Internal ROM Boot Process (continued)

The internal ROM present on the S6 performs the following actions on reset when booting is done from ROM:

❒ The S6 processor is initialized.

❒ MODE (IO3) is switched to output driving 0 or 1, depending on the state sensed at MODE. If MODE is 0, the controller initializes in SD mode, if MODE is 1, the controller initializes in MMC mode. BOOT (IO4) is switched to output driving 0 or 1, depending on the state sensed at BOOT. The sensed value is saved to be used later in the booting process. All Flash chips are deselected.

❒ The SD interface is initialized to a default configuration and brought into the reset state.

❒ The Boot bit in the SD Flags Register is checked. If this bit indicates a high level on SDCMD or SDDAT0, control proceeds to firmware boot from flash, else control proceeds to the SD interface boot.

❒ For the SD interface boot, the S6 performs the same power-on procedure as for the flash boot as detailed below (charge pump enable, Ready/Busy wait, flash reset), and then waits until the SD interface state machine reset is complete (when the host has sent the first clocks), then determines the device ID of flash chip 0 and stores this information, and sets up a data sector containing a magic number, the controller’s revision ID, the flash device ID, and the value of the SD Mode Select register (will be 1 for MMC and 2 for SD mode). When CMD61 is received, this sector is transferred to the host that can use this information to decide about the correct firmware files. The next host command is used to download a firmware file. The number of sectors in this firmware file is specified in the command argument. The S6 reads the specified number of sectors through the SD interface, the downloaded code is put into IRAM starting at address 0x0000 0000.

If any other command has been received instead of CMD61, the SD interface boot is aborted and control proceeds to normal firmware boot from flash.

❒ For booting from flash, the S6 waits until the voltage detector indicates a supply voltage of at least 2.5V if the DUAL pin is low, followed by a wait until the first CMD1 (in MMC mode) or ACMD41 (in SD mode) with a valid voltage range has been received from the host. Then the CPEN pin is checked, if this indicates that the charge pump is used, both the charge pump and the 1.8V flash regulator are enabled, and the S6 waits until the charge pump stable indication is there.

After that, the S6 waits until the first flash chip Ready/Busy line goes high, waits for another 2ms, polls the first flash chip status register until this indicates that the flash is ready. Then a reset command is sent to the flash, and again the Ready/Busy line and the flash status register are polled. Now the Anchor Block is searched. If the Anchor Block is not found or if there is an uncorrectable error when loading the firmware, the S6 falls back to booting from the SD interface. If the Anchor Block is found, a copy is stored in the SD sector buffer. Then, a pre-boot routine at offset 0x1FC in the sector buffer is called. After return, the S6 processor proceeds to load the firmware sectors from Flash 0 using the Anchor Block information in the sector buffer.

❒ For the boot from flash chip 0, the location numbers stored in the anchor block are taken as page numbers of the flash chip.

38 FUNCTIONAL DESCRIPTION

4.4.2. Internal ROM Boot Process (continued)

There are two parameters in the Anchor Sector that modify the sector read routine for booting. A byte at 0x1FB specifies the sector size in 512 byte units. A word at 0x1F4 specifies a subroutine called from the sector read routine that outputs the correct number of address bytes to the flash memory. These are initialized to 1, for a sector size of 512 bytes, and to a routine sending the address bytes needed by the Samsung 2Gbit (K9F2G08U0M) flash chips. In case the Anchor sector could not be found, the search loop is retried with a different routine sending the address bytes needed by the Samsung 512Mbit (K9F1208U0M) flash chips. For the firmware boot later, the correct values for the sector size and address routine from the Anchor sector are used.

After the Anchor sector has been found and loaded, the parameters stored there overwrite the boot time initialization for the parameters.

❒ After booting, the firmware is started via a TRAP 63 instruction with the trap table located at the beginning of the IRAM.

The controller revision ID is ID Byte 3 Description

0xD5 S6 SD/MMC Controller, first revision

For the controller revision 0xD5, the following sub-revisions are defined:

ID Byte 2 Description

0 S6 revision D1A

This manual describes the controller revision 0xD5.

4.5. S6 Controller Revisions

At this moment, there is only one revision of the S6 controller.

4.6. Example Schematics

This section contains simplified schematics for a single-voltage card using a 3.3V flash, not using the charge pump, and for a dual-voltage card using a 3.3V flash, using the charge pump. The host connection and the connection between controller and flash are not shown in detail.


S6

SD...HostFxCLEFxALE

FxCSn#FxD0..7FxWE#FxOE#FWP#

FxRDYn

3.3V

3.3V

VSS

VCC

Signals

Flash

MODE

MODE2

DUAL3.3V

RESET#

3.3V

VCC3H

VCC3F

VSS VDDC_C

VDDC

1uF

connect as required

CPEN

100nF

100nF

100nF

Figure 9: Hyperstone S6 High Voltage Card example

S6

SD...HostFxCLEFxALE

FxCSn#FxD0..7FxWE#FxOE#FWP#

FxRDYn

3.3V

VSS

VCC

Signals

Flash

MODE

CPEN

DUAL3.3V

RESET#

3.3V

VCC3H

VSS VDDC_C

VDDC100nF

1uF

connect as required

CFLYP

VDD_CP2.2uF

1uF

VCC3F

3.0V

MODE2

2.2uF

CFLYNVIN_CP

Figure 10: Hyperstone S6 Dual Voltage Card example

40 ELECTRICAL SPECIFICATIONS

5. Electrical Specifications

5.1. DC Characteristics

Absolute Maximum Ratings

Case temperature TC under Bias: -25°C to +85°C Storage Temperature: -40°C to +125°C Voltage on any Pin with respect to ground: -0.3V to VCC + 0.3V

D.C. Parameters

Data transfer mode: Supply Voltage VCC3H, VCC3F: 1.65V to 3.6V Regulator output VDDC: 1.80V ± 4% Regulator output VDDF: 1.87V ± 4% Regulator current VDDC, VDDF: 50 mA max Voltage drop VDDC, VDDF at 50mA: 100 mV max Case Temperature TCASE: -25°C to +85°C

Symbol Parameter Min Max Unit Notes

VIL Input LOW Voltage -0.3 +0.8 V

VIH Input HIGH Voltage 2.0 VCC+0.3 V

VOL Output LOW Voltage 0.4 V at 4mA

VOH Output HIGH Voltage 2.4 V at 1mA

VIL Input LOW Voltage, SD pins -0.3 25% V Fraction of VCC3H

VIH Input HIGH Voltage, SD pins 62.5% VCC+0.3 V Fraction of VCC3H

VOL Output LOW Voltage, SD pins 12.5% V at 100µA, Fraction of VCC3H

VOH Output HIGH Voltage, SD pins 75% V at 100µA, Fraction of VCC3H

ICC Operating Current

Sleep mode Operating, 20 MHz Operating, 40 MHz

0.2 25 40

mAmAmA

ILI Input Leakage Current ±10 µA

ILO Output Leakage Current ±10 µA

CI/O Input/output Capacitance 10 pF

VCP Charge Pump Output Voltage 2.7 3.3 V 3.0V typical

ICP Charge Pump Output Current 50 mA

Vripple Charge Pump Output Ripple 30 150 mV in regulated mode

Table 7.2: DC Characteristics

ELECTRICAL SPECIFICATIONS 41

5.2. AC Characteristics

5.2.1. SD Interface AC Characteristics, Low Speed Mode

The SD interface characteristics refer to the symbols used in the timing definition of the SD 1.01 and MMC 3.31 standards.

Symbol Parameter Min Max Units Notes

fPP Clock, Data transfer mode 25 MHz CL ≤ 100pF

fOD Clock, Identification mode 400 kHz CL ≤ 250pF

tWL Clock low time 10 ns CL ≤ 100pF

tWH Clock high time 10 ns CL ≤ 100pF

tTLH Clock rise time 10 ns CL ≤ 100pF

tTHL Clock fall time 10 ns CL ≤ 100pF

tWL Clock low time 50 ns CL ≤ 250pF

tWH Clock high time 50 ns CL ≤ 250pF

tTLH Clock rise time 50 ns CL ≤ 250pF

tTHL Clock fall time 50 ns CL ≤ 250pF

tISU CMD, DAT input setup time 5 ns CL ≤ 25pF

TIH CMD, DAT input hold time 5 ns CL ≤ 25pF

tOLDY CMD, DAT output delay 0 14 ns CL ≤ 25pF, Data transfer

tOLDY CMD, DAT output delay 0 50 ns CL ≤ 25pF, Identification

5.2.2. SD Interface AC Characteristics, High Speed Mode

tbd

42 ELECTRICAL SPECIFICATIONS

5.2.3. Flash Memory Interface AC Characteristics

The AC Characteristics for the flash memory interface are based on the S6 processor clock cycle time tCPU. The tables list the flash memory interface timing based on the tCPU value. There are two different tables, one for a single-cycle flash memory access (MEM2Access=1), and one for a two-cycle flash memory access (MEM2Access=2).

The tWP and tRP values (FWE# and FOE# pulse) can be adjusted by MCR settings in the firmware in steps of about 2.7ns. The adjustment is denoted A in the table.

Symbol Parameter Min Max Units

TCLS CLE setup time tCPU – 5ns ns

TCLH CLE hold time tCPU/2 – 2ns – A ns

TCS CE setup time tCPU – 5ns ns

TCH CE hold time tCPU – 5ns ns

TALS ALE setup time tCPU – 5ns ns

TALH ALE hold time tCPU/2 – 2ns – A ns

TDS Data Setup time tCPU/2 – 5ns + A ns

TDH Data hold time tCPU/2 – 5ns – A ns

TWP WE pulse width tCPU/2 – 2ns + A ns

TWC Write cycle time tCPU ns

TWH WE high hold time tCPU/2 – 2ns – A ns

TRP RE pulse width tCPU/2 – 2ns + A ns

TRC Read cycle time tCPU ns

TREA RE access time tCPU – 10ns ns

TREH RE high hold time tCPU/2 – 2ns + A ns

TCEH CE high hold time tCPU*4 ns

TWHR WE high to RE low tCPU*2 – 5ns – A ns

Table 7.3: Flash Interface AC Characteristics, single-cycle access

ELECTRICAL SPECIFICATIONS 43

Symbol Parameter Min Max Units

TCLS CLE setup time tCPU/2 – 2ns ns

TCLH CLE hold time tCPU/2 – 2ns – A ns

TCS CE setup time tCPU/2 – 2ns ns

TCH CE hold time tCPU – 5ns ns

TALS ALE setup time tCPU/2 – 2ns ns

TALH ALE hold time tCPU/2 – 2ns – A ns

TDS Data Setup time tCPU ns

TDH Data hold time tCPU/2 – 5ns – A ns

TWP WE pulse width tCPU – 2ns + A ns

TWC Write cycle time tCPU*2 ns

TWH WE high hold time tCPU – 2ns – A ns

TRP RE pulse width tCPU – 2ns + A ns

TRC Read cycle time tCPU*2 ns

TREA RE access time tCPU*1.5 – 10ns ns

TREH RE high hold time tCPU – 2ns – A ns

TCEH CE high hold time tCPU*4 ns

TWHR WE high to RE low tCPU*2 ns

Table 7.4: Flash Interface AC Characteristics, two-cycle access

44

Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. Hyperstone does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent licences are implied. Hyperstone reserves the right at any time without notice to change the said circuitry and this product specification. Hyperstone has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. Specific testing of all circuit parameters is not necessarily performed.

www.hyperstone.com

Hyperstone GmbH Line-Eid-Strasse 3 78467 Konstanz Germany Phone: +49 7531 98030 Fax: +49 7531 51725 Sales: [email protected] Technical support:

[email protected]

Hyperstone Inc. - USA 465 Corporate Square Drive Winston-Salem, NC 27105 USA Phone: +1 336 744 0724 Fax: +1 336 744 5054 Sales: [email protected] Technical support: [email protected]

Hyperstone Asia Pacific - Taiwan 3F., No. 501, Sec.2, Tiding Blvd. Neihu District, Taipei City 114 Taiwan, R.O.C. Phone: +886 2 8751 0203 Fax: +886 2 8797 2321 Sales: [email protected] Technical support:

[email protected]

Ordering Information The following table lists the different variants and the corresponding ordering code.

Device Revision Package Order Code

S6 D1A LGA 54 S6-LAK05

S6 D1A LGA 58 S6-LAK06

S6 D1A TQFP 128 S6-LAT06Q

S6 D1A Good Die S6-0ABD0

S6 D1A Wafer S6-0AWF0

Hyperstone S6 Flash Memory Controller Specification

Documents

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pin lga package

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hyperstone microprocessor

hyperstone gmbhhyperstone

hyperstone gmbh revision