Hyperstone S3D-16X Flash Memory Controller Specification

Hyperstone S4 32-Bit Flash Memory Controller

User's Manual

Preliminary

Specifications and information in this document are subject to change without notice and do not represent a commitment on the part of Hyperstone AG. Hyperstone AG reserves the right to make changes to improve functioning. Although the information in this document has been carefully reviewed, Hyperstone AG does not assume any liability arising out of the use of the product or circuit described herein.

Hyperstone AG does not authorize the use of the Hyperstone microprocessor in life support applications wherein a failure or malfunction of the microprocessor may directly threaten life or cause injury. The user of the Hyperstone microprocessor in life support applications assumes all risks of such use and indemnifies Hyperstone AG against all damages.

No part of this manual may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photo-copying and recording, for any purpose without the permission of Hyperstone AG.

Hyperstone is a registered trademark of Hyperstone AG.

For further information please contact:

Hyperstone AG Line-Eid-Strasse 3 D-78467 Konstanz Germany Phone +49 (7531) 9803-0 Fax +49 (7531) 51725 E-Mail [email protected]

www.hyperstone.com

Copyright 1990, 2006 Hyperstone AG

Revision 06/03 U1C

3

Table of Contents

Revision History ............................................................................................. 4

1. Features ................................................................................................ 5

1.1. Host Interface...........................................................................................5 1.2. Flash Memory Interface ...........................................................................5 1.3. Controller Core ........................................................................................5

2. General Description ............................................................................... 6

3. Pin Configuration ................................................................................... 8

3.1. Hyperstone S4, 128-Pin TQFP Package ..................................................8 3.1.1. Pin Configuration - View from Top Side................................8 3.1.2. Pin Cross Reference by Pin Name ..........................................9 3.1.3. Pin Cross Reference by Location............................................9

3.2. Hyperstone S4, 50-Pin LGA Package....................................................10 3.2.1. Pin Configuration - View from Top Side..............................10 3.2.2. Pin Cross Reference by Pin Name ........................................11 3.2.3. Pin Cross Reference by Location..........................................11

3.5. Hyperstone S4 Die .................................................................................12 3.5.1. Pad Configuration .................................................................12 3.5.2. Pad Cross Reference by Pad Name.......................................13 3.5.3. Pad Cross Reference by Pad Number ...................................14

3.6. Package Dimensions ..............................................................................15 3.6.1. 128 Pin TQFP Package .........................................................15 3.6.2. 50-Pin LGA Package ............................................................17

3.7. Bus Signals.............................................................................................19 3.7.1. Bus Signals for the S4 Flash Memory Controller .................19 3.7.2. Bus Signal Description .........................................................20

4. Functional Description ......................................................................... 23

4.1. Block Diagram .......................................................................................23 4.2. System Memory Map.............................................................................23 4.3. Flash Memory Interface .........................................................................24 4.4. Reset and ROM Boot .............................................................................24

4.4.1. Boot Selection on Reset ........................................................24 4.4.2. Internal ROM Boot Process ..................................................25

4.5. S4 Controller Revisions .........................................................................26 4.6. Example Schematics ..............................................................................27

5. Electrical Specifications ....................................................................... 28

5.1. DC Characteristics .................................................................................28 5.2. AC Characteristics .................................................................................29

5.2.1. SD Interface, SD 1.01 and MMC 3.31 Mode .......................29 5.2.2. SD Interface, SD 1.1 and MMC 4.0 Mode ...........................29 5.2.3. Flash Memory Interface AC Characteristics.........................30

Ordering Information .................................................................................... 32

4

Revision History Revision Change History Date

05/2005 Initial release June 2, 2005

08/2005 Updated pad sequence, Updated flash timing, added schematic August 9, 2005

09/2005 SCANOUT2 pad position updated, minor updates, TQFP128 package added

Sept 8, 2005

09a/2005 Pad 1..9 positions updated Sept 15, 2005

01/2006 S04U1B revision update Jan 13, 2006

03/2006 S04U1C revision update, LGA50 package added March 13, 2006

FEATURES 5

1. Features

1.1. Host Interface

Compliant to the SD standards rev. 1.01 and rev. 1.10

Compliant to the MMC standards rev. 3.31 and rev. 4.0

Dual Voltage Support (1.8V and 3.3V)

Dual integrated 512 Byte Sector Buffers for fast data transfer

1.2. Flash Memory Interface

Supports all control signal for NAND type flash memory connection

Supports direct connection of up to 4 flash memory chips

Supports 128, 256, 512Mbit, 1, 2, 4, 8 Gbit NAND type flash memories

Flash memory power down logic and flash memory write protect control

Firmware storage in flash memory

Firmware is loaded into internal memory by the boot ROM

Error Correcting Code capable of correcting 3 bytes in a 512 byte sector

On-chip voltage regulator for 1.8V processor core power supply

Optional on-chip voltage regulator for 1.8V flash memory power supply

1.3. Controller Core

High performance microprocessor core based on the Hyperstone architecture

Clock frequency from 10 MHz to 60MHz using trimmable internal oscillator

16 Kbyte internal Boot ROM

20 Kbyte internal RAM

Automatic power-down mode during wait periods for host data or flash memory operation completion

Automatic sleep mode during host inactivity periods, Icc < 100 µA

50 pin LGA (7×4×0.7 mm) package, 128 pin TQFP (14×14×1.0 mm) package for engineering purposes

0.18 µm CMOS technology

Supply voltage 1.65V to 1.95V and 2.7V to 3.6V (2.0V to 3.6V for identification)

6 GENERAL DESCRIPTION

2. General Description The Hyperstone S4 flash memory controllers are among the most powerful single-chip controllers on the market for designing SD and MMC Flash Memory Cards. The required external component count is reduced to a bare minimum of few passive components enabling the design of very low-cost but high-performance SD and MMC Cards.

The Hyperstone S4 flash memory controller can operate with flash memory devices from Samsung or compatible chips thereof. It operates with a supply voltage of 1.8V or 3.3V. A highly sophisticated Error Correction Code and a wear-leveling algorithm are implemented. A complete set of development tools is available which enables you to design SD Cards with a very competitive cost/performance ratio.

The main features of Hyperstone S4 flash memory controller are:

Inexpensive single-chip controller for SD and MMC flash memory cards

NAND type flash memory interface

Firmware support for various NAND flash memories including Samsung, Toshiba, Infineon TwinFlash™ and others

Built-in 1.8V voltage regulator for flash memory supply (optional)

Built-in 1.8V voltage regulator for processor core supply

Built-in SD and MMC Card Interface

Data transfer rate to flash memories: up to 40 MBytes/s

On-chip ECC and CRC16 units for flash data protection

Hardware support for the C2 encryption and decryption routines (CPRM)

Sophisticated software for wear leveling

Automatic power-down mode and sleep mode

Small 50-pin LGA package

also available as a bare die

available in a 128-pin TQFP package for engineering purposes

Comprehensive equipment available for development and test of hardware and firmware

The Hyperstone S4 single-chip controller for SD and MMC Flash Memory Cards is based on the Hyperstone E1-32X microprocessor core providing a modern 32-bit RISC architecture. The controller’s flash memory interface allows the direct connection of up to 4 flash memory chips and supports NAND type flash memories (128 Mbit to 8 Gbit). Next-generation flash memories will be supported as well. Through the sophisticated memory interface of the Hyperstone S4, your flash memory card will achieve a superior performance with a data transfer rate to flash memories of up to 40 MBytes/s. An on-chip ECC and CRC16 unit generates the required code bytes for error detection and correction of up to three random bytes per 512 Byte data sector. Code byte generation during write operations as well as error detection during read operation is implemented on the fly without any speed penalties.

GENERAL DESCRIPTION 7

The controller is equipped with 20 KByte internal memory that is used for storage of code and data. The internal memory can also be used as an intermediate memory for storing data blocks during flash memory operations.

The Hyperstone S4 controller works at a power supply voltage of 1.65V to 1.95V or 2.7V to 3.3V. It provides a built-in voltage regulator of 1.8V for the processor core power supply.

A 16 KByte internal boot ROM includes basic routines for accessing the flash memories and for loading the main code into the internal memory of the Hyperstone S4. This boot concept offers a high degree of flexibility while keeping the component count small.

The SD and MMC interface provides all required signals and is fully compliant with the SD Card standards rev. 1.01 and 1.10, and with the MMC standards rev. 3.31 and 4.0. The SD/MMC Card controller part of the Hyperstone S4 includes the SD and MMC card configuration and status registers as well as two 512 Byte sector buffers.

A comprehensive tool kit is also available for developing and testing SD or MMC Flash Memory Cards based on the Hyperstone S4. This includes a hardware/software test environment, pre-format hardware and software, and controller firmware.

8 PIN CONFIGURATION

3. Pin Configuration

3.1. Hyperstone S4, 128-Pin TQFP Package

3.1.1. Pin Configuration - View from Top Side

hyFlashS04U1C-TQ128

979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128

VDDFVCC3H

VSSVDDF_C

VCC3HVDDC

VDDC_CVSS

IBIASUART_TXUART_RX

UART_CLKVCC3H

RESET#VSSVSSVSSVSS

DUALVCC3HBOOT

90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 659192939495961 2 3 4 6 7 8 9 10 11 125 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

VCC

3HVS

SVC

C3H

SDD

AT0

VCC

3HSD

DAT

1

SD

CLK

VCC

3H

SDD

AT3

SDD

AT6

SDD

AT5

A7

A6

A5

A4

FOE#

FRD

Y3FR

DY2

VCC

3FFR

DY1

FRD

Y D7

D6

VCC

3F D5

D4

D3

SDC

MD

SDD

AT7

60595857565554535251504948474645444342414039383736353433

61626364

INT4

VSSSCANIN1SCANIN2VCC3HVSSSCANENSCANOUT1SCANOUT2VSSVSS

A3FWE#FWP#D0D1

VCC3HXTALSELXTALI

SCANMODE

SDD

AT2

VCC

3F

D2

A2

MODE

SDD

AT4

Figure 7.1: Hyperstone S4, 128-Pin TQFP Package

PIN CONFIGURATION 9

3.1.2. Pin Cross Reference by Pin Name

Signal Location Signal Location Signal Location Signal Location

A2 ..................... 39 FRDY3.............. 21 SDDAT5 ........... 14 VDDC_C ...........113 A3 ..................... 38 FWE#................ 37 SDDAT6 ........... 13 VDDF.................107 A4 ..................... 19 FWP#................ 36 SDDAT7 ........... 10 VDDF_C............110 A5 ..................... 18 IBIAS .............. 115 UART_CLK..... 118 VSS ...................109 A6 ..................... 17 INT4.................. 53 UART_RX....... 117 VSS ...................114 A7 ..................... 16 MODE............. 128 UART_TX....... 116 VSS ...................121 BOOT ............. 127 RESET# ......... 120 VCC3F.............. 23 VSS ...................122 D0 ..................... 35 SCANEN .......... 44 VCC3F.............. 28 VSS ...................123 D1 ..................... 34 SCANIN1.......... 48 VCC3F.............. 32 VSS ...................124 D2 ..................... 33 SCANIN2.......... 47 VCC3H ........... 108 VSS .......................3 D3 ..................... 31 SCANMODE..... 54 VCC3H ........... 111 VSS .....................40 D4 ..................... 30 SCANOUT1...... 43 VCC3H ........... 119 VSS .....................41 D5 ..................... 29 SCANOUT2...... 42 VCC3H ............. 12 VSS .....................45 D6 ..................... 27 SDCLK ............. 11 VCC3H ........... 126 VSS .....................49 D7 ..................... 26 SDCMD .............. 6 VCC3H ............... 2 XTALI ..................52 DUAL .............. 125 SDDAT0 ............. 7 VCC3H ............... 4 XTALSEL.............51 FOE# ................ 20 SDDAT1 ............. 9 VCC3H ............. 46 n.c................55..106 FRDY................ 25 SDDAT2 ............. 1 VCC3H ............. 50 FRDY1.............. 24 SDDAT3 ............. 5 VCC3H ............... 8 FRDY2.............. 22 SDDAT4 ........... 15 VDDC ............. 112

3.1.3. Pin Cross Reference by Location

Location Signal Location Signal Location Signal Location Signal

1..............SDDAT2 21.............. FRDY3 41 .................. VSS 112 ................VDDC 2................VCC3H 22.............. FRDY2 42 ......SCANOUT2 113 ........... VDDC_C 3.....................VSS 23.............. VCC3F 43 ......SCANOUT1 114 ...................VSS 4................VCC3H 24.............. FRDY1 44 .......... SCANEN 115 .................IBIAS 5..............SDDAT3 25................ FRDY 45 .................. VSS 116 ......... UART_TX 6...............SDCMD 26......................D7 46 .............VCC3H 117 ......... UART_RX 7..............SDDAT0 27......................D6 47 ..........SCANIN2 118 .......UART_CLK 8................VCC3H 28.............. VCC3F 48 ..........SCANIN1 119 ..............VCC3H 9..............SDDAT1 29......................D5 49 .................. VSS 120 ............RESET# 10............SDDAT7 30......................D4 50 .............VCC3H 121 ...................VSS 11.............. SDCLK 31......................D3 51 ......... XTALSEL 122 ...................VSS 12..............VCC3H 32.............. VCC3F 52 ............... XTALI 123 ...................VSS 13............SDDAT6 33......................D2 53 ................. INT4 124 ...................VSS 14............SDDAT5 34......................D1 54 .... SCANMODE 125 ................ DUAL 15............SDDAT4 35......................D0 55..106 ........... n.c. 126 ..............VCC3H 16......................A7 36................ FWP# 107 ............. VDDF 127 ................BOOT 17......................A6 37................ FWE# 108 ...........VCC3H 128 ............... MODE 18......................A5 38......................A3 109 ................ VSS 19......................A4 39......................A2 110 .........VDDF_C 20.................FOE# 40...................VSS 111 ...........VCC3H

10 PIN CONFIGURATION

3.2. Hyperstone S4, 50-Pin LGA Package

3.2.1. Pin Configuration - View from Top Side

VSS A4VSS VSS

VSS VCC3H

D5

1

2

3

4

5

6

7

8 9 10 11 12 13 14 15 16 17 18 19 20

21

22

23

24

25

26

27

28293031323334353637383940

41 42 43 44 45

46 47 48 49 50

SDDAT4

VCC3F VCC3F

VCC3H

VDDF_C

VDDC

VDDC_C

IBIAS

RESET#

DUAL (IO5)

D2

D3

D0

FWP# (IO2)

FWE#

A3

A2

BO

OT

(IO4)

MO

DE

(IO

3)

SDD

AT2

SDD

AT3

SDD

AT0

SDC

LK

SDD

AT5 A5

FRD

Y (IO

1) D7

D6

D4

D1

FRD

Y1

FRD

Y2

FRD

Y3

FOE#

A6

A7

SD

DAT

6

SD

DAT

7

SD

DAT

1

SD

CM

D

VC

C3H

VSS

VD

DF

Figure 7.2: Hyperstone S4, 50-Pin LGA Package

PIN CONFIGURATION 11

3.2.2. Pin Cross Reference by Pin Name

Signal Location Signal Location Signal Location Signal Location

A2 ..................... 21 D6..................... 18 SDCLK ............. 13 VCC3H ............. 38 A3 ..................... 22 D7..................... 17 SDCMD ............ 37 VCC3H ............. 47 A4 ..................... 44 DUAL.................. 7 SDDAT0 ........... 12 VDDC ................. 3 A5 ..................... 15 FOE# ................ 31 SDDAT1 ........... 36 VDDC_C ............ 4 A6 ..................... 32 FRDY................ 16 SDDAT2 ........... 10 VDDF................ 40 A7 ..................... 33 FRDY1.............. 28 SDDAT3 ........... 11 VDDF_C............. 2 BOOT ................. 8 FRDY2.............. 29 SDDAT4 ........... 48 VSS .................. 39 D0 ..................... 25 FRDY3.............. 30 SDDAT5 ........... 14 VSS .................. 41 D1 ..................... 20 FWE#................ 23 SDDAT6 ........... 34 VSS .................. 42 D2 ..................... 27 FWP#................ 24 SDDAT7 ........... 35 VSS .................. 43 D3 ..................... 26 IBIAS .................. 5 VCC3F.............. 49 VSS .................. 46 D4 ..................... 19 MODE................. 9 VCC3F.............. 50 D5 ..................... 45 RESET# ............. 6 VCC3H ............... 1

3.2.3. Pin Cross Reference by Location

Location Signal Location Signal Location Signal Location Signal

1................VCC3H 14............SDDAT5 27 .....................D2 40 ................VDDF 2..............VDDF_C 15......................A5 28 ............. FRDY1 41 .................. VSS 3..................VDDC 16................ FRDY 29 ............. FRDY2 42 .................. VSS 4............. VDDC_C 17......................D7 30 ............. FRDY3 43 .................. VSS 5................... IBIAS 18......................D6 31 ................FOE# 44 .....................A4 6.............. RESET# 19......................D4 32 .....................A6 45 .....................D5 7.................. DUAL 20......................D1 33 .....................A7 46 .................. VSS 8..................BOOT 21......................A2 34 ...........SDDAT6 47 ............. VCC3H 9................. MODE 22......................A3 35 ...........SDDAT7 48 ........... SDDAT4 10............SDDAT2 23................ FWE# 36 ...........SDDAT1 49 ..............VCC3F 11............SDDAT3 24................ FWP# 37 ............SDCMD 50 ..............VCC3F 12............SDDAT0 25......................D0 38 .............VCC3H 13.............. SDCLK 26......................D3 39 .................. VSS

12 PIN CONFIGURATION

3.3. Hyperstone S4 Die

3.3.1. Pad Configuration

VS

S

SCAN

OU

T2

VC

C3H

SCAN

OU

T1S

CA

NE

N

VS

SV

CC

3HXT

ALS

ELXT

ALI

INT4

SC

AN

MO

DE

RE

SE

T#V

CC

3HU

AR

T_C

LKU

AR

T_R

XU

AR

T_TX

IBIA

SV

SS

VD

DC

_CV

DD

C

VS

SV

CC

3HV

DD

F

A2A3FWE#FWP# (IO2)

D1D2

D3D4D5

D6D7FRDY (IO1)FRDY1VCC3FVSSFRDY2FRDY3FOE#A4A5A6A7SDDAT4SDDAT5SDDAT6

12367891011121314

34353637

40

3839

4142434445464748

60

5049

515253545556575859

63

64

65

67 6866 74 75 77 787669 70 71 72 73

VCC3HVSSSDCLKSDDAT7SDDAT1VCC3HVSSSDDAT0SDCMDSDDAT3VCC3HVSSVSS

MODE (IO3)BOOT (IO4)19

20

62

21

33

2322

242526272829303132

VSSVCC3HDUAL (IO5)16

17

18V

CC

3HV

DD

F_C

45

VS

S

15

SDDAT2

61

VCC3H

VSSVCC3F

VSSVCC3F

SC

AN

IN2

SC

AN

IN1

Die size:X=3964.76µmY=1319.06µm(not including110um scribe line)

Figure 7.3: Hyperstone S4 Die

PIN CONFIGURATION 13

3.3.2. Pad Cross Reference by Pad Name

Signal Location X Y Signal Location X Y

A2 ..................... 65.........322.64 ....1288.66 SDDAT4............38 ...... 2151.64.... 1288.66 A3 ..................... 64.........403.24 ....1288.66 SDDAT5............37 ...... 2217.36.... 1288.66 A4 ..................... 42.......1878.84 ....1288.66 SDDAT6............36 ...... 2283.08.... 1288.66 A5 ..................... 41.......1944.56 ....1288.66 SDDAT7............32 ...... 2545.96.... 1288.66 A6 ..................... 40.......2010.28 ....1288.66 UART_CLK.......12 ...... 3934.36..... 835.22 A7 ..................... 39.......2076.00 ....1288.66 UART_RX.........11 ...... 3934.36..... 754.62 BOOT ............... 19.......3400.32 ....1288.66 UART_TX .........10 ...... 3934.36..... 688.90 D0 ..................... 61.........630.16 ....1288.66 VCC3F ..............47 ...... 1550.24.... 1288.66 D1 ..................... 60.........695.88 ....1288.66 VCC3F ..............53 ...... 1155.92.... 1288.66 D2 ..................... 59.........761.60 ....1288.66 VCC3F ..............58 ........ 827.32.... 1288.66 D3 ..................... 56.........958.76 ....1288.66 VCC3H..............13 ...... 3934.36..... 915.82 D4 ..................... 55.......1024.48 ....1288.66 VCC3H..............17 ...... 3561.52.... 1288.66 D5 ..................... 54.......1090.20 ....1288.66 VCC3H................2 ...... 3934.36..... 123.46 D6 ..................... 51.......1287.36 ....1288.66 VCC3H..............22 ...... 3203.16.... 1288.66 D7 ..................... 50.......1353.08 ....1288.66 VCC3H..............25 ...... 3006.00.... 1288.66 DUAL ................ 16.......3642.12 ....1288.66 VCC3H..............30 ...... 2677.40.... 1288.66 FOE# ................ 43.......1813.12 ....1288.66 VCC3H..............35 ...... 2348.80.... 1288.66 FRDY................ 49.......1418.80 ....1288.66 VCC3H................5 ...... 3934.36..... 350.38 FRDY1.............. 48.......1484.52 ....1288.66 VCC3H..............70 .......... 30.40..... 678.98 FRDY2.............. 45.......1681.68 ....1288.66 VCC3H..............74 .......... 30.40..... 350.38 FRDY3.............. 44.......1747.40 ....1288.66 VDDC..................6 ...... 3934.36..... 416.10 FWE#................ 63.........483.84 ....1288.66 VDDC_C.............7 ...... 3934.36..... 481.82 FWP#................ 62.........564.44 ....1288.66 VDDF ..................1 ...... 3934.36...... 42.86 IBIAS .................. 9.......3934.36 ..... 613.26 VDDF_C .............4 ...... 3934.36..... 284.66 INT4.................. 77...........30.40 ..... 123.46 VSS...................15 ...... 3934.36.... 1077.02 MODE............... 20.......3334.60 ....1288.66 VSS...................18 ...... 3480.92.... 1288.66 RESET#............ 14.......3934.36 ..... 996.42 VSS...................23 ...... 3137.44.... 1288.66 SCANEN........... 68...........30.40 ..... 825.30 VSS...................24 ...... 3071.72.... 1288.66 SCANIN1.......... 72...........30.40 ..... 547.54 VSS...................29 ...... 2744.12.... 1288.66 SCANIN2.......... 71...........30.40 ..... 613.26 VSS.....................3 ...... 3934.36..... 204.06 SCANMODE..... 78...........30.40 ...... 42.86 VSS...................34 ...... 2414.52.... 1288.66 SCANOUT1...... 67...........30.40 ..... 905.90 VSS...................46 ...... 1615.98.... 1288.66 SCANOUT2...... 66...........30.40 ..... 996.42 VSS...................52 ...... 1221.64.... 1288.66 SDCLK.............. 33.......2480.24 ....1288.66 VSS...................57 ........ 893.04.... 1288.66 SDCMD ............ 27.......2874.56 ....1288.66 VSS...................69 .......... 30.40..... 744.70 SDDAT0 ........... 28.......2808.84 ....1288.66 VSS...................73 .......... 30.40..... 416.10 SDDAT1 ........... 31.......2611.68 ....1288.66 VSS.....................8 ...... 3934.36..... 547.54 SDDAT2 ........... 21.......3268.88 ....1288.66 XTALI................76 .......... 30.40..... 204.06 SDDAT3 ........... 26.......2940.28 ....1288.66 XTALSEL ..........75 .......... 30.40..... 284.66

14 PIN CONFIGURATION

3.3.3. Pad Cross Reference by Pad Number

Signal Location X Y Signal Location X Y

VDDF.................. 1 ...... 3934.36 ..... 42.86 A6......................40 ...... 2010.28.... 1288.66 VCC3H ............... 2 ...... 3934.36 .... 123.46 A5......................41 ...... 1944.56.... 1288.66 VSS..................... 3 ...... 3934.36 .... 204.06 A4......................42 ...... 1878.84.... 1288.66 VDDF_C ............. 4 ...... 3934.36 .... 284.66 FOE#.................43 ...... 1813.12.... 1288.66 VCC3H ............... 5 ...... 3934.36 .... 350.38 FRDY3 ..............44 ...... 1747.40.... 1288.66 VDDC.................. 6 ...... 3934.36 .... 416.10 FRDY2 ..............45 ...... 1681.68.... 1288.66 VDDC_C............. 7 ...... 3934.36 .... 481.82 VSS...................46 ...... 1615.98.... 1288.66 VSS..................... 8 ...... 3934.36 .... 547.54 VCC3F ..............47 ...... 1550.24.... 1288.66 IBIAS................... 9 ...... 3934.36 .... 613.26 FRDY1 ..............48 ...... 1484.52.... 1288.66 UART_TX ......... 10 ...... 3934.36 .... 688.90 FRDY ................49 ...... 1418.80.... 1288.66 UART_RX......... 11 ...... 3934.36 .... 754.62 D7 .....................50 ...... 1353.08.... 1288.66 UART_CLK....... 12 ...... 3934.36 .... 835.22 D6 .....................51 ...... 1287.36.... 1288.66 VCC3H ............. 13 ...... 3934.36 .... 915.82 VSS...................52 ...... 1221.64.... 1288.66 RESET#............ 14 ...... 3934.36 .... 996.42 VCC3F ..............53 ...... 1155.92.... 1288.66 VSS................... 15 ...... 3934.36 ... 1077.02 D5 .....................54 ...... 1090.20.... 1288.66 DUAL ................ 16 ...... 3642.12 ... 1288.66 D4 .....................55 ...... 1024.48.... 1288.66 VCC3H ............. 17 ...... 3561.52 ... 1288.66 D3 .....................56 ........ 958.76.... 1288.66 VSS................... 18 ...... 3480.92 ... 1288.66 VSS...................57 ........ 893.04.... 1288.66 BOOT................ 19 ...... 3400.32 ... 1288.66 VCC3F ..............58 ........ 827.32.... 1288.66 MODE............... 20 ...... 3334.60 ... 1288.66 D2 .....................59 ........ 761.60.... 1288.66 SDDAT2 ........... 21 ...... 3268.88 ... 1288.66 D1 .....................60 ........ 695.88.... 1288.66 VCC3H ............. 22 ...... 3203.16 ... 1288.66 D0 .....................61 ........ 630.16.... 1288.66 VSS................... 23 ...... 3137.44 ... 1288.66 FWP#................62 ........ 564.44.... 1288.66 VSS................... 24 ...... 3071.72 ... 1288.66 FWE#................63 ........ 483.84.... 1288.66 VCC3H ............. 25 ...... 3006.00 ... 1288.66 A3......................64 ........ 403.24.... 1288.66 SDDAT3 ........... 26 ...... 2940.28 ... 1288.66 A2......................65 ........ 322.64.... 1288.66 SDCMD ............ 27 ...... 2874.56 ... 1288.66 SCANOUT2 ......66 .......... 30.40..... 996.42 SDDAT0 ........... 28 ...... 2808.84 ... 1288.66 SCANOUT1 ......67 .......... 30.40..... 905.90 VSS................... 29 ...... 2744.12 ... 1288.66 SCANEN...........68 .......... 30.40..... 825.30 VCC3H ............. 30 ...... 2677.40 ... 1288.66 VSS...................69 .......... 30.40..... 744.70 SDDAT1 ........... 31 ...... 2611.68 ... 1288.66 VCC3H..............70 .......... 30.40..... 678.98 SDDAT7 ........... 32 ...... 2545.96 ... 1288.66 SCANIN2 ..........71 .......... 30.40..... 613.26 SDCLK.............. 33 ...... 2480.24 ... 1288.66 SCANIN1 ..........72 .......... 30.40..... 547.54 VSS................... 34 ...... 2414.52 ... 1288.66 VSS...................73 .......... 30.40..... 416.10 VCC3H ............. 35 ...... 2348.80 ... 1288.66 VCC3H..............74 .......... 30.40..... 350.38 SDDAT6 ........... 36 ...... 2283.08 ... 1288.66 XTALSEL ..........75 .......... 30.40..... 284.66 SDDAT5 ........... 37 ...... 2217.36 ... 1288.66 XTALI ................76 .......... 30.40..... 204.06 SDDAT4 ........... 38 ...... 2151.64 ... 1288.66 INT4 ..................77 .......... 30.40..... 123.46 A7 ..................... 39 ...... 2076.00 ... 1288.66 SCANMODE .....78 .......... 30.40...... 42.86

PIN CONFIGURATION 15

3.4. Package Dimensions

3.4.1. 128-Pin TQFP Package

b

D

D1

E1Index

A1

A2

L

E

e

Figure 7.4: Hyperstone S4 Package-Outline

Symbol Term Definition

A1 Standoff height Height from ground plane to bottom edge of package

A2 Package height Height of package itself

E, D Overall length & width Length and width including leads

E1, D1 Package length & width Length and width of package

L Lead footprint Length of flat lead section

E Lead pitch Lead pitch

B Lead width Width of a lead

16 PIN CONFIGURATION

3.4.1. 128-Pin TQFP Package (continued)

Hyperstone S4, 128-Pin Package

Symbol Dimensions in Millimeters Dimensions in Inches

Min. Nom. Max. Min. Nom. Max

A1 0.05 0.10 0.15 .002 .004 .006

A2 0.95 1.00 1.05 .037 .039 .041

E, D 15.80 16.00 16.20 .622 .630 .638

E1, D1 13.00 14.00 14.10 .547 .551 .555

L 0.45 0.60 0.75 .018 .024 .030

B 0.13 0.18 0.23 .005 .007 .009

e 0.40 .0157

PIN CONFIGURATION 17

3.4.2. 50-Pin LGA Package

AA1

a1

BB1

Bottom view:

Side view:

C

b1

a2

b2 L

Figure 7.5: Hyperstone S4 Package-Outline

18 PIN CONFIGURATION

3.4.2. 50-Pin LGA Package (continued)

Hyperstone S4, 50-Pin LGA Package

Symbol Dimensions in Millimeters Dimensions in Inches

Min. Nom. Max. Min. Nom. Max

A 6.90 7.00 7.10 0.272 0.276 0.280

A1 6.00 0.236

B 3.90 4.00 4.10 0.154 0.157 0.161

B1 3.00

C 0.70 0.028

a1 0.50 0.020

a2 1.00 0.039

b1 0.20 0.25 0.30 0.008 0.010 0.012

b2 0.35 0.40 0.45 0.014 0.016 0.018

L 0.225 0.325 0.425 0.009 0.013 0.017

PIN CONFIGURATION 19

3.5. Bus Signals

3.5.1. Bus Signals for the S4 Flash Memory Controller

The following table is an overview of the bus signals of the Hyperstone S4 flash memory controller. The signal states are defined as I = input, O = output, pu = pullup, pd = pulldown, h = hold and s = strong.

Status Pins S3D-16XT

Pins S3D-16XL

Pins S3D-16XR

Signal Name Description

Flash Memory Control O 1 1 1 FWE# Flash Write Enable O 1 1 1 FOE# Flash Output Enable

I/pu/s 1 1 1 FRDY Flash Ready/Busy (IO1), Chip 0/commonO/pd 1 1 1 FWP# Flash Reset/Write Protect (IO2) I/pu/s 3 3 3 FRDY1..3 Flash Ready/Busy, Chips 1..3 separate

SD/MMC Card Interface I/pu 1 1 1 SDCLK SD/MMC Clock

I/O/pu 1 1 1 SDCMD SD/MMC Command I/O/pu 8 8 8 SDDAT0..7 SD/MMC Data 0..7

General Control O 6 6 6 A(7..2) Address Bus I/O 8 8 8 D(7..0) Data Bus I/pu 1 1 1 MODE SD/MMC Select (IO3) I/pu 1 1 1 BOOT Boot OCR Wait Select (IO4) I/pu 1 1 1 DUAL Dual Voltage Support Select (IO5)

I 1 1 1 RESET# Reset

Debugging I/pd 1 1 1 UART_CLK Debugging UART Clock I/pu 1 1 1 UART_RX Debugging UART Receive Data O 1 1 1 UART_TX Debugging UART Transmit Data

Test I/pd 1 1 1 INT4 Interrupt 4, Boot Select (for Test) I/pu 1 1 1 XTALI Test Clock Input I/pu 1 1 1 XTALSEL Test Clock Select I/pd 1 1 1 SCANEN Scan Test Enable I/pd 1 1 1 SCANMODE Scan Mode Select I/pd 2 2 2 SCANIN1..2 Scan Path Input O/pd 2 2 2 SCANOUT1..2 Scan Path Output

Flash Memory and Core Voltage Regulators O 1 1 1 VDDF 1.8V Flash Power Supply Output 1 1 1 VDDF_C 1.8V Flash Regulator Capacitor

O 1 1 1 VDDC 1.8V Core Power Supply Output

20 PIN CONFIGURATION

Status Pins S3D-16XT

Pins S3D-16XL

Pins S3D-16XR

Signal Name Description

1 1 1 VDDC_C 1.8V Core Regulator Capacitor 1 1 1 IBIAS Regulator Bias Generation Resistor

Power Supply 1 1 1 VCC3H Host Supply Connection 1 1 1 VCC3F Flash Bus I/O Supply 1 1 1 VSS Host Ground Connection 22 - - Not connected

Total: 128 64 52

Table 7.1: Bus Signals for the S4 Flash Memory Controller

3.5.2. Bus Signal Description

The following section describes the bus signals for the Hyperstone S4 controller in detail. In the following signal description, the signal states are defined as I = input, O = output, U = pull-up, D = pull-down.

States Names Use

O FWE# NAND Flash Memory Write Enable. Connect to the flash WE# pin.

O FOE# NAND Flash Output Enable. Connect to flash RE# pin.

I,U FRDY NAND Flash Ready/Busy signal.

I,U FRDY1..3 NAND Flash Ready/Busy signals. Depending on the firmware version, all Flash Ready/Busy signals share a common connection to FRDY, or separate connections of the flash chips to the four FRDY, FRDY1..3 inputs are needed.

O,D FWP# NAND Flash Write Protect signal. Connect to the flash WP# pin.

I SDCLK SD/MMC Interface Clock input

O/I,U SDCMD SD/MMC Interface Command.

O/I,U SDDAT0..7 SD/MMC Interface Data 0..7.

O A7..A2 The address bits A7..A2 represent the CPU core’s address bus. A4..A7 are used as chip select signals for up to 4 Flash memory chips, A2 and A3 are used for the CLE and ALE signals.

O/I D7..D0 Data bus. The signals D7..D0 represent the bidirectional data bus. At a read access, data is transferred from the data bus to the register set or to the instruction cache only at the cycle corre-sponding to the last actual read access cycle, thus inhibiting gar-bled data from being transferred. At a write access, the data bus signals are activated during the address setup, write and bus hold cycle(s).

PIN CONFIGURATION 21

3.5.2. Bus Signal Description (continued)

States Names Use

I,U MODE SD/MMC mode select. If this pin is low, SD mode is selected, if this pin is high (or open), MMC mode is selected.

I,U BOOT SD/MMC boot mode select. If this pin is high (or open), the S4 boots the firmware from the flash chip without interaction with the SD/MMC interface. If this pin is low, the S4 waits with the firmware boot until a valid voltage range is received via ACMD41 (SD) or CMD1 (MMC).

I,U DUAL SD/MMC dual voltage select. If this pin is high (or open), the SD/MMC interface initializes as a high voltage card (2.7V to 3.6V support signaled in the OCR). If this pin is low, the SD/MMC interface initializes as a dual voltage card (additional 1.65V to 1.95V support signaled in the OCR).

I RESET# Reset processor. RESET# low resets the processor to the initial state and halts all activity. RESET# must be low for at least one cycle. On a transition from low to high, a Reset exception occurs and the processor starts execution at the Reset entry determined by the INT4 state. The transition may occur asynchronously to the clock.

If the reset input is not needed, this pin must be high. In this case, an internal voltage detector will generate a reset pulse of about 0.5ms when the supply voltage has reached about 1.5V.

I/U UART_CLK Debugging UART Clock Input.

I/U UART_RX Debugging UART Receive Data Input.

O/U UART_TX Debugging UART Transmit Data Input.

I,D INT4 Boot Select Pin. The INT4 state on a reset exception determines the location of the reset boot procedure. If INT4 is low on reset, the S4 begins booting from the internal ROM, if INT4 is high on reset, the S4 begins booting from the external MEM3 ROM for testing. Controlled by the corresponding FCR bits, this signal may also be used to interrupt the CPU.

I/U XTALI Test Clock Input.

I/U XTALSEL Internal/External Clock Select Input. Connect to GND to use the XTALI pin as clock input. Leave open to use the Internal R/C Oscillator. In this case, the XTALI pin should also be left open.

I/D SCANEN Scan Test Enable signal. Do not connect.

I/D SCANMODE Scan Mode Select signal. Do not connect.

I/D SCANIN1..2 Scan Input 1 and 2 signal. Do not connect.

O SCANOUT1..2 Scan Output 1 and 2 signal. Do not connect.

22 PIN CONFIGURATION

3.5.2. Bus Signal Description (continued)

States Names Use

VDDF Flash Memory 1.8V Power Supply Regulator output. Connect to VCC3F if the flash I/O voltage is 1.8V. Connect to the flash power supply as well if the flash supply voltage is 1.8V. Connect a 100nF ceramic capacitor to GND.

VDDF_C Flash Memory 1.8V Power Supply Regulator Stabilizing Capacitor. Connect a 1uF ceramic capacitor to GND.

VDDC Controller Core 1.8V Power Supply Regulator output. Connect a 10nF ceramic capacitor to GND.

VDDC_C Controller Core 1.8V Power Supply Regulator Stabilizing Capacitor. Connect a 1uF ceramic capacitor to GND.

IBIAS Controller Regulator Bias Generation Resistor. Connect a 68kΩ 1% resistor to VCC3H.

VCC3H Controller Regulator and Host I/O power supply. Connect this to the SD/MMC host power supply.

VCC3F Controller Flash I/O power supply. Connect to the SD/MMC host power supply or to VDDF depending on the flash memory I/O levels.

VSS Controller Core and I/O ground. Connect to the SD/MMC host ground.

FUNCTIONAL DESCRIPTION 23

4. Functional Description

4.1. Block Diagram

Instruction Cache

Interrupt

Controller

32 Bit Timer

Watchdog Power Down

Control

Bus Controller

Load/ Store Unit

ALU/Shifter32 Bit

Register File for RISC Unit 96 Registers 32 Bit Wide

Bus Interface On-Chip I/O

RAM 20 KByte

1.8V Core Regulator

1.8V Flash Regulator

Flash Control

ECC/CRC Unit

Boot ROM 16 KByte

Control Logic

Card Interface

SD/MMCRegisters

2x512 Byte Sector Buffers

4 Flash Memory Chips

8 Bit Wide

up to 4 GByte

SD/MMC Interface

UART Debug

4.2. System Memory Map

The memory address space is divided into seven partitions as follows:

Address (Hex) Address Space Memory Type

0000 0000..3FFF FFFF MEM0 not available

4000 0000..7FFF FFFF MEM1 not available (external SRAM)

8000 0000..BFFF FFFF MEM2 external Flash Memory

C000 0000..C7FF FFFF IRAM Internal RAM

C800 0000..CFFF FFFF IRAM SD Sector Buffers

D000 0000..D7FF FFFF MMIO Memory-Mapped I/O

D800 0000..DFFF FFFF IROM Internal ROM

E000 0000..FFFF FFFF MEM3 not available (external ROM)

24 FUNCTIONAL DESCRIPTION

Access to the registers of the SD/MMC and flash memory interface takes place in the processor’s Memory Mapped I/O address space.

4.3. Flash Memory Interface

NAND type flash memory chips are connected to the Hyperstone S4 as described below.

Flash Chip Signal S4 Signal

CLE A2

ALE A3

CE# one of A7..A4

WE# FWE#

RE# FOE#

I/O 0 ... I/O 7 D0 ... D7

WP# FWP#

Ready/Busy# FRDY

When a NAND type flash memory chip is connected, the FCR bit 7 must remain set in the default reset state (1). Switching this bit to 0 with a NAND type flash memory chip connected may cause a collision on the hyperstone S4 data bus.

The FWE# and FOE# control signals are activated on any MEM2 write or read access when address bit A22 is set to zero. Address lines A7 to A2 are used for control signal and chip select generation. Address bits A1 to A0 should not be connected and should be zero on a MEM2 access so that word accesses are possible.

Setting A22 to one on a MEM2 write or read access inhibits the generation of the FWE# and FOE# signals. This mode may be used to pre-set the address or data lines to a specific value without causing an actual access.

At most 4 NAND type flash chips can be connected to the Hyperstone S4. Since address bit A2 is used as CLE, double-word flash accesses are not possible. Flash chip 0 CE# is A4, chip 1 CE# is A5, chip 2 CE# is A6, chip 3 CE# is A7.

During reset, A2.. A7 and FWE#, FOE# are high, FWP# is low.

4.4. Reset and ROM Boot

4.4.1. Boot Selection on Reset

The S4 uses the INT4 line state at reset to select between booting from internal boot ROM and booting from external MEM3 (only for test functionality). The INT4 pad has an internal pull-down resistor so that INT4 is low when INT4 is not connected.

If the INT4 line is high at reset, the S4 reset begins fetching instructions from MEM3 address FFFF FFF816. If the INT4 line is low at reset, the S4 begins booting from it’s internal boot ROM.

FUNCTIONAL DESCRIPTION 25

4.4.2. Internal ROM Boot Process

The S4 has 16 Kbytes of internal ROM at address D800 000016 with a wraparound modulo 16 Kbytes up to DFFF FFFF16. When the interrupt 4 input of the S4 is low (or open) at reset, the MCR trap table bits (bits 14..12) are initialized to 110 so that the trap table is located at the end of the internal ROM, and the reset trap begins executing the boot ROM code at DFFF FFF816.

The internal ROM present on the S4 performs the following actions on reset when booting is done from ROM:

The S4 processor is initialized.

MODE (IO3) is switched to output driving 0 or 1, depending on the state sensed at MODE. If MODE is 0, the controller initializes in SD mode, if MODE is 1, the controller initializes in MMC mode. BOOT (IO4) is switched to output driving 0 or 1, depending on the state sensed at BOOT. The sensed value is saved to be used later in the booting process. All Flash chips are deselected.

The SD interface is initialized to a default configuration and brought into the reset state.

The Boot bit in the SD Flags Register is checked. If this bit indicates a high level on SDCMD or SDDAT0, control proceeds to firmware boot from flash, else control proceeds to the SD interface boot.

For the SD interface boot, the S4 waits until the SD interface state machine reset is complete (when the host has sent the first clocks), then determines the device ID of flash chip 0 and stores this information, and sets up a data sector containing a magic number, the controller’s revision ID, the flash device ID, and the value of the SD Mode Select register (will be 1 for MMC and 2 for SD mode). When CMD61 is received, this sector is transferred to the host that can use this information to decide about the correct firmware files. The next host command is used to download a firmware file. The number of sectors in this firmware file is specified in the command argument. The S4 reads the specified number of sectors through the SD interface, the downloaded code is put into IRAM starting at address C000 000016.

If any other command has been received instead of CMD61, the SD interface boot is aborted and control proceeds to normal firmware boot from flash.

For booting from flash, the S4 waits until the voltage detector indicates a supply voltage of at least 2.5V. Then the sensed state of the BOOT input is checked. If the value was low, the S4 waits until the first CMD1 (in MMC mode) or ACMD41 (in SD mode) with a valid voltage range has been received from the host. This wait is skipped if BOOT has been sensed high.

After that, the S4 waits until the first flash chip Ready/Busy line goes high, then waits for another 2ms (assuming 16 MHz clock), then polls the first flash chip status register until this indicates that the flash is ready. Now the Anchor Block is searched. If the Anchor Block is not found or if there is an uncorrectable error when loading the firmware, the S4 falls back to booting from the SD interface. If the Anchor Block is found, a copy is stored in the SD sector buffer. Then, a pre-boot routine at offset 0F416 in the sector buffer is called. After return, the S4 processor proceeds to load the firmware sectors from Flash 0 using the Anchor Block information in the sector buffer.

For the boot from flash chip 0, the location numbers stored in the anchor block are taken as page numbers of the flash chip.

26 FUNCTIONAL DESCRIPTION

4.4.2. Internal ROM Boot Process (continued)

There are two parameters in the Anchor Sector that modify the sector read routine for booting. A byte at 0F316 specifies the sector size in 512 byte units. A word at 0EC16 specifies a subroutine called from the sector read routine that outputs the correct number of address bytes to the flash memory. These are initialized to 1, for a sector size of 512 bytes, and to a routine sending the address bytes needed by the Samsung 2Gbit (K9K2G08U0M) flash chips. In case the Anchor sector could not be found, the search loop is retried with a different routine sending the address bytes needed by the Samsung 512Mbit (K9F1208U0M) flash chips. For the firmware boot later, the correct values for the sector size and address routine from the Anchor sector are used.

After the Anchor sector has been found and loaded, the parameters stored there overwrite the boot time initialization for the parameters.

After booting, the firmware is started via a TRAP 63 instruction with the trap table located at the beginning of the IRAM.

The controller revision ID is ID Byte 3 Description

0xD1 S4 SD/MMC Controller, first revision

0xD2 S4 SD/MMC Controller, second revision

For the controller revision 0xD1, the following sub-revisions are defined:

ID Byte 2 Description

0 S4 revision U1A

For the controller revision 0xD2, the following sub-revisions are defined: ID Byte 2 Description

0 S4 revision U1B

1 S4 revision U1C

This manual describes the controller revision 0xD2.

4.5. S4 Controller Revisions

The S4 controller, revision U1A, has the following differences to the specification:

Only limited configuration is possible for the internal clock oscillator.

The wait for ACMD41 or CMD1 during firmware boot (BOOT pin low) does not work.

The regulator disable functionality is not there, FCR bit 11 is always 1.

The Power-On-Reset circuit is over-sensitive to noise on the power supply.

The S4 controller, revision U1B, has the following differences to the specification:

The wait for ACMD41/CMD1 during boot (BOOT pin low) does not work in SPI mode.

All these are corrected in the U1C revision.

FUNCTIONAL DESCRIPTION 27

4.6. Example Schematics

This section contains simplified schematics for a single-voltage card using a 3.3V flash, and for a dual-voltage card using a 1.8V flash. The host connection and the connection between controller and flash are not shown in detail.

S4

SD...HostA2,A3

A4..A7D0..D7FWE#FOE#FWP#FRDY

FRDY1..3

3.3V

3.3V

VSS

VCC

Signals

Flash

BOOT

MODE

DUAL3.3V

RESET#

IBIAS

3.3V

VCC3H

VCC3F

VSS VDDC_C

VDDC10nF

1uF

68k1%

connect as required

Figure 6: Hyperstone S4 High Voltage Card example

S4

SD...HostA2,A3

A4..A7D0..D7FWE#FOE#FWP#FRDY

FRDY1..3

3.3V

VSS

VCC

Signals

Flash

BOOT

MODE

DUAL3.3V

RESET#

IBIAS

3.3V

VCC3H

VSS VDDC_C

VDDC10nF

1uF

68k1%

connect as required

VDDF_C

VDDF100nF

1uF

VCC3F

1.8V

Figure 7: Hyperstone S4 Dual Voltage Card example

28 ELECTRICAL SPECIFICATIONS

5. Electrical Specifications

5.1. DC Characteristics

Absolute Maximum Ratings

Case temperature TC under Bias: -25°C to +85°C extended temperature range on request Storage Temperature: -40°C to +125°C Voltage on any Pin with respect to ground: -0.5V to VCC + 0.5V

D.C. Parameters

Data transfer mode: Supply Voltage VCC3H, VCC3F: 1.65V to 3.6V Regulator output VDDC: 1.80V ± 4% Regulator output VDDF: 1.87V ± 4% Regulator current VDDC, VDDF: 50 mA max Voltage drop VDDC, VDDF at 50mA: 100 mV max Case Temperature TCASE: -25°C to +85°C

Symbol Parameter Min Max Unit Notes

VIL Input LOW Voltage -0.3 +0.8 V

VIH Input HIGH Voltage 2.0 VCC+0.3 V

VOL Output LOW Voltage 0.4 V at 4mA

VOH Output HIGH Voltage 2.4 V at 1mA

VIL Input LOW Voltage, SD pins -0.3 25% V Fraction of VCC3H

VIH Input HIGH Voltage, SD pins 62.5% VCC+0.3 V Fraction of VCC3H

VOL Output LOW Voltage, SD pins 12.5% V at 100µA, Fraction of VCC3H

VOH Output HIGH Voltage, SD pins 75% V at 100µA, Fraction of VCC3H

ICC Operating Current

Sleep mode Operating, 20 MHz Operating, 40 MHz

0.2 25 40

mAmAmA

ILI Input Leakage Current ±10 µA

ILO Output Leakage Current ±10 µA

CI/O Input/output Capacitance 10 pF

Table 7.2: DC Characteristics

ELECTRICAL SPECIFICATIONS 29

5.2. AC Characteristics

5.2.1. SD Interface AC Characteristics, SD 1.01 and MMC 3.31 Mode

The SD interface characteristics refer to the symbols used in the timing definition of the SD 1.01 and MMC 3.31 standards.

Symbol Parameter Min Max Units Notes

fPP Clock, Data transfer mode 25 MHz CL ≤ 100pF

fOD Clock, Identification mode 400 kHz CL ≤ 250pF

tWL Clock low time 10 ns CL ≤ 100pF

tWH Clock high time 10 ns CL ≤ 100pF

tTLH Clock rise time 10 ns CL ≤ 100pF

tTHL Clock fall time 10 ns CL ≤ 100pF

tWL Clock low time 50 ns CL ≤ 250pF

tWH Clock high time 50 ns CL ≤ 250pF

tTLH Clock rise time 50 ns CL ≤ 250pF

tTHL Clock fall time 50 ns CL ≤ 250pF

tISU CMD, DAT input setup time 5 ns CL ≤ 25pF

TIH CMD, DAT input hold time 5 ns CL ≤ 25pF

tOLDY CMD, DAT output delay 0 14 ns CL ≤ 25pF, Data transfer

tOLDY CMD, DAT output delay 0 50 ns CL ≤ 25pF, Identification

5.2.2. SD Interface AC Characteristics, SD 1.10 and MMC 4.0 Mode

tbd

30 ELECTRICAL SPECIFICATIONS

5.2.3. Flash Memory Interface AC Characteristics

The AC Characteristics for the flash memory interface are based on the S4 processor clock cycle time tCPU. The tables list the flash memory interface timing based on the tCPU value. There are two different tables, one for a single-cycle flash memory access (MEM2Access=1), and one for a two-cycle flash memory access (MEM2Access=2).

The tWP and tRP values given in these tables are the nominal values, these may be adjusted by MCR settings in the firmware.

Symbol Parameter Min Max Units

TCLS CLE setup time tCPU ns

TCLH CLE hold time tCPU/2 ns

TCS CE setup time tCPU ns

TCH CE hold time tCPU ns

TALS ALE setup time tCPU ns

TALH ALE hold time tCPU/2 ns

TDS Data Setup time tCPU/2 – 5ns ns

TDH Data hold time tCPU/2 – 5ns ns

TWP WE pulse width tCPU/2 ns

TWC Write cycle time tCPU ns

TWH WE high hold time tWC – tWP – 5ns ns

TRP RE pulse width tCPU/2 ns

TRC Read cycle time tCPU ns

TREA RE access time tCPU – 10ns ns

TREH RE high hold time tRC – tRP – 5ns ns

TCEH CE high hold time tCPU*4 ns

TWHR WE high to RE low tCPU*2 ns

Table 7.3: Flash Interface AC Characteristics, single-cycle access

ELECTRICAL SPECIFICATIONS 31

Symbol Parameter Min Max Units

TCLS CLE setup time tCPU/2 ns

TCLH CLE hold time tCPU/2 ns

TCS CE setup time tCPU ns

TCH CE hold time tCPU ns

TALS ALE setup time tCPU/2 ns

TALH ALE hold time tCPU/2 ns

TDS Data Setup time tCPU ns

TDH Data hold time tCPU/2 – 5ns ns

TWP WE pulse width tCPU ns

TWC Write cycle time tCPU*2 ns

TWH WE high hold time tWC – tWP – 5ns ns

TRP RE pulse width tCPU ns

TRC Read cycle time tCPU*2 ns

TREA RE access time tCPU*1.5 – 10ns ns

TREH RE high hold time tRC – tRP – 5ns ns

TCEH CE high hold time tCPU*4 ns

TWHR WE high to RE low tCPU*2 ns

Table 7.4: Flash Interface AC Characteristics, two-cycle access

32

Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. Hyperstone does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent licences are implied. Hyperstone reserves the right at any time without notice to change the said circuitry and this product specification. Hyperstone has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. Specific testing of all circuit parameters is not necessarily performed.

www.hyperstone.com

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Ordering Information The following table lists the different variants and the corresponding ordering code.

Device Revision Package Order Code

S4 U1A LGA 50 S04U1A-LG050RC

S4 U1A TQFP 128 S04U1A-TQ128RC

S4 U1A Good Die S04U1A-DI000RC

S4 U1A Wafer S04U1A-WF000RC

S4 U1B LGA 50 S04U1B-LG050RC

S4 U1B TQFP 128 S04U1B-TQ128RC

S4 U1B Good Die S04U1B-DI000RC

S4 U1B Wafer S04U1B-WF000RC

S4 U1C LGA 50 S04U1C-LG050RC

S4 U1C TQFP 128 S04U1C-TQ128RC

S4 U1C Good Die S04U1C-DI000RC

S4 U1C Wafer S04U1C-WF000RC