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Haps-54 March2009 Manual

Oct 22, 2015

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john92691

ASIC Prototyping

  • HAPS

    High-performance ASIC Prototyping System

    MotherboardHAPS-54

  • 2 HAPS-54High-performance ASIC Prototyping System

    Revision History

    Date Name Comment

    Sep 04, 2007 Bo Nilsson Initial versionSep 05, 2007 Bo Nilsson Corrected GCLK numbering in table 9 and 11Sep 17, 2007 Bo Nilsson Cooling fans are not mounted on delivery (p. 3, 44)

    Cut the VCCO wires before connecting together GPIO headers (p. 24, 56)Sep 27, 2007 Bo Nilsson Minor correctionsOct 04, 2007 Bo Nilsson Minor correctionsNov 13, 2007 Bo Nilsson p43: ALERT LED lights green indicating no overheatingNov 14, 2007 Bo Nilsson p69: Added pin numbers for the connectorsNov 23, 2007 Bo Nilsson p59, 60: Corrected bank numbers in HapsTrak connectors 4 and 7Dec 03, 2007 Bo Nilsson p10: Updated fig 3Dec 10, 2007 Bo Nilsson p37: Create lower frequencies with internal PLLs

    p41: Updated text about SPI Flash PROMsJan 09, 2008 Bo Nilsson Updated fig 45, 60, 61 and 62Feb 04, 2008 Bo Nilsson Updated table Global Clocks on page 66Feb 07, 2008 Bo Nilsson p24: Updated fig 26Mar 18, 2008 Bo Nilsson STB2_1x1 replaces STB1_1x1 Updated the Self-TestApr 02, 2008 Bo Nilsson p66: Renamed A_RESET, etc to A_RESET_n, etcMay 15, 2008 Bo Nilsson Updated section Board SetupJun 26, 2008 Bo Nilsson p49: OSC2 default is 52 MHz

    HAPS SupportNet is moved to http://hapssupportnet.synplicity.comNov 17, 2008 Bo Nilsson p3: Support is now on SolvNet. Documentation is still on SupportNet.Dec 03, 2008 Bo Nilsson p34: Output frequency from single-ended PLL defined up to 266 MHzFeb 26, 2009 Bo Nilsson p43: Updated table 13 (Power Good LED)Mar 11, 2009 Bo Nilsson p17: Updated figure 12; p69: Added delay for global signals between FPGAsMar 20, 2009 Bo Nilsson p63, 64: Corrected the indexes for the tables A-B and D-C

    HAPS-54 2009, Synopsys, Inc. March 20, 2009

    S/N

  • 3HAPS-54High-performance ASIC Prototyping System

    Synopsys, Inc.

    General Information

    Contents of the boxA basic HAPS-54 delivery contains the following: This manual The manual HAPS Interconnect Boards & Cables The manual Custom Daughter Boards The STB2_1x1 User Guide 1 CD with manuals, application notes and design files 1 HAPS-54 board with 4 Xilinx Virtex-5 LX330 devices in FF1760 packages 2 interconnect boards CON_1x2 4 interconnect boards CON_2x1B 1 interconnect board CON_2x2 1 interconnect cable CON_CABLE40 2 TERM-TOP_1x1 1 STB2_1x1 (Self-Test Board) for testing the HAPS-54 board 1 LAB_1x1 experiment board 2 ribbon cables for GPIO, 320 mm [order code: HX-GPIO_CABLE] 7 MMCX coax cables, 300 mm [order code: HX-MMCX_CABLE] 1 RS232/SERIAL cable, [order code: HX-RS232_DATAPORT] 1 RS232/USB cable, [order code: HX-RS232_USB] 4 fans to be mounted on the FPGAs, [order code: HX-EBF42.5] 1 power cable (ATX MiniFit to Phoenix FMC plug), [order code: HX-ATX_ADAPTER] A sample of 5 HapsTrak II socket connectors (ASP-125516-03) 1 wrist strap

    Power RequirementA complete system with HAPS-54 and daughter boards may require as much as 40A on 5V.Use a power supply such as TP-II 550PEC from Antec (http://www.antec.com).

    Technical SupportThis manual contains all information you need to use the HAPS-54 motherboard. For each standard daughter board you are using, you should refer to the documentation provided with that board. If you want to design your own daughter boards, please see the manual Custom Daughter Boards.

    Technical support is available on SolvNet at https://solvnet.synopsys.com.

    SupportNetFor registered customers we offer complete documentation of all HAPS products. Please register at http://hapssupportnet.synplicity.com.

    On SupportNet you will find the latest releases of all HAPS manuals, application notes, board files, HapsMap and other useful information.

  • 4 HAPS-54High-performance ASIC Prototyping System

    Synopsys, Inc.

    ContentsRevision History ............................................................2

    General Information .............................................................3Contents of the box ........................................................3

    Power Requirement ..................................................3Technical Support ..........................................................3

    SupportNet ................................................................3Overview ................................................................................6

    Features ..........................................................................6Concept ..........................................................................8

    Daughter Boards .......................................................8Inter-FPGA Connections ...........................................9Height Dimension Rules .........................................10Example of a HAPS System ...................................10HapsTrak .................................................................11

    Board Layout Top Side ................................................12Board Layout Bottom Side ..........................................13I/O Signals & Interconnects ........................................15

    VCCO Regions .........................................................15I/O Signals ..............................................................15Inter-FPGA Connections .........................................16General Purpose I/Os ..............................................16

    Clocks ..........................................................................16Getting Started ....................................................................18

    Applying Power the First Time ...................................18Test the Board ..............................................................19Adding Daughter Boards .............................................19Connecting Clocks.......................................................20Board Setup (SETUP switch) ......................................20Power-Up .....................................................................20Board Setup (Advanced Options) ................................20Configuring the Devices ..............................................21Reset & Reconfigure ....................................................22

    Expansion and I/Os .............................................................23HapsTrak II Connectors ...............................................23

    Signal Levels and I/O Standards .............................24GPIOs ..........................................................................24

    Power ....................................................................................25VCCO Regions ..............................................................25VCCO in the HapsTrak II Connectors ..........................27Battery .........................................................................27

    Clocks ...................................................................................28Clock Generators .........................................................28Global Single-Ended 1-to-1 Clocks .............................29Global Differential PLL Clocks ...................................31Global Single-Ended PLL Clocks ...............................33

  • 5HAPS-54High-performance ASIC Prototyping System

    Synopsys, Inc.

    Direct Clocks ...............................................................35Synchronizing Clocks ..................................................36

    Direct coax inputs ...................................................37Using a PLL to synchronize clocks ........................37Distributing clock hierarchies .................................37

    Local Clocks ................................................................38Configuration.......................................................................39

    JTAG Cable .................................................................40SPI Flash PROMs ...................................................41

    CompactFlash ..............................................................42Board Status ........................................................................43

    Voltage Monitoring ......................................................43Temperature Monitoring ..............................................43Self-Test .......................................................................44

    Board Setup .........................................................................46Board Supervisor Registers .........................................47Setup via the Data Port ................................................54

    Advanced Options ...............................................................56VCCO in the Bottom Side Connectors ..........................56GCLK_IN parallel termination .................................57

    Design Considerations ........................................................58Part Reference .....................................................................59Pin Tables .............................................................................60

    HapsTrak II Connectors 1-3....................................60HapsTrak II Connectors 4-6....................................61HapsTrak II Connector 7 ........................................62Inter-FPGA Connections A-B (fast) .......................63Inter-FPGA Connections A-B (slow) ......................63Inter-FPGA Connections D-C (fast) .......................64Inter-FPGA Connections D-C (slow) .....................64Inter-FPGA Connections A-D (fast) .......................65Inter-FPGA Connections B-C (fast) .......................66HapsTrak CDE In ...................................................67HapsTrak CDE Out .................................................67Global Clocks .........