Fall 2006 Lillevik 333f06-e2 1 University of Portland School of Engineering EE 333 EE 333 Exam 2 November 9, 2006 Instructions 1. Print your name, student ID, and seat in the above blanks. 2. This is a Closed Book exam. 3. Do all of the problems. They may vary in points but the total is 100. Questions are short answer and problems. 4. Do not use any additional pages of paper. If you run out of room, use the back sides. Do not remove the staple. 5. Please write clearly or print. Illegible or unreadable answers may not be graded for partial credit. Name Student ID Seat 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 10 9 10 10 10 10 0 Answers
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Fall 2006 1 EE 333 Lillevik333f06-e2 University of Portland School of Engineering EE 333 Exam 2 November 9, 2006 Instructions 1.Print your name, student.
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Fall 2006
Lillevik 333f06-e2 1
University of Portland School of Engineering
EE 333
EE 333 Exam 2November 9, 2006
Instructions1. Print your name, student ID, and seat in the above
blanks.2. This is a Closed Book exam.3. Do all of the problems. They may vary in points but the
total is 100. Questions are short answer and problems.4. Do not use any additional pages of paper. If you run out
of room, use the back sides. Do not remove the staple.5. Please write clearly or print. Illegible or unreadable
answers may not be graded for partial credit.6. Mark your answer with a box or star.
Name Student ID
Seat1 10
2 10
3 10
4 10
5 10
6 10
7 10
8 10
9 10
10 10
100
Answers
Fall 2006
Lillevik 333f06-e2 2
University of Portland School of Engineering
EE 333
Problem 1 (10 pts)
Determine the control/mux signals for the branch-on-equal EX clock? Mark on the next page.
• Operation– If (A = = B), PC = ALUout
– ALUout = branch address from clock 2
• Functional units– ALU must subtract, A-B
– ALUout contains optimistic branch address
– Zero flag controls write to PC
Fall 2006
Lillevik 333f06-e2 3
University of Portland School of Engineering
EE 333
Problem 1, continued. (10 pts)
Clock 3
Optimistic branch address
01 or sub
Fall 2006
Lillevik 333f06-e2 4
University of Portland School of Engineering
EE 333
Problem 2 (10 pts)74LS161 Data Sheet
Fall 2006
Lillevik 333f06-e2 5
University of Portland School of Engineering
EE 333
Problem 2, continued. (10 pts)
Complete the design for an 8-bit PC
Data for write
Write to PC
Increment PC
All signals asserted high
Fall 2006
Lillevik 333f06-e2 6
University of Portland School of Engineering
EE 333
Problem 3 (10 pts)
A. List ideal memory design goals.Unlimited size, infinite bandwidth
B. What is a memory hierarchy?Multiple levels of memory with different speeds
and sizes
C. How does a hierarchy approximate the goals?
Principal of locality
Fall 2006
Lillevik 333f06-e2 7
University of Portland School of Engineering
EE 333
Problem 4 (10 pts)
Design a 12K x 8 ROM memory using only the ROM and 138 devices, fully decode the address, and start memory at address zero.
Fall 2006
Lillevik 333f06-e2 8
University of Portland School of Engineering
EE 333
Problem 5 (10 pts)
Consider the 16 x 8 RAM design below.
Fall 2006
Lillevik 333f06-e2 9
University of Portland School of Engineering
EE 333
Problem 5, continued. (10 pts)
A. At what time(s) are data written, what are the data and address?
(125, FF, 0) (225, AA, 1) (325, 55, 2)
B. At what time(s) are data read, what are the data and address?
(400, FF, 0) (500, AA, 1) (600, 55, 2)
Fall 2006
Lillevik 333f06-e2 10
University of Portland School of Engineering
EE 333
Problem 6 (10 pts) Determine the length and width of the memory components required for the system memory in the table below (note: G=1024M, M=1024K)?
Memory Component Length Width16K x 16 2K x 4 8 4
256K x 32 16K x 1 16 32
2M x 32 256K x 4 8 8
32M x 64 1M x 8 32 8
4G x 64 512M x 8 8 8
Fall 2006
Lillevik 333f06-e2 11
University of Portland School of Engineering
EE 333
Problem 7 (10 pts)
Cache memory
index V M tag data
000 Y Y 10 0x123
001 N Y 11 0x456
010 N N 01 0x789
011 Y Y 00 0xabc
100 Y N 01 0xdef
101 Y Y 11 0x123
110 Y Y 10 0x456
111 N Y 00 0x789
For the direct mapped, write-back cache below, complete the table (Y or N)?
CPU write
adr hit? WB?
1 0001 N N, invalid
1 1101 Y N
0 0011 Y N
0 0010 N N
1 0000 Y N
0 1110 N Y
0 0000 N Y
0 1111 N N, invalid
WB = miss-modified
Fall 2006
Lillevik 333f06-e2 12
University of Portland School of Engineering
EE 333
Problem 8 (10 pts)
A. Draw the block diagram of a controller.
B. Explain how it works.The IR and present state dictate the next state,
each present state asserts control points (MUXes, read/writes, etc.)
Present
State
NS
Decoder
Output
DecoderIR Control points
Fall 2006
Lillevik 333f06-e2 13
University of Portland School of Engineering
EE 333
Problem 9 (10 pts)Below is the MDP16 register array and timing diagram
Fall 2006
Lillevik 333f06-e2 14
University of Portland School of Engineering
EE 333
Problem 9, continued. (10 pts)
A. At what time(s) are data written to the array, with what data, which register?