Top Banner

of 28

ES Chapter11

Jun 02, 2018

ReportDownload

Documents

anses1000

  • 8/10/2019 ES Chapter11

    1/28

    The PIC uCs

    PIC Microcontroller andEmbedded Systems

    Muhammad Ali Mazidi, Rolin McKinlay and Danny Causey

    11-1

  • 8/10/2019 ES Chapter11

    2/28

    The PIC uCs

    Chapter 11 Interrupts

    pro!rammin! inAssembly

    PIC Microcontrollerand Embedded SystemsMuhammad Ali Mazidi,Rolin McKinlay andDanny Causey, "ebruary#$$%&

    11-2

  • 8/10/2019 ES Chapter11

    3/28

    The PIC uCs

    'b(ecti)e

    11-3

  • 8/10/2019 ES Chapter11

    4/28

    The PIC uCs

    Introduction

    Interrupts are mechanisms *hich enableinstant response to e)ents such as countero)er+lo*, pin chan!e, data recei)ed, etc&

    In normal mode, microcontroller eecutesthe main pro!ram as lon! as there are nooccurrences that *ould cause an interrupt&

    -pon interrupt, microcontroller stops theeecution o+ main pro!ram and commencesthe special part o+ the pro!ram.ISR/ *hich*ill analyze and handle the interrupt&

    11-4

  • 8/10/2019 ES Chapter11

    5/28

    The PIC uCs

    11&1PIC10 interrupts

    PIC can ser)e multiple de)ices usin!mechanisms o+ Pollin!

    PIC continuously monitors the status o+ each de)ice Each de)ice !et the attention o+ the CP- as the same

    le)el o+ priority

    2astes u3Controllers time by pollin! de)ices that do notneed ser)ice&

    Interrupt De)ices !et the attention o+ the CP- only *hen it needs a

    ser)ice

    Can ser)ice many de)ices *ith di++erent le)el o+ priorities

    11-5

  • 8/10/2019 ES Chapter11

    6/28

    The PIC uCs

    Interrupt ser)ice routine .ISR/

    2hen an interrupt isin)o4ed the uC runs theInterrupt Ser)iceRoutine.ISR/

    Interrupt )ector tableholds the address o+ISRs Po*er3on Reset $$$$h 5i!h priority interrupt

    $$$0h 6o* priority interrupt

    $$10h

    11-6

  • 8/10/2019 ES Chapter11

    7/28The PIC uCs

    Steps in eecutin! an interrupt

    -pon acti)ation o+ interrupt themicrocontroller "inishes eecutin! the current instruction

    Pushes the PC o+ net instruction in the stac4 7umps to the interrupt )ector table to !et the

    address o+ ISR and (umps to it 8e!in eecutin! the ISR instructions to the

    last instruction o+ ISR .RE9"IE/ Eecutes RE9"IE

    Pops the PC +rom the stac4

    Starts to eecute +rom the address o+ that PC

    11-7

  • 8/10/2019 ES Chapter11

    8/28

    The PIC uCs

    Pro!ram or!anization in MP6A8

    11-8

  • 8/10/2019 ES Chapter11

    9/28

    The PIC uCs

    Sources o+ interrupts in PIC10

    Eternal hard*are interrupts Pins R8$.I:9$/,R81.I:91/,R8#.I:9#/

    P'R98 chan!e 9imers

    9imer$ , 9imer1 ,9imer#

    ADC .analo! to di!ital con)erter/

    CCP .compare capture pulse *idthmodulation, P2M/

    &&& etc

    11-9

  • 8/10/2019 ES Chapter11

    10/28

    The PIC uCs

    Enablin! and disablin! aninterrupt

    2hen the PIC is po*ered on .or resets/ All interrupts are mas4ed .disabled/

    9he de+ault ISR address is $$$0h :o interrupt priorities +or interrupts

    11-10

  • 8/10/2019 ES Chapter11

    11/28

    The PIC uCs

    Enablin! and disablin! aninterrupt In !eneral, interrupt sources ha)e three

    bits to control their operation& 9hey are Flag bit

    to indicate that an interrupt e)ent occurred Enable bit

    that allo*s pro!ram eecution to branch to the

    interrupt )ector address *hen the +la! bit isset

    Priorit bit to select hi!h priority or lo* priority

    11-11

  • 8/10/2019 ES Chapter11

    12/28

    The PIC uCs

    Steps in enablin! an interrupt

    Set the ;IE bit+rom I:9C': RE;

    Set the IE bit +or

    that interrupt I+ the interrupt is

    one o+ the

    peripheral .timers1,# , serial,etc / setPEIE bit +romI:9C': re!

    11-12

  • 8/10/2019 ES Chapter11

    13/28

    The PIC uCs

    Eample 11&1

    a/8S"I:9C':,9MR$IE

    8S"I:9C':,I:9$IE

    8S"I:9C':,;IE

    'rM'

  • 8/10/2019 ES Chapter11

    14/28

    The PIC uCs

    Pro!ram 113> Eternalhard*are interrupt

    'R; $$$$5;'9' MAI:

    'R; $$$0589"SS I:9C':,I:9$I"RE9"IE;'9' I:9$?ISR

    'R; $$1$$5MAI:

    8C" 9RIS8,%8S" 9RIS8,I:9$C6R" 9RISDSE9" 9RISC8S" I:9C':,I:9$IE

    8S" I:9C':,;IE'

  • 8/10/2019 ES Chapter11

    15/28

    The PIC uCs

    Pro!ram [email protected] ne!ati)e Ed!e3tri!!ered interrupts

    'R; $$$$5;'9' MAI:

    'R; $$$0589"SS I:9C':,I:9$I"RE9"IE;'9' I:91?ISR

    'R; $$1$$5MAI:

    8C" 9RIS8,%8S" 9RIS8,I:918S" I:9C':,I:91IE8C" I:9C':#,I:9ED;E1

    8S" I:9C':,;IE'

  • 8/10/2019 ES Chapter11

    16/28

    The PIC uCs

    Samplin! the Ed!e tri!!eredinterrupt 9he eternal

    source must beheld hi!h +or at

    least t*oinstruction cycles

    "or B9A6 1$Mhz Instruction cycle

    time is >$$ns,$&>us

    So minimum pulseduration to detected!e tri!!ered

    interrupts #instruction cycle $&0us

    11-16

  • 8/10/2019 ES Chapter11

    17/28

    The PIC uCs 11-17

  • 8/10/2019 ES Chapter11

    18/28

    The PIC uCs

    At *hat address does theCP- *a4e up *hen po*erapplied

    9he uC *a4es up at memoryaddress $$$$9he PC has the )alue $$$$'R; directi)e put theaddress o+ the +irst op codeat the memory location $$$$

    1-18

    Figure 2-11! PIC18

    Progra" #$% &'a(e

    Po*erin! -P

  • 8/10/2019 ES Chapter11

    19/28

    Intcon

    globalinterupt

    enable INT pin interrupt

    TMR0 overflow interrupt

    GP port

    change

    interrupt

    GP port

    change

    interrupt

    INT pin interrupt

    TMR0 overflow interrupt

    FLAGSNA!LS

  • 8/10/2019 ES Chapter11

    20/28

    The PIC uCs

    9imer Interrupts

    Interru't Flag )it #egister Enable

    )it

    #egister

    9imer$ 9MR$I" I:9C': 9MR$IE I:9C':9imer1 9MR1I" PIR1 9MR1IE PIE1

    9imer# 9MR#I" PIR1 9MRIE PIE1

    9imer 9MRI" PIR 9MRIE PIE#9imer Interrupt "la! 8its and Associated Re!isters

    I:9C': Re!ister *ith 9imer$ Interrupt Enable and Interrupt "la11-20

  • 8/10/2019 ES Chapter11

    21/28

    The PIC uCs

    9imer Interrupts

    11-21

  • 8/10/2019 ES Chapter11

    22/28

    The PIC uCs

    Pro!ram 1131 .p! >$/

    "RG 0000#

    G"T" MAIN

    "RG 000$#

    !TFSS INT%"N&TMR0IF

    RTFI

    G"T" T0'ISR

    "RG 00(00#

    MAIN !%F TRIS!&)

    %LRF TRIS*

    STF TRIS%

    M"+L, 0-0$

    M"+,F T0%"N

    M"+L, 0-FF

    M"+,F TMR0#

    M"+L, 0-F.

    M"+,F TMR0L!%F INT%"N&TMR0IF

    !SF T0%"N&TMR0"N

    !SF INT%"N&TMR0I

    !SF INT%"N&GI

    "+R M"+FF P"RT%&P"RT*

    !RA "+R

    T0'ISR

    "RG .00#

    M"+L, 0-FFM"+,F TMR0# M"+L,

    0-F. M"+,F TMR0L

    !TG P"RT!&) !%F

    INT%"N&TMR0IF

    RTFI

    N*

    Ti"er0 Interru't

    11-22

  • 8/10/2019 ES Chapter11

    23/28

    The PIC uCs

    Re)isit

    11-23

  • 8/10/2019 ES Chapter11

    24/28

    The PIC uCs

    Please see Pro!ram 113# .p! >#/ andPro!ram 113 .p! >/

    11-24

  • 8/10/2019 ES Chapter11

    25/28

    The PIC uCs

    Serial Communication Interrupts

    Interru't Flag )it #egister Enable )it #egister

    9BI"

    .9ransmit/

    9BI" PIR1 9BIE PIE1

    RCI".Recei)e/ RCI" PIR1 RCIE PIE1

    Serial Port Interrupt "la! 8its and Associated Re!isters

    PIE1 Re!ister 8its 5oldin! 9BIE and RCIE

    11-25

  • 8/10/2019 ES Chapter11

    26/28

    The PIC uCs

    "i!ure 1131 Serial InterruptEnable "la!s

    11-26

  • 8/10/2019 ES Chapter11

    27/28

    The PIC uCs

    Pro!ram 113 .p! >>/

    'R; $$$$5;'9' MAI:

    'R; $$$0589"SC PIR1,9BI"8RA 9B?ISRRE9"IE

    'R; $$>$5

    9B?ISRM'

  • 8/10/2019 ES Chapter11

    28/28

    The PIC uCs

    Pro!ram 113%pa!e >>%

    'R; $$$$5;'9' MAI:

    'R;$$$05

    5I?ISR 89"SC PIR1,9BI"

    8RA 9B?ISR

    89"SC PIR1,RCI"

    8RA RC?ISR

    RE9"IE

    9B?ISR M'

Welcome message from author
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.