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– The PCB is silkscreened with component identification lettering (usually white)
– The silkscreen legendis dried or cured
– Any final drilling is done of holes that are not to be plated through, any routing is done, and the laminate is cut into individual
printed circuit boards
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PCB AssemblyPCB Assembly
Assemblies should be – maintainable
– repairable
– durable; and
– easy to install
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PCB DocumentationPCB Documentation
Front Cover – Title, date, version number, customer details, project features
Schematic
ECO Sheet – Details of any circuit modifications
Bill of material – The parts list
Parts key – A glossary of the part number abbreviations, with package sizes,
lead spacing, tolerance notes and preferred types
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PCB DocumentationPCB Documentation
Front panel artwork Manufacturing notes
– Contains the notes relating to previous production runs
- for instance problems encountered, methods of testing Drilling diagram
– Showing the positioning and size of every hole on the PCB
Actual size PCB overlay – Showing the positioning and identification of the PCB components– The plan is printed actual size to allow components
to be placed against it to check for fit
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Firmware Firmware
The major steps in Firmware design are:
– Program Specification
– Program Design
– Writing code
– Program Test
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Program Specification Program Specification
The specification for the Electronic Product being designedwill usually also be the specification for the programming required
The program specification will required the writer to go into substantial detail about how the product actually operates,and how it is used
A thorough program specification leads straight in toFlow charts and timing diagrams,which are components of Program Design
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Program DesignProgram Design
The program design stage lays out the structure andalgorithms of the firmware
The structure and algorithms may be laid out as:
– flowchart
– timing diagram
– description of a protocol
– memory map; or
– equation
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Writing CodeWriting Code
If the program is well specified andthe algorithm design stage has been thorough,the actual code writing stage can become almost mechanical
By defining the software at the outset, before code is written,a much more defined, integrated, set of code can be produced
The extra space occupied by comments costs nothing,and if the comments are well laid outthere is no possibility that they can detractfrom understanding the code
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Program TestProgram Test
Divide the testing of the design into small, autonomous units
– It is easier to detect faultsbefore they are compounded by other factors
Program testing requires getting diagnostic data out of the target, for analysis
– By emulation tools,or through the hardware itself (for instance a serial port)
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Pilot RunPilot Run
To test the product further, a Pilot run normally follows the prototyping stage
Small quantity of units are field trialed in a beta test
Opportunity to assess the manufacturability of the design,
and the usability of the documentation
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ProductionProduction
Following the pilot run there will likely be changesto the firmware, and possibly the circuit design,as the unit develops into a stable, final product
This process is controlled by ECO’s and version numbers
The cost, style of design of the final production, is heavily influenced by the number of units manufactured
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ComponentsComponents
Capacitors Resistors Transistors Diodes Oscillators and Crystals AD Converters DA Converters LCD (Liquid Crystal Display) Operational Amplifier Sensors and Transducers
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Oscillators and CrystalsOscillators and Crystals
Feedback Oscillators
– Loop Gain
– How Feedback Oscillators Work?
Quartz Crystal– Crystal Parameters– Equivalent Circuit– Load Capacitance– “Series” vs. “Parallel” Crystals– Frequency Tolerance
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AD ConvertersAD Converters
Converts analog input to a digital value and outputs it as serial or parallel data
Basic attributes– number of channels for analog input
The ALU can manipulate one-bit as well as eight-bit data types– This features makes the 8051 especially well suited
for controller-type applications A total of 51 separated operations
move and manipulate three data types:– Boolean (1-bit)– Byte (8-bit)– Address (16-bit)
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Intel 8051: CPUIntel 8051: CPU
Instruction types:– Arithmetic Operations– Logic Operations for Byte Variables– Data Transfer Instructions– Boolean Variable Manipulation– Program Branching and Machine Control
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Intel 8051: CPUIntel 8051: CPU
There are eleven addressing modes:– seven for data– four for program sequence control
Most operations allow several addressing modes,bringing total number of instructions to 111,encompassing 255 of the 256 possible 8-bit instruction opcodes
8051 instruction set fares well at bothreal-time control and data intensive algorithms
Program memory is separate distinct from data memory– Each memory type has a different addressing mechanism,
different control signals, and a different functions Architecture supports several distinct “physical” address spaces
functionally separated at the hardware level:– On - chip program memory– On - chip data memory– Off - chip program memory– Off - chip data memory– On chip special function registers
Program (Code) memory– Holds the actual 8051 program that is to be run
– Limited to 64K – may be found on-chip as ROM or EPROM– may be stored completely off-chip in
an external ROM or an external EPROM– Flash RAM is also another popular method of storing a program– Various combinations of these memory types may be used
Stack Pointer (SP)– Eight bits wide– Stack may reside anywhere
in on chip RAM
– The Stack Pointer is initialized on 0x07after a reset, and this causes stack to begin at location 0x08
Data Pointer(DPTR) – Consist high byte (DPH) and
low byte (DPL)– It may be manipulated as a
16-bit register or as two independent 8-bit registers
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Part 4Part 4
Intel 8051: SFRIntel 8051: SFR
Ports 0 to 3 (P0, P1, P2, P4)– Latches of Port 0 to 3,
respectively Serial Data Buffer (SDBF)
– It is actually two separated registers: receive and transmit buffer registers
– When data is moved to SBUF it goes to the transmit buffer
– When data is moved from SBUF it comes from the receive buffer
Timer Registers (T1, T0)– (TH1, TL1) (TH0, TL0)
Counting Registers for Timer/Counter 1 and 0
Control Registers– IP: Interrupt priority – IE: Interrupt enable – TMOD Timer/Counter mode– TCON Timer/Counter control– PCON Power control
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Intel 8051: PSWIntel 8051: PSW
Auxiliary Carry flag is used for BCD operations Flag 0 is available to user for general purposes The contest of (RS1, RS2) enable working register banks as follows:
00 - Bank 0 [0x00-0x07], 01 - Bank 1 [0x08-0x0f],10 - Bank 2 [ 0x10-0x17], 11 - Bank 3 [0x18-0x1F]
CY AC F0 RS1 RS0 OV - P
7 6 5 4 3 2 1 0
PSW
Carry flag
Auxiliary Carry flag
Flag 0
Registar BankSelect bit 1
Registar BankSelect bit 1
Overflow flag
Parity flag
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Intel 8051: CPU TimingIntel 8051: CPU Timing
The internal clock generator defines the sequence of states that make up a machine cycle
A machine cycle consists of 6 states, numbered S1 through S6 Each state time lasts for two oscillator periods Each state is then divided into a Phase 1 and Phase 2 half
Intel 8051: Port StructuresIntel 8051: Port Structures
Pseudo bi-directional I/O port structure
– On Port0 R2 is disabledexcept during bus operations(open-collector output)
The address latch bit is updated by direct addressing instructions
The value read is “OR-tied” function of Q1 and the external device
To use a pin for input latch must be set
D
Q
QSET
CLR
ENB
ENB
R1 R2
I/OPIN
+5V +5VREAD/MODIFY/WRITE
READ
INPUTBUFFER
Q2
Q1
BUS CYCLETIMING
WRITE PULSE
INTERNAL BUS
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Intel 8051: Port InterfacingIntel 8051: Port Interfacing
The output buffers of Ports 0, 1, 2 and 3can each drive 4 LS TTL inputs
Can be driven by open-collector and open-drain outputs– 0-to-1 transitions will not be fast since
there is little current pulling the pin up Port 0 output buffers can each drive 8 LS TTL inputs
(external bus mode) As port pins PORT 0 requires external pull-ups
to be able to drive any inputs bit
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Intel 8051: Intel 8051: Special Peripheral FunctionsSpecial Peripheral Functions
There are few special needscommon among control-oriented computer systems:
– keeping tracks of elapsed time– maintaining a count of signal transitions– measuring the precise width of input pulses– communicating with other systems
Two 16-bit Timer/Counter registers Timer: Register is incremented every machine cycle
(1 machine cycle = 12 oscillator periods) Counter: Register is incremented in response to
1-to-0 transition at its corresponding external input pin (T0, T1)– External input is sampled at S5P2 of every machine cycle– When the samples show high in one cycle and low in the next,
the count is incremented– The new count value is appears in S3P1
of the following detection cycle – Max count rate is 1/24 of oscillator frequency
TMOD - Timer/Counter mode register TCON - Timer/Counter control register
Intel 8051: Serial Port InterfaceIntel 8051: Serial Port Interface
Full-duplex Serial port receive and transmit registers
are both accessed at Special Function Register SBUF– Writing to SBUF loads the transmit register– Reading from SBUF accesses a physically separated receive register
Four modes of operation– In all four modes transmission is initiated by
any instruction that uses SBUF as destination register– Reception is initiated in Mode 0 by condition RI=0 and REN=1
In other modes by the incoming start bit if REN=1 SCON - Serial Port Control Register
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Intel 8051: Serial Port InterfaceIntel 8051: Serial Port Interface
SM0 SM1:– 00: Mode 0, Shift register, fosc//12
– 01: Mode 1, 8-bit UART, variable
– 10: Mode 2, 9-bit UART, fosc//32 or fosc//64
– 11: Mode 3, 9-bit UART, variable SM2: Enables multiprocessor features in Mode 2 and Mode 3
– When the stop bit is received,the interrupt will be activated only if RB8=1 (9th bit =1)
REN: Enables serial reception– Set/Clear by software
Part 2Part 2
7 6 5 4 3 2 1 0SCON SM0 SM1 SM0 REN TB8 RB8 TI RI
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Intel 8051: Serial Port InterfaceIntel 8051: Serial Port Interface
TB8: 9th data bit that will be transmitted in Mode2 and Mode3– Set/Clear by software
RB8: 9th data bit that was received in Mode2 and Mode3In Mode 1, if SM2=0, is the stop bit that was received
TI: Transmit interrupt flag– Set by hardware. Must be cleared by software
RI: Receive interrupt flag– Set by hardware. Must be cleared by software
Part 3Part 3
7 6 5 4 3 2 1 0SCON SM0 SM1 SM0 REN TB8 RB8 TI RI
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Intel 8051: Serial Port InterfaceIntel 8051: Serial Port Interface
MODE 0:– Serial data enters and exits through RXD– TXD outputs shift clock– 8 bits are transmitted/received: 8 data bits (LSB first)– The baud rate is fixed at 1/12 oscillator frequency
MODE 1:– Serial data enters through RXD, exits through TXD– 10 bits are transmitted/received:
start bit(0), 8 data bits (LSB first), stop bit(1)– On receive the stop bit goes into RB8 in SCON register– The baud rate is variable
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Intel 8051: Serial Port InterfaceIntel 8051: Serial Port Interface
MODE 2:– Serial data enters through RXD, exits through TXD– 11 bits are transmitted/received:
start bit(0), 8 data bits (LSB first), a programmable 9th bit, stop bit(1)– On transmit, the 9th bit is TB8 in SCON register– On receive, the 9th bit goes into RB8 in SCON register– The baud rate is programmable to either
1/32 or 1/64 the oscillator frequency MODE 3:
– Same as MODE 2 in all respects except baud rate– The baud rate is variable
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Intel 8051: Serial Port InterfaceIntel 8051: Serial Port Interface
Supports in-system and in-board code changes Electrically erasable Reduces code inventory and scrap Simplifies the task of upgrading code and
reduces upgrade cycle time Provides just-in-time system software downloads Truly non-volatile
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Intel 8051: Intel 8051: The On-Chip OscillatorThe On-Chip Oscillator
Intel 8051 microcontrollers have an on-chip oscillator
resonators are connected between XTAL1 and XTAL2 pins
external oscillators (HMOS or CMOS)
8051
XTAL2
XTAL1
VSS
C1
C2
QUARTZ CRYSTAL ORCERAM IC RESONATOR
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Intel 8051: Power ManagementIntel 8051: Power Management
Low power devices Power saving Voltage monitoring
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Intel 8051: Intel 8051: Power Reduction ModesPower Reduction Modes
CHMOS versions provides power reduced modes of operations There are two power reducing modes Idle and Power Down In the Idle mode oscillator continues to ran
Interrupt, Timer and Serial Port blocks continue to be clockedclock signal is gated off to the CPU
In the Power Down mode the oscillator is frozen
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Intel 8051: Instruction Set Intel 8051: Instruction Set
Intel 8051: Instruction Set Intel 8051: Instruction Set
Logical OperationsAND AndORL OrXRL Exclusive-OrCLR A Clear (Accumulator)CPL A ComplementRL A Rotate LeftRLC A Rotate Left through Carry FlagRR A Rotate RightRLC A Rotate Right through Carry FlagSWAP A Swap nibbles within Accumulator
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Intel 8051: Instruction Set Intel 8051: Instruction Set
Data TransferMOV MoveMOVC Move Code byteMOVX Move External RAM byte/wordPUSH Push direct byte on stackPOP Pop direct byte from stackXCH ExchangeXCHD Exchange low order Digit
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Intel 8051: Instruction Set Intel 8051: Instruction Set
Boolean Variable ManipulationCLR Clear bit/flagSET Set bit/flagCPL Complement bit/flagANL AND bit and flagORL OR bit and flagMOV Move bit
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Intel 8051: Instruction Set Intel 8051: Instruction Set
Program and Machine Control #1ACALL Absolute Subroutine CallLCALL Long Subroutine CallRET Return from SubroutineRETI Return from interruptAJMP Absolute JumpLJMP Long JumpSJMP Short (Relative) JumpJMP @A+DPTR Jump indirect relative to the DPTR
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Intel 8051: Instruction Set Intel 8051: Instruction Set
Program and Machine Control #2JZ Jump if Accumulator is ZeroJNZ Jump if Accumulator is Not ZeroJC Jump if Carry flag is setJNC Jump if No Carry flagJB Jump if Bit setJNB Jump if Bit Not setJBC Jump if Bit set & Clear bitCJNE Compare and Jump if Not ZeroDJNZ Decrement and Jump if Not ZeroNOP No Operation
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Intel 8051: Instruction Set Intel 8051: Instruction Set
Instructions that affect Flag Settings #1C OV AC
ADD X X XADDC X X XSUBB X X XMUL 0 XDIV 0 XDA XRRC XRLC X
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Intel 8051: Instruction Set Intel 8051: Instruction Set
Instructions that affect Flag Settings #2C OV AC
SET C 1CLR C 0CPL C XANL XORL XMOV C, bit XCJNE XOperations on PSW X X X
Intel 8051: Keil C Compiler Intel 8051: Keil C Compiler
Keil Compiler C51 includes extensions (for ANSI C) for:– Memory Types and areas on the 8051– Memory Models– Memory Type Specifiers– Variable Data Type Specifiers– Bit variables and bit-addressable data– Special Function Registers– Pointers– Function Attributes
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Intel 8051: Keil C Compiler Intel 8051: Keil C Compiler
Program Memory– code specifier refers to to the 64Kbyte code memory
Program Memory is read only; it cannot be written to It can reside within 8051 CPU, it may be external, or both Program code, including all functions and library routines are
stored in program memory
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Intel 8051: Keil C Compiler Intel 8051: Keil C Compiler
Data Memory– Up to 256 bytes of internal data memory are available
depending upon the 8051 derivate
– data refers to the first 128 bytes of internal memorychar data var1;
– idata refers to all 256 bytes of internal data memorygenerated by indirect addressingfloat idata x,y,z;
– bdata refers to 16 bytes of bit-addressable memoryin the internal data memory (20h to 2Fh)char bdata flags;
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Intel 8051: Keil C Compiler Intel 8051: Keil C Compiler
External Data Memory– xdata specifier refers to any location
in the 64KByte address space of external data memoryunsigned long xdata array[100];
– pdata specifier refers to only 1 page of 256 bytesof external data memoryunsigned char xdata vector[10][4][4];
Part 4Part 4
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Intel 8051: Keil C Compiler Intel 8051: Keil C Compiler
Special Function Register Memory– SFRs are declared in the same fashion as other C variables
– sfr (rather then char or int)sfr P0 = 0x80; /*Port0, address 80h*/
Intel 8051: Keil C Compiler Intel 8051: Keil C Compiler
Memory Models– SmallModel -
all variables, by default, reside in the internal data memory• All objects, as well as stack must fit into internal RAM
– Compact Model -all variables, by default, reside in one page of external data memory
• Can accommodate a maximum of 256 variables• Slower then small model
– Large Model - all variables, by default, reside in external data memory
• The Data Pointer (DPTR) is used for addressing• Memory access is inefficient• Generates more code then small and compact model
Part 7Part 7
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Intel 8051: Keil C Compiler Intel 8051: Keil C Compiler
Memory-specific Pointers– Include a memory type specification in the pointer declaration– May be used to access variables in the declared memory area only
char data *str;int xdata *numtab;long code *powtab;
Part 8Part 8
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Intel 8051: Keil C Compiler Intel 8051: Keil C Compiler
Function Declarations Extensions allow to:– Specify a function as an interrupt procedure– Choose register bank used– Select the memory model
• small, compact, large - memory model• reentrant - recursive function• interrupt - interrupt function• using - specify register bank
Part 9Part 9
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Intel 8051: Keil C Compiler Intel 8051: Keil C Compiler
Function Parameters and the Stack– The stack pointer on the 8051 access internal data memory only– C51 locates the stack area immediately following
all variables in the internal data memory– The stack pointer access internal data memory inirectly– C51 assigns a fixed memory location for each function parameter– Only return address is stored on the stack– Interrupts fuctions switch register banks and
save the values of few registers on the stack– By default, the C51 compiler passes up to three arguments in registers
Part 10Part 10
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Intel 8051: Keil C Compiler Intel 8051: Keil C Compiler
Passing Parameters in Registers
Part 11Part 11
ArgumentNumber
char1 byte ptr
int2 bytes ptr
longfloat
generic ptr
1 R7 R6&R7 R4-R7 R1-R3
2 R5 R4&R5 R4-R7 R1-R3
3 R3 R2&R3
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Intel 8051: Keil C Compiler Intel 8051: Keil C Compiler
Function Return Values
Part 12Part 12
Return Type Register Description
bit Carry Flag
char R7
int R6&R7 MSB in R6, LSB in R7
long R4-R7 MSB in R4, LSB in R7
float R4-R7 32-bit IEEE format
generic ptr R1-R3Memory type in R3, MSB R2, LSB R1
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Intel 8051: Keil C Compiler Intel 8051: Keil C Compiler
Specifying the Memory Model for a Function#pragma small /*default small model */
extern int calc (char i, int b) large reentrant;extern int func (char i, float f) large;extern void *tcp (char xdata *xp, int ndx) small;
int mtest (int i, int y){ /*small model*/return (i*y + y*i + func(-1, 4.75);}
int large_func (int i, int k) large { /*large model*/return (mtest(i,k) * 2)}
Part 13Part 13
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Intel 8051: Keil C Compiler Intel 8051: Keil C Compiler
Specifying the RegisterBank for a Functionvoid rb_function (void ) using 3 { ... }
– The using attribute affects object code as follows:• The currently selected register bank is saved on stack• The specified register bank is set • The former register bank is restored before the function is exited
– Register banks are useful when processing interrupts orwhen using a real-time operating system
– The using attribute may not be used infunctions that returns a value in registers
Part 14Part 14
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Intel 8051: Keil C Compiler Intel 8051: Keil C Compiler
Register Bank Access The REGISTERBANK control directive allows you to specify which
default register bank to use Upon reset, 8051 loads the PSW with 00h, which selects register
bank 0. To change this, you sholud:– Modify the startup code to select a different bank– Specify the REGISTERBANK control directive along with the new
register bank number By default, C51 generates code that accesses the registers R0-R7
using absolute addresses To make a function insensitive to the current bank, it must be
compiled using the NOAREGS control directive
Part 15Part 15
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Intel 8051: Keil C Compiler Intel 8051: Keil C Compiler
Interrupt Functions void timer0 (void) interrupt 1 using 2 {
if (++interruptcnt == 4000){second++;Interruptcnt=0; }
}– The interrupt attribute takes an argument
an integer constant in the 0 to 31 value range– The interrupt attribute affects object code as follows:
• The contains of SFR ACC, B, DPH, DPL and PSW,when required, are saved on stack
• All working registers are stored on stack if a register bank is not specified
• SFRs and working registers are restored before exiting function• The function is terminated by 8051 RETI instruction
Part 16Part 16
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Intel 8051: Keil C Compiler Intel 8051: Keil C Compiler
Reentrant Function can be shared by several processes at the same time.
When a reentrant function is executing, another process can interrupt it and then begin to execute that same function. The reentrant functions may be called recursively:
int calc (char i, int b) reentrant {
int x;
x=table[i];
return (x*b);
} Reentrant functions can be called simultaneously by two or more
processes. Reentrant functions are often required in real-time applications or
when interrupt and non-interrupt code must share a function.
Part 17Part 17
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Intel 8051: Keil C Compiler Intel 8051: Keil C Compiler
Functions may be selectively defined as reentrant, using the reentrant attribute.
For each reentrant function, a reentrant stack area is simulated in internal or external memory.
The following rules apply to reentrant functions:– bit type arguments or local variables may not be used– must not be called from alien functions or using alien attribute– may have other attributes like using or interrupt– return addresses are stored in the 8051 hardware stack– functions using different memory models may be intermixed– each of three reentrant models (small, compact and large) contains its
own reentrant stack and SP
Part 18Part 18
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Intel 8051: Keil C Compiler Intel 8051: Keil C Compiler
Control directives are used to control the operation of the compiler and can be specified after the filename on the command line or within a source file using the #pragma directive:
C51 testfile.c SYMBOLS CODE DEBUG
or
#pragma SYMBOLS CODE DEBUG
Directive categories:– source controls define macros on the command line and determine the
name of the file to be compiled)– object controls affect the form and content of the generated object
module; allow you to specify the optimizing level or include debugging information in the object file
– listing controls govern various aspects of the listing file (format and specific content)
Part 19Part 19
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Intel 8051: Keil C Compiler Intel 8051: Keil C Compiler
The C51 is an optimizing compiler. The C51 provides six different levels of optimizing:
– constant folding, simple access optimizing, jump optimizing– dead code elimination, jump negation– data overlaying– peephole optimizing– register variables, extended access optimizing, local common
subexpression elimination, case/switch optimizing– global common subexpression elimination, simple loop optimizing– loop rotation
Part 20Part 20
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Intel 8051: Keil C Compiler Intel 8051: Keil C Compiler
General optimizations:– constant folding: several constant values occurring in an expression
or address calculation are combined as a constant– jump optimizing: jumps are inverted or extended to the final target
addresses when the program efficiency is thereby increased– dead code elimination: code which cannot be reached is removed– register variables: automatic variables and function arguments are
located in registers when possible– parameter passing via registers: a maximum of three function
arguments can be passed in registers– global common subexpression elimination: identical subexpressions
or address calculations that occur multiple times in a function are calculated only once
Part 21Part 21
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Intel 8051: Keil C Compiler Intel 8051: Keil C Compiler
8051 - specific optimizations– peephole optimization: complex operations are replaced by simplified
operations when memory space or execution time can be saved as a result
– extended access optimizing: constants and variables are included directly in operations
– data overlaying: data and bit segments of functions are overlaid with other data and bit segments by the linker/locator
– case/switch optimization: any switch and case statements are optimized by using a jump table or string of jumps
Part 22Part 22
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Intel 8051: Keil C Compiler Intel 8051: Keil C Compiler
Options for code generation:– OPTIMIZE(SIZE): common C operations are replaced by subprograms,
thereby reducing the program code– NOAREGS: C51 no longer uses absolute register access; program
code is independent of the register bank– NOREGPARAMS: parameter passing is always performed in local data
segments
Part 23Part 23
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Intel 8051: Keil C Compiler Intel 8051: Keil C Compiler
You can easily interface C51 to routines written in 8051 assembler For an assembly routine to be called form C, it must be aware of
the parameter passing and return value conventions used in C
Function parameters By default C functions pass up to three parameters in registers.
The remaining parameters are passed in fixed memory locations. Functions that pass parameters in registers are prefixed with the
underscore character (_functionName)
Part 24Part 24
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Intel 8051: Keil C Compiler Intel 8051: Keil C Compiler
Intel 8051: Additional FeaturesIntel 8051: Additional Features
Watch Dog Timers Clock Monitor Resident Program Loader Software protection P Supervisory Circuit
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Watch Dog TimersWatch Dog Timers
Provides a means of graceful recovery from a system problem If the program fails to reset the watchdog at some predetermined
interval, a hardware reset will be initiated Especially useful for unattended systems
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Clock MonitorClock Monitor
If the input clock is too slow, a clock monitor can shut the microcontroller down
Usually software controlled status (on/off)
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Resident Program LoaderResident Program Loader
Loads a program by initializing program/data memory from either a serial or parallel port
Eliminates the erase/burn/program cycle (typical with EPROM’s) Allows system updating from an offsite location
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Software protectionSoftware protection
Protect unauthorized snooping (reverse engineering, modifications, piracy, etc.
Only OTPs and Windowed devices option
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P Supervisory CircuitP Supervisory Circuit
Functions: P reset (active low or high)– Manual reset input– Two stage power fall warning– Backup-battery switchover– Write protection of RAM– 2.275 threshold detector– Battery OK flag indicator– Watch Dog timer
Intel 8051-Design ExampleIntel 8051-Design Example
The complete design project using the 8051 microcontroller will be presented here. All design phases mentioned earlier will be shown:
– specification
– circuit diagram
– pcb layout
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SpecificationSpecification
The idea is to design a small, simple PCB for test purposes. The device will have:
– 8 driver outputs (ie. LEDs, relays)
– a speaker output
– a light sensor input
– 3 extra inputs
– optional serial port
The device will be based on Atmel AT89C2051microprocessor, a 20
pin 8051 variant with FLASH program memory.
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Circuit DiagramCircuit Diagram
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Circuit DescriptionCircuit Description The battery power supply is connected on terminals T1 &T2. While the circuit diagram specifies 3v/4.5v battery, the part ULN2803 needs 4.5v-5v
battery to get proper operation.
Switch SW2 allows the PCB to be turned on and off.
Capacitor C1 provides a reset signal to the microprocessor. XTAL1 provides the oscillator timing component for the microprocessor. It is important to use a crystal for XTAL1, not a ceramic resonator -
prototype testing shows that a ceramic resonator gives problems unless capacitors to ground are placed on X1 & X2.
Diode D1 provides some protection for the microprocessor in case of transients or misconnection of the battery
Optodarlington TR1 is the light sensor
Pot VR1, as labelled, adjusts the sensitivity of the light sensor Resistor R9 provides current limiting when full illumination is on TR1 at max sensitivity
The symbol PCB LAM#1 is a record of the PCB laminate ID number, and ensures the PCB laminate appears in the parts list
The symbol SKT1 is a record of the need for a socket for IC1, and ensures that the socket appears in the parts list
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Circuit DescriptionCircuit Description
TR2 is a switch used to sense illumination (On=TR1 illuminated)
Pin 6 of the micro is the LiteOn input (Low=TR1 illuminated)
SW1 is in parallel with the LiteOn input - pushing SW1 is like illuminating TR1
Resistors R12 & R13 pull up the open collector outputs P1.0 and P1.1 of IC1
IC2 is the driver IC, with several hundred milliamps drive capability on each output
R1-R8 limit the current that can be taken from each output of IC2, and are most useful when LEDs are connected directly to pins L1-L8. If other
devices are used, such as relays, the values may of R1-R8 may have to be changed, or replaced with links.
R10 limits the current from IC1 into the base of TR3 TR3 is a switch transistor that drives the sounder output (P3.7 Low=Sounder driven high)
R11 provides the class A load resistor for the sounder output
C2 Capacitively couples the speaker to TR3 and R11.
C3 provides some supply decoupling.
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PCB DiagramPCB Diagram
Central to the board are the two IC's: The AT89C2051 (in an IC socket) and ULN2803 driver. The bank of resistors to the right of the ULN2803 are primarily for limiting the current through LEDs, when they are being driven direct from the outputs. You may wish to use another value instead of the 27 ohm shown on the circuit. The circuitry to the left of the CPU is primarily for the light sensor - this is just a simple darlington phototransistor, sensitivity pot and switch
transistor.
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PCB Artwork, overlayPCB Artwork, overlay
The overlay diagram is used for the silkscreen (legend) of the
circuit board.
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PCB Artwork, top layerPCB Artwork, top layer
The top layer diagram is used for the tracks that go on the component side of the circuit
The bottom layer diagram is used for the tracks that go on the solder side of the circuit board. The layer is printed as if you are viewing through the circuit board (this is a convention used so that the layers line up) and will have to be reversed left-for-right before the copper tracks are
AT89C2051 - Atmel microprocessor, see Atmel site for data and a programmer
ULN2803A - Manufacturer: Allegro (formerly known as Sprague)
27E - Resistor, value 27 ohm - substitute if required for different outputs
MEL12 - Phototransistor - many substitutes will work, but darlington types offer the best sensitivity. We have used BP103B
(Farnell 212-763 in Australia). Flat goes toward TR2 for two leaded devices. 3.57945Mhz - Frequency depends on application program. Use a crystal, rather than a ceramic resonator (otherwise fit extra
capacitors to gnd on X1 and X2).
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Using the DeviceUsing the Device
The diagram on the left shows a typical circuit using the HSETI PCB, with the optional serial port in place also. The serial port does not have strict RS232 level signals, but will work with just about all PC clones with reasonable