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    EC2155 CIRCUITS AND DEVICES LABORATORY

    1. Verification of KVL and KCL

    2. Verification of Thevenin and Norton Theorems.

    3. Verification of superposition Theorem.

    4. Verification of Maximum power transfer and reciprocity theorems.

    5. Frequency response of series and parallel resonance circuits.

    6. Characteristics of PN and Zener diode

    7. Characteristics of CE configuration

    8. Characteristics of CB configuration

    9. Characteristics of UJT and SCR

    10. Characteristics of JFET and MOSFET

    11. Characteristics of Diac and Triac.

    12. Characteristics of Photodiode and Phototransistor.

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    1.(a).VERIFICATION OF KIRCHOFFS CURRENT LAW

    CIRCUIT DIAGRAM:

    TABULATION:

    Sl.No. Value of the

    resistance

    Practical CurrentValue (mA)

    TheoreticalCurrent Value

    (mA)

    2

    R3 10 V

    `R1 R2

    R4

    12 V

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    EX.NO.: 1. VERIFICATION OF KVL AND KCL

    1. (a) VERIFICATION OF KIRCHOFFS CURRENT LAW

    AIM :

    To verify Kirchoffs Current Law experimentally for the given network.

    APPARATUS REQUIRED:

    Sl.No.

    Description of the Item Type Range Quantity

    1 Variable DC RegulatedPower Supply

    (0 30) V, 2 A 1

    2 Ammeter MC (0 10) mA 23 Ammeter MC (0 15) mA 14 Fixed Resistors 820,680,560,100 1 each5 Multimeter Digital 16 Bred Board 17 Connecting Wires Hook

    up

    THEORY :

    Statement of Kirchoffs Current Law :

    In any electrical network, the algebric sum of the currents meeting at ajunction is zero.The sum of the currents entering a junction is equal to the sum ofthe currents leaving away from the junction.

    Consider the case of a few conductors meeting at a point O. Some

    conductors have currents leading away from point O.

    If I1 and I4 are the incoming currents (currents entering the junction O) andI2, I3 and I5 are the currents leaving the junction O, then

    Sum of Incoming currents = Sum of outgoing currents

    I1 + I4 = I2 + I3 + I5 (or) I = 0PROCEDURE :

    1. The connections are made as per the circuit diagram.

    2. Both the DC RPS are switched on.3. The DC RPS1 is varied to a voltage of 15 V. This corresponds tosource voltage V1.

    4. The DC RPS2 is varied to a voltage of 12V. This corresponds tosource voltage V2.

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    CALCULATION:

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    5. The current readings I1, I2and I3 shown by the ammeters A1, A2and A3are observed and noted down.

    6. Both the DC RPS are then switched off.7. Kirchoffs Current Law is verified using the relation I3 = I1 + I2.

    RESULT :

    Thus, Kirchoffs Current Law has been verified experimentally for thegiven network.

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    CIRCUIT DIAGRAM FOR KIRCHOFFS VOLTAGE LAW:

    TABULATION:

    Sl.No. Value of the

    resistance

    Practical CurrentValue (mA)

    TheoreticalCurrent Value

    (mA)

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    1. (b). VERIFICATION OF KIRCHOFFS VOLTAGE LAW

    AIM :To verify Kirchoffs Voltage Law experimentally for the given network.

    APPARATUS REQUIRED:

    Sl.No. Description of the Item Type Range Quantity1 Variable DC Regulated

    Power Supply(0 30) V, 2 A 1

    2 Voltmeter MC (0 30) V 33 Fixed Resistors 820,680,560,100 1 each4 Multimeter Digita

    l1

    5 Bred Board 16 Connecting Wires Hook up

    THEORY :

    Statement of Kirchoffs Voltage Law :

    The algebric sum of the products of currents and resistances in each ofthe conductors in any closed path (or mesh) in a network plus the algebric sum ofthe emfs in that path is zero.

    IR + Emf = 0

    PROCEDURE :

    1. The connections are made as per the circuit diagram.2. Both the DC RPS are switched on.3. The DC RPS1 is varied to a voltage of 10 V. This corresponds to

    source voltage V1.4. The DC RPS2 is varied to a voltage of 8 V. This corresponds to source

    voltage V2.5. The voltage drops and voltage rises across various elements for each

    closed loop is measured.6. Kirchoffs Voltage Law is then verified for each closed loop wherein the

    sum of the voltage drops and voltage rises is zeo.

    7. Both the DC RPS are then switched off.

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    CALCULATION :

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    RESULT :

    Thus, Kirchoffs Voltage Law has been verified experimentally.

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    CIRCUIT DIAGRAM FOR THEVENIN THEOREMS:

    1. To Find VTH

    2. To Find RTH

    3. To Find Load Current

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    EXP.NO :

    2. VERIFICATION OF THEVENIN AND NORTON THEOREMS.

    2.a.VERIFICATION OF THEVENINS THEOREM

    AIM :

    To verify Thevenins Theorem for the given network.

    APPARATUS REQUIRED:

    Sl.No. Description of the Item Type Range Quantity

    1 Variable DC Regulated PowerSupply

    Dual (0 30) V, 2 A 1

    2 Ammeter MC (0 10) mA 13 Fixed Resistors 2 each

    4 Fixed Resistors 15 Multimeter Digital 16 Voltmeter MC (0 10) V 17 Decade Resistance Box 18 Connecting Wires

    THEORY:

    Statement of Thevenins Theorem:

    Any linear, bilateral, active electric network with output terminals AB canbe replaced by a simple equivalent circuit with a single voltage source Vo inseries with a resistance Rth about the terminals AB.

    V0 = Open Circuit VoltageRth = Thevenins Resistance

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    TABULATION:

    Sl.No. Parameter

    TheoreticalValue

    PracticalValue

    CALCULATE RTH:

    CALCULATE VTH:

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    PROCEDURE:I To find Open Circuit Voltage V0

    1. The connections are made as per the circuit diagram.

    2. The load resistance RL = 2.2 k is removed and an open circuit is

    created across the terminals AB.

    3. The DC RPS is switched on.4. The DC RPS is varied and set to a voltage of 25 V.

    5. The open circuit voltage V0 about the terminals AB is measured

    from the voltmeter reading.

    6. The DC RPS is then switched off.

    II To find Thevenins Resistance Rth1. The connections are made as per the circuit diagram.

    2. The Thevenins resistance Rth about the terminals AB is measured

    using the multimeter.III To find the Current IL through Load Resistor RL = 2.2 k from

    Thevenins Equivalent Circuit

    1. The connections are made as per the Thevenins EquivalentCircuit.

    2. The DC RPS is switched on.3. The DC RPS is varied and set to a voltage corresponding to Open

    Circuit Voltage V0.4. The DRB is adjusted to a resistance value corresponding to

    Thevenins resistance Rth.5. The current IL through Load Resistor RL = 2.2 k is measured

    using the ammeter.

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    Thevinin Equivalent Circuit:Calculate Load Current

    RESULT:Hence, Thevenins Theorem is verified for the given network.

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    2. b. VERIFICATION OF NORTONS THEOREM

    AIM :To verify Nortons Theorem for the given network.

    APPARATUS REQUIRED:

    S.No. Description of the Item Type Range Quantity

    1 Variable DC Regulated PowerSupply

    Dual (0 30) V, 2 A 1

    2 Ammeter MC (0 10) mA 13 Fixed Resistors 24 Fixed Resistors 1 each

    5 Multimeter Digital 16 Decade Resistance Box 17 Connecting Wires

    THEORY:

    Statement of Nortons Theorem:

    Any linear, bilateral, active electric network with output terminals AB canbe replaced by a simple equivalent circuit with a single current source I sc inparallel with a resistance Rth about the terminals AB.

    Isc = Short Circuit CurrentRth = Thevenins Resistance

    PROCEDURE:

    I To find Short Circuit Current Isc

    1. The connections are made as per the circuit diagram.2. The load resistance RL = 2.2 K is removed and the terminals AB is

    short circuited.3. Both the DC RPS 1 and DC RPS 2 are switched on.

    The DC RPS1 is varied and set to a voltage of 10 V and the DC RPS2 is variedand set to a voltage of 5 V

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    Verification of Norton Theorems.

    CIRCUIT DIAGRAM:

    1. To Find Isc

    2. To Find Req

    3. To Find Load Current IL

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    4. The short circuit current Iscthrough the terminals AB is measured fromthe ammeter reading.

    5. The DC RPS is then switched off.

    II To find Thevenins Resistance Rth

    1. The connections are made as per the circuit diagram.2. The Thevenins resistance Rth about the terminals AB is measured

    using the multimeter

    III To find the Current IL through Load Resistor RL = 2.2K fromNortons Equivalent Circuit

    1. After obtaining the Nortons equivalent circuit, its Thevenins equivalentis obtained from it using source transformation technique.

    2. The connections are made as per the Thevenins Equivalent Circuit.3. The DC RPS is switched on.4. The DC RPS is varied and set to a voltage corresponding to Open

    Circuit Voltage V0 = Isc x Rth.5. The DRB is adjusted to a resistance value corresponding to Thevenins

    resistance Rth.6. The current IL through Load Resistor RL = 2.2K is measured using

    the ammeter.

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    TABULATION:

    Sl.No. Parameter

    TheoreticalValue

    PracticalValue

    CALCULATE RTH:

    CALCULATE IN:

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    Nortons Equivalent Circuit:Calculate Load Current

    RESULT:

    Hence, Nortons Theorem is verified for the given network.

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    VERIFICATION OF SUPERPOSITION THEOREM

    CIRCUIT DIAGRAM:1) 2)

    3)

    TABULATION:

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    EXP.NO :3.VERIFICATION OF SUPERPOSITION THEOREM

    AIM :To verify Superposition Theorem for the given network experimentally.

    APPARATUS REQUIRED:

    S.No.

    Description of the Item Type Range Quantity

    1 Variable DC Regulated PowerSupply

    Dual (0 30) V, 2 A 1

    2 Ammeter MC (0 10) mA 13 Fixed Resistors 1

    each4 Multimeter Digital 15 Bred Board 16 Connecting Wires

    THEORY:

    Statement of Superposition Theorem:

    In a linear, lumped element, bilateral, active electric network that isenergized by two or more sources, the current through (or voltage across) anyresistor is equal to the algebric sum of the currents through (or voltages across)the resistor, when each source acts separately. While one source is applied theother sources are replaced by their respective internal resistances.

    To replace the other sources by their respective internal resistances, the

    voltage sources are short circuited and the current sources are open circuited.

    PROCEDURE:

    I Both Voltage Sources V1 and V2 are active1. The connections are made as per the circuit diagram.2. Both the DC RPS are switched on.3. The first DC RPS is varied and set to a voltage of 10 V. (V1 = 10 V)4. The second DC RPS is varied and set to a voltage of 5V. (and V2 = 5

    V).

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    Voltage(v) I1

    (mA)

    I2(mA)

    I=I1+I2(mA)

    CACULATION:

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    5. The current ILthrough the load resistor RL = 2.2k is measured fromthe ammeter reading.

    6. Both the DC RPS are switched off.

    II Voltage Source V1 is alone energized and Voltage Source V2 is shortcircuited

    1. The connections are made as per the circuit diagram.2. The first DC RPS are switched on.

    3. The first DC RPS is varied and set to a voltage of 10 V. (V1 = 10 V)4. The second DC RPS is short circuited.5. The current IL1 through the load resistor RL = 2.2k is measured

    from the ammeter reading.6. The first DC RPS is switched off.

    III Voltage Source V2 is alone energized and Voltage Source V1 is shortcircuited

    1. The connections are made as per the circuit diagram.2. The second DC RPS are switched on.

    3. The second DC RPS is varied and set to a voltage of 5 V. (V 1 = 5V)

    4. The first DC RPS is short circuited.5. The current IL2 through the load resistor RL = 470 is measured

    from the ammeter reading.6. The second DC RPS is switched off.

    IV Verification of Superposition Theorem

    1. By Superposition Theorem, Current IL through the load resistor RL =

    2.2k is IL1 + IL2.

    2. The theoretical values of the current through the load resistor RL = 2.2k obtained by manual calculation for different cases (both sources

    active, V1 alone is energized and V2 alone is energized) are compared

    with the practical values.

    3. Hence, Superposition Theorem is verified.

    RESULT:Thus, Superposition Theorem has been verified for the given

    network.Theoretical value = ------------- Practical value = ----------------

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    CIRCUIT DIAGRAM:

    MODEL GRAPH:

    TABULATION:

    LoadResistance

    ()Voltage

    (v)

    Current(mA)

    Power(watts)

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    4. a. VERIFICATION OF MAXIMUM POWER TRANSFERTHEOREM

    AIM :To verify Maximum Power Transfer Theorem for the given network.

    APPARATUS REQUIRED:

    S.No.

    Description of the Item Type Range Quantity

    1 Variable DC Regulated PowerSupply

    Dual (0 30) V, 2 A 1

    2 Ammeter MC (0 10) mA 13 Voltmeter MC (0 10) V 14 Fixed Resistors 1 each

    5 Multimeter Digital 16 Decade Resistance Box 2

    Connecting Wires

    THEORY:

    Statement of Maximum Power Transfer Theorem:

    PROCEDURE:

    I To find Open Circuit Voltage V0

    1. The connections are made as per the circuit diagram.2. The load resistance RL is removed and an open circuit is created

    across the terminals AB.3. The DC RPS 1 and the DC RPS 2 are switched on.

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    Calculation:

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    4. The DC RPS 1 is varied and set to a voltage of 20 V and the DC RPS2 is varied and set to a voltage of 10 V.

    5. The open circuit voltage V0about the terminals AB is measured fromthe voltmeter reading.

    6. Both the DC RPS are then switched off.II To find Thevenins Resistance Rth

    1. The connections are made as per the circuit diagram.2. The Thevenins resistance Rth about the terminals BD is measured

    using the multimeter.III To find the Load Current IL for Maximum Power Transfer and

    Maximum Power transferred to the load PL from TheveninsEquivalent Circuit1. The connections are made as per the Thevenins Equivalent

    Circuit.2. The condition for Maximum Power Transfer is RL = Rth.3. The DC RPS is switched on.4. The DC RPS is varied and set to a voltage corresponding to Open

    Circuit Voltage V0.5. The DRB1 is adjusted to a resistance value corresponding to

    Thevenins resistance Rth.6. The DRB2 is varied and for various values of RL. The voltmeter and

    ammeter readings are recorded for various values of R L. The powertransferred to the load PL is also calculated.

    7. When the load resistance RL becomes equal to a resistance valuecorresponding to Thevenins resistance Rth (RL = Rth), then it isfound that maximum power is transferred to the load.

    8. The current IL through Load Resistor RL for Maximum PowerTransfer is measured using the ammeter and Maximum Powertransferred to the load PL is also calculated.

    IV Verification of Maximum Power Transfer Theorem

    1. The Open Circuit Voltage V0, Thevenins Resistance Rth, load current ILfor maximum power transfer and the Maximum Power transferred tothe load PL obtained from manual calculation are compared with thepractical values.

    RESULT:

    Hence, Maximum Power transferred Theorem is verified for the given

    network.Theoretical value Pmax= ------------- Practical value Pmax= ----------------

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    CIRCUIT DIAGRAM FOR RECIPROCITY THEOREM:

    Before changing the source : After Changing the source:

    TABULATION:

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    4. b. VERIFICATION OF RECIPROCITY THEOREM

    AIM :To verify Reciprocity Theorem for the given network experimentally.

    APPARATUS REQUIRED:

    Sl.No.

    Description of the Item Type Range Quantity

    1 Variable DC Regulated PowerSupply

    Dual (0 30)V, 2 A 1

    2 Ammeter MC (0 10) mA 13 Fixed Resistors 2.2 k,1k,470, 330,220,100

    1

    each4 Multimeter Digital 15 Bred Board 16 Connecting Wires

    THEORY:

    Statement of Reciprocity Theorem:

    In a linear, lumped element, bilateral, active electric network that is energised bya single source, the ratio of excitation to response is a constant even when thepositions of these two are interchanged.

    The excitation may be a voltage source or a current source and the responsemay be the current through or voltage across any branch.

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    CALCULATION:

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    PROCEDURE:

    I Before Interchanging The Positions of Excitation And Response

    2. The connections are made as per the circuit diagram.

    3. The DC RPS is switched on.

    4. The DC RPS is varied and set to a voltage of 20 V. (V = 20 V).

    5. The source in the branch cd(V = 20 V) is the excitation.

    6. The current through the branch ab is the response.

    7. The current I through the branch ab is measured using the

    ammeter.

    8. The DC RPS is switched off.

    9. The ratio of excitation to response is calculated.

    II After Interchanging The Positions of Excitation And Response1. The connections are made as per the circuit diagram.

    2. The positions of the excitation and response are now interchanged.

    3. The DC RPS is switched on.

    4. The DC RPS is varied and set to a voltage of 20 V. (V = 20 V).

    5. The source in the branch cd (V = 20 V) is the excitation.

    6. The current through the branch cdis the response.

    7. The current I through the branch cd is measured using the

    ammeter.8. The DC RPS is switched off.

    9. The ratio of excitation to response is calculated.

    RESULT:Thus, Reciprocity Theorem has been verified for the given network.

    Before interchanging the source = ----------------After interchanging the source = -----------------

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    CIRCUIT DIAGRAM FOR SERIES RESONANT CIRCUIT

    MODEL GRAPH:

    TABULATION :

    S.NO Frequencyf

    (kHz)

    Output VoltageV0(v)

    CALCULATION:

    5.FREQUENCY RESPONSE OF SERIES AND PARALLEL RESONANTCIRCUIT

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    AIM:To obtain the frequency response of series resonant and parallel resonant

    circuit.

    APPARATUS REQUIRED:

    Sl.No. Description of the Item Type Range Quantity

    1 Function Generator 12 CRO Dual 30 MHZ 13 CRO Probes 34 Resistor 560 15 Decade Inductance Box 16 Capacitor 0.1 F 17 Bred Board 18 Multimeter Digital 19 Connecting Wires

    FORMULA:

    1. Resonant Frequencyf0 = 1

    ------------- Hz2 LC

    THEORY:

    An a.c. circuit is said to be in resonance when the applied voltage and the currentare in phase. Resonant circuits are formed by combination of reactive elements(L & C) connected either in series or in parallel. The power factor of the RLCcircuit is unity at resonance and the circuit acts as a purely resistive circuit.

    At resonance, XL = XC1

    0 L = --------0C

    where, 0 = Angular frequency in rad / sec and f0 = Frequency in Hz1 1

    0 = -------------- and f0 = -------------- LC 2 LC

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    CIRCUIT DIAGRAM FOR PARALLEL RESONANT CIRCUIT

    MODEL GRAPH:

    TABULATION :

    S.NO Frequencyf

    (kHz)

    Output VoltageV0(v)

    I=V/R

    CALCULATION:

    PROCEDURE (SERIES RESONANCE):

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    1. The elements are connected as per the circuit diagram.

    2. The function generator is switched on and is set in sine wave mode.

    3. A particular frequency (say 1 kHz) is set in the function generator.

    4. The input voltage is adjusted to 1 volts peak value with the help of CRO.

    5. Starting from 1kHz, the values of output voltage are observed and

    tabulated for various frequencies above and below the resonant frequency.6. The resonance curve is drawn between Voltage and frequency.

    PROCEDURE(PARALLEL RESONANCE) :

    1. The elements are connected as per the circuit diagram.

    2. The function generator is switced on and is set in sine wave mode.

    3. A particular frequency (say 1 kHz) is set in the function generator.

    4. The input voltage is adjusted to 1 volts peak value with the help of CRO.

    5. Starting from 1kHz, the values of output voltage are observed and

    tabulated for various frequencies above and below the resonant frequency.

    6. The values of the current corresponding to various frequencies are

    calculated.

    7. The resonance curve is drawn between current and frequency.

    RESULT:

    Thus the frequency response of a series RLC circuit and a parallel RLC circuithas been obtained.

    Theoretical value P0= -------------Practical value P0= ----------------

    CIRCUIT DIAGRAM:-35

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    FORWARD BIAS:-

    REVERSE BIAS:-

    Symbol Pin diagram

    MODEL WAVEFORM:-

    6. a. P-N JUNCTION DIODE CHARACTERISTICS

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    AIM:-To observe and draw the Forward and Reverse bias V-I Characteristics of a

    P-N Junction diode.

    APPARATUS:-

    P-N Diode IN4007 -1

    Regulated Power supply (0-30v) -1Resistor 1K - 1

    Ammeters (0-200 mA, 0-500mA) -1

    Voltmeter (0-20 V) -1

    Bread board -1

    Connecting wires - few

    THEORY:-

    A p-n junction diode conducts only in one direction. The V-I

    characteristics of the diode are curve between voltage across the diode and

    current through the diode. When external voltage is zero, circuit is open and the

    potential barrier does not allow the current to flow. Therefore, the circuit current is

    zero. When P-type (Anode is connected to +ve terminal and n- type (cathode) is

    connected to ve terminal of the supply voltage, is known as forward bias. The

    potential barrier is reduced when diode is in the forward biased condition. At

    some forward voltage, the potential barrier altogether eliminated and current

    starts flowing through the diode and also in the circuit. The diode is said to be inON state. The current increases with increasing forward voltage.

    When N-type (cathode) is connected to +ve terminal and P-type

    (Anode) is connected ve terminal of the supply voltage is known as reverse

    bias and the potential barrier across the junction increases. Therefore, the

    junction resistance becomes very high and a very small current (reverse

    saturation current) flows in the circuit. The diode is said to be in OFF state. The

    reverse bias current due to minority charge carriers.

    OBSERVATION:-

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    S.NO FORWARD VOLTAGE

    (V)

    FORWARD CURRENT

    (mA)

    OBSEVATION:-

    S.NO REVERSE VOLTAGE (V) REVERSE CURRENT (mA)

    FORMULA:

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    D.C (or) Static resistance, rdc = VF/ IF (At any point in the linear region of

    forward characteristics)

    A.C (or) Dynamic resistance, rac = VR/ IR (In the linear region of reverse

    characteristics)

    PROCEDURE:-

    FORWARD BIAS:-1. Connections are made as per the circuit diagram.

    2. For forward bias, the RPS +ve is connected to the anode of the diode and

    RPS ve is connected to the cathode of the diode,

    3. Switch on the power supply and increases the input voltage (supply voltage) in

    Steps.

    4. Note down the corresponding current flowing through the diode and voltage

    across the diode for each and every step of the input voltage.

    5. The reading of voltage and current are tabulated.Graph is plotted between

    voltage and current.

    REVERSE BIAS:-

    1. Connections are made as per the circuit diagram

    2 . For reverse bias, the RPS +ve is connected to the cathode of the diode and

    RPS ve is connected to the anode of the diode.

    3. Switch on the power supply and increase the input voltage (supply voltage) in

    Steps4. Note down the corresponding current flowing through the diode voltage

    across the diode for each and every step of the input voltage.

    5. The readings of voltage and current are tabulated

    6. Graph is plotted between voltage and current.

    RESULT:- Thus the Forward and Reverse Bias characteristics for a p-n diode is

    observed.

    D.C (or) Static resistance, rdc =

    A.C (or) Dynamic resistance, rac =

    CIRCUIT DIAGRAM:-

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    FORWARD BIAS CHARACTERISTICS:-

    REVERSE BIAS CHARACTERISTICS:-

    Symbol Pin diagram

    MODEL WAVEFORMS:-

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    6 . b. ZENER DIODE CHARACTERISTICS

    AIM: To observe and draw the Forward and Reverse bias V-I Characteristics of

    a zener diode.

    APPARATUS: -

    Zener diode -1

    Regulated Power Supply (0-30v) - 1

    Voltmeter (0-20v) -1

    Ammeter (0-100mA) -1

    Resistor (1KOhm) -1

    Bread Board -1

    Connecting wires - few

    Theory:- A zener diode is heavily doped p-n junction diode, specially

    made to operate in the break down region. A p-n junction diode normally does

    not conduct when reverse biased. But if the reverse bias is increased, at a

    particular voltage it starts conducting heavily. This voltage is called Break down

    Voltage. High current through the diode can permanently damage the device

    To avoid high current, we connect a resistor in series with zenerdiode. Once the diode starts conducting it maintains almost constant voltage

    across the terminals what ever may be the current through it, i.e., it has very

    low dynamic resistance. It is used in voltage regulators.

    FORMULA:

    Dynamic Impedance, ZR = VZ/ IZ

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    OBSERVATIONS:-

    Forward bias characteristics:-

    S.NO FORWARDVOLTAGE(VZ)

    REVERSECURRENT(IZ)

    OBSEVATION:-

    S.NO REVERSE VOLTAGE (V) REVERSE CURRENT (mA)

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    PROCEDURE:-

    Forward bias characteristics:-

    1. Connections are made as per the circuit diagram.

    2. The Regulated power supply voltage is increased in steps.

    3. The zener current (lz), and the zener voltage (Vz.) are observed and then

    noted in the tabular form.4. A graph is plotted between zener current (Iz) and zener voltage (Vz).

    Reverse bias characteristics:-

    1. The voltage regulation of any device is usually expressed as percentage

    regulation

    2. The percentage regulation is given by the formula

    ((VNL-VFL)/VFL)X100

    VNL=Voltage across the diode, when no load is connected.

    VFL=Voltage across the diode, when load is connected.

    3. Connection are made as per the circuit diagram

    4. The load is placed in full load condition and the zener voltage (Vz), Zener

    current (lz), load current (IL) are measured.

    5. The above step is repeated by decreasing the value of the load in steps.

    6. All the readings are tabulated.

    7. The percentage regulation is calculated using the above formula

    RESULT:- Thus the Forward and Reverse Bias characteristics for a Zener

    diode is observed.

    Dynamic Impedance, ZR =

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    CIRCUIT DIAGRAM:

    Symbol Pin diagram

    MODEL GRAPHS:

    INPUT CHARACTERSTICS

    OUTPUT CHARECTERSTICS

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    7. Characteristics of CE configuration

    AIM: To draw the input and output characteristics of transistor connected in

    CE configuration and find out the h- parameters.

    APPARATUS:

    Transistor (BC 107) - 1

    R.P.S (O-30V) - 2

    Voltmeters (0-20V) - 2Ammeters (0-200A) - 2

    (0-500mA)

    Resistors 1Kohm - 2 Bread board - 1

    THEORY:

    A transistor is a three terminal device. The terminals are emitter,

    base, collector. In common emitter configuration, input voltage is applied

    between base and emitter terminals and out put is taken across the collector

    and emitter terminals.Therefore the emitter terminal is common to both input

    and output.

    The input characteristics resemble that of a forward biased diode

    curve. This is expected since the Base-Emitter junction of the transistor is

    forward biased. As compared to CB arrangement IB increases less rapidly with

    VBE . Therefore input resistance of CE circuit is higher than that of CB circuit.

    The output characteristics are drawn between Ic and VCE at constant IB.

    the collector current varies with VCE unto few volts only. After this the collectorcurrent becomes almost constant, and independent of VCE. The value of VCE up

    to which the collector current changes with V CE is known as Knee voltage. The

    transistor always operated in the region above Knee voltage, I C is always

    constant and is approximately equal to IB.

    The current amplification factor of CE configuration is given by = IC/IB

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    OBSERVATIONS:

    INPUT CHARACTERISTICS: OUT PUT CHAREACTARISTICS:

    S.NO

    VCE = VCE =

    VBE

    (V)IB

    (A)VBE

    (V)IB

    (A)

    S.NO

    IB = IB =

    VCE

    (V)

    IC

    (mA)

    VCE

    (V)

    IC

    mA)

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    PROCEDURE:

    INPUT CHARECTERSTICS:

    1. Connect the circuit as per the circuit diagram.2. For plotting the input characteristics the output voltage VCE is kept

    constant at 1V and for different values of VBE . Note down the values of IC

    3. Repeat the above step by keeping VCE at 2V and 4V.

    4. Tabulate all the readings.

    5. plot the graph between VBE and IB for constant VCE

    6.

    OUTPUT CHARACTERSTICS:

    1. Connect the circuit as per the circuit diagram

    2. for plotting the output characteristics the input current IB is kept

    constant at 10A and for different values of VCE note down the values of IC

    3. repeat the above step by keeping IB at 75 A 100 A4. tabulate the all the readings

    5. plot the graph between VCE and IC for constant IB

    RESULT:

    Thus the input and out put characteristics of a transistor in CE

    configuration are Drawn and its h-parameters are calculated.

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    CIRCUIT DIAGRAM

    Symbol Pin diagram

    MODEL GRAPHS:

    INPUT CHARACTERISTICS

    OUTPUT CHARACTERISTICS:

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    8. Characteristics of CB configuration

    AIM: To observe and draw the input and output characteristics of a transistor

    connected in common base configuration.

    APPARATUS: Transistor, BC 107 - 1

    Regulated power supply (0-30V, 1A) - 2

    Voltmeter (0-20V) - 2

    Ammeters (0-100mA) - 2

    Resistor, 1000 - 2

    Bread board - 1

    Connecting wires - few

    THEORY:

    A transistor is a three terminal active device. T he terminals are emitter,

    base, collector. In CB configuration, the base is common to both input (emitter)

    and output (collector). For normal operation, the E-B junction is forward biasedand C-B junction is reverse biased.

    In CB configuration, IE is +ve, IC is ve and IB is ve.

    So,

    VEB=f1 (VCB,IE) and

    IC=f2 (VCB,IB)

    With an increasing the reverse collector voltage, the space-charge width

    at the output junction increases and the effective base width W decreases.

    This phenomenon is known as Early effect. Then, there will be less chance for

    recombination within the base region. With increase of charge gradient with in

    the base region, the current of minority carriers injected across the emitter

    junction increases.The current amplification factor of CB configuration is given

    by,

    = IC/ IE

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    OBSERVATIONS:

    INPUT CHARACTERISTICS: OUT PUT CHAREACTARISTICS:

    S.NO

    VCB = VCB =

    VEB

    (V)

    IE

    (A)

    VEB

    (V)

    IE

    (A)

    FORMULA:

    Reverse Voltage Gain (kb) =VEB

    A VcBA Ic'

    Output Conductance (hob) =

    IE =constant

    =

    A lc(ii) Forward Current Gain (Iii,) =

    Vc8 =constant

    S.NO

    IE = IE =

    VCB

    (V)

    IC

    (mA)

    VCB

    (V)

    IC

    mA)

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    PROCEDURE:

    INPUT CHARACTERISTICS:

    1. Connections are made as per the circuit diagram.

    2. For plotting the input characteristics, the output voltage VCE is kept constant

    at 0V and for different values of VEB note down the values of IE.

    3. Repeat the above step keeping VCB at 2V, 4V, and 6V.All the readings are

    tabulated.

    4. A graph is drawn between VEB and IE for constant VCB.

    OUTPUT CHARACTERISTICS:

    1. Connections are made as per the circuit diagram.

    2. For plotting the output characteristics, the input IE iskept constant at 10m A

    and for different values of VCB, note down the values of IC.

    3. Repeat the above step for the values of IE at 20 mA, 40 mA, and 60 mA,

    all the readings are tabulated.

    4. A graph is drawn between VCB and Ic for constant IE

    RESULT:

    The input and output characteristics of the transistor are drawn.

    parameters:

    (i) Input Impedance (kb) = -------------

    (ii) Forward Current Gain (hp) = ----

    (hi) Reverse Current Gain ( kb) = --- -

    (iv) Output Conductance (hGb) --------

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    CIRCUIT DIAGRAM

    Symbol Pin diagram

    MODEL GRAPH:

    TRANSFER CHARACTERISTICS

    DRAIN CHARACTERISTICS

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    9. CHARACTERISTICS OF FET

    AIM: a). To draw the drain and transfer characteristics of a given

    FET.

    b). To find the drain resistance (rd) amplification factor () and

    Tran conductance (gm) of the given FET.

    APPARATUS: FET (BFW-10) - 1

    Regulated power supply - 2

    Voltmeter (0-20V) - 2

    Ammeter (0-100mA) - 1

    Bread board - 1

    Connecting wires - few

    THEORY:A FET is a three terminal device, having the characteristics of high input

    impedance and less noise, the Gate to Source junction of the FET s always

    reverse biased. In response to small applied voltage from drain to source, the n-

    type bar acts as sample resistor, and the drain current increases linearly with

    VDS. With increase in ID the ohmic voltage drop between the source and the

    channel region reverse biases the junction and the conducting position of the

    channel begins to remain constant. The VDS at this instant is called pinch of

    voltage.

    If the gate to source voltage (VGS) is applied in the direction to

    provide additional reverse bias, the pinch off voltage ill is decreased.

    In amplifier application, the FET is always used in the region

    beyond the pinch-off. FDS=IDSS(1-VGS/VP)^2

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    OBSERVATIONS:

    DRAIN CHARACTERISTICS: TRANSFER CHAREACTARISTICS:

    S.NOVGS = VGS =VDS

    (V)

    ID

    (A)

    VDS

    (V)

    ID

    (A)

    CALCULATION:

    S.NO

    VDS = VDS =

    VGS

    (V)

    ID

    (mA)

    VGS

    (V)

    ID

    mA)

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    PROCEDURE:

    1. All the connections are made as per the circuit diagram.

    2. To plot the drain characteristics, keep VGS constant at 0V.

    3. Vary the VDD and observe the values of VDS and ID.4. Repeat the above steps 2, 3 for different values of VGS at 0.1V and 0.2V.

    5. All the readings are tabulated.

    6. To plot the transfer characteristics, keep VDS constant at 1V.

    7. Vary VGG and observe the values of VGS and ID.

    8. Repeat steps 6 and 7 for different values of VDS at 1.5 V and 2V.

    9. The readings are tabulated.

    10. From drain characteristics, calculate the values of dynamic resistance (rd) by

    using the formula

    rd = VDS/ID

    11. From transfer characteristics, calculate the value of transconductace (gm) By

    using the formula

    Gm=ID/VDS

    12.Amplification factor () = dynamic resistance. Tran conductance

    = VDS/VGS

    RESULT :

    Thus the drain and transfer characteristics of a given FET are drawn

    1. dynamic resistance (rd) =

    2. Amplification factor ()=

    3. Tran conductance (gm)=

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    CIRCUIT DIAGRAM FOR SCR:

    Symbol Pin diagram

    MODEL WAV EFORM:

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    10. a.CHARACTERISTICS OF SCR

    AIM: To draw the V-I Charateristics of SCR

    APPARATUS: SCR (TYN616) - 1

    Regulated Power Supply (0-30V) - 2

    Resistors 10k, 1k - 1 each

    Ammeter (0-50)A - 1

    Voltmeter (0-10V) - 2

    Breadboard - 1

    Connecting Wires. - few

    THEORY:

    It is a four layer semiconductor device being alternate of P-type and N-typesilicon. It consists os 3 junctions J1, J2, J3 the J1 and J3 operate in forwarddirection and J2 operates in reverse direction and three terminals called anode

    A, cathode K , and a gate G. The operation of SCR can be studied when thegate is open and when the gate is positive with respect to cathode.

    When gate is open, no voltage is applied at the gate due toreverse bias of the junction J2 no current flows through R2 and hence SCR is atcutt off. When anode voltage is increased J2 tends to breakdown. When thegate positive,with respect to cathode J3 junction is forward biased and J2 is

    reverse biased .Electrons from N-type material move across junction J3 towardsgate while holes from P-type material moves across junction J3 towardscathode. So gate current starts flowing ,anode current increaase is in extremelysmall current junction J2 break down and SCR conducts heavily.

    When gate is open thee breakover voltage is determined on theminimum forward voltage at which SCR conducts heavily.Now most of thesupply voltage appears across the load resistance.The holfing current is themaximum anode current gate being open , when break over occurs.

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    OBSERVATION

    Gate current , IG = ----------mA

    VAK(V) IAK ( A)

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    PROCEDURE:

    1. Connections are made as per circuit diagram.

    2. Keep the gate supply voltage at some constant value

    3. Vary the anode to cathode supply voltage and note down the readings of

    voltmeter and ammeter.Keep the gate voltage at standard value.

    4. A graph is drawn between VAK and IAK .

    RESULT: Thus the Break over voltage, on state resistance, holding current

    and latching current of SCR have found out and the characteristics is alsoplotted.

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    CIRCUIT DIAGRAM:

    Symbol Pin diagram

    MODEL GRAPH:

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    10.b . CHARACTERISTICS OF UJT

    AIM: To observe the characteristics of UJT and to calculate the Intrinsic Stand-

    Off Ratio ().

    APPARATUS:

    Regulated Power Supply (0-30V, 1A) - 2Nos

    UJT 2N2646 - 1

    Resistors 10k, 47, 330 - 1 each

    Multimeters - 2NosBreadboard - 1

    Connecting Wires - few

    THEORY:

    A Unijunction Transistor (UJT) is an electronic semiconductor device

    that has only one junction. The UJT Unijunction Transistor (UJT) has three

    terminals an emitter (E) and two bases (B1 and B2). The base is formed by

    lightly doped n-type bar of silicon. Two ohmic contacts B1 and B2 are attached

    at its ends. The emitter is of p-type and it is heavily doped. The resistance

    between B1 and B2, when the emitter is open-circuit is called interbase

    resistance.The original unijunction transistor, or UJT, is a simple device that is

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    OBSEVATIONS:

    VBB=1V VBB=2V VBB=3V

    VEB(V) IE(mA) VEB(V) IE(mA) VEB(V) IE(mA)

    CACULATION:

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    essentially a bar of N type semiconductor material into which P type material

    has been diffused somewhere along its length. The 2N2646 is the most

    commonly used version of the UJT.

    The UJT is biased with a positive voltage between the two

    bases. This causes a potential drop along the length of the device. When the

    emitter voltage is driven approximately one diode voltage above the voltage at

    the point where the P diffusion (emitter) is, current will begin to flow from the

    emitter into the base region. Because the base region is very lightly doped, the

    additional current (actually charges in the base region) causes (conductivity

    modulation) which reduces the resistance of the portion of the base between

    the emitter junction and the B2 terminal. This reduction in resistance means that

    the emitter junction is more forward biased, and so even more current is

    injected. Overall, the effect is a negative resistance at the emitter terminal. Thisis what makes the UJT useful, especially in simple oscillator circuits.When the

    emitter voltage reaches Vp, the current startsto increase and the emitter voltage

    starts to decrease.This is represented by negative slope of the characteristics

    which is reffered to as the negative resistance region,beyond the

    valleypoint ,RB1 reaches minimum value and this region,VEB propotional to IE.

    FORMULA :

    VP = VBB + VD = (VP-VD) / VBB

    PROCEDURE:

    1. Connection is made as per circuit diagram.

    2. Output voltage is fixed at a constant level and by varying input voltage

    corresponding emitter current values are noted down.

    3. This procedure is repeated for different values of output voltages.4. All the readings are tabulated and Intrinsic Stand-Off ratio is calculated

    using = (Vp-VD) / VBB

    5. A graph is plotted between VEE and IE for different values of VBE.

    RESULT: The characteristics of UJT are observed and the values of Intrinsic

    Stand-Off Ratio is calculated.

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    CIRCUIT DIAGRAM:

    DEVICE SYMBOL: PIN DIAGRAM:

    MODEL GRAPH:

    TABULATION:FORWARD BIAS: REVERSE BIAS:

    Supply

    voltage

    (Vr)

    DIACcurrent(IA)

    (mA)

    Supply

    voltage

    (Vs)

    DIACcurrent(IA)

    (mA)

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    11. a. STATIC CHARACTERISTICS OF DIACAIM:To determine the static characteristics of DIAC in both direction.

    APPARATUS REQUIRED:

    1 Regulated power supply (0-30) V 22 Voltmeter (0-30) V MC 2

    3 Ammeter (0-10) mA MC 14 Ammeter (0-100) mA MC 15 DIAC DB3 16 Resistor 1K_ 27 Bread board 18 Connecting wires

    THEORY:

    A DIAC is a bidirectional diode. It conducts in both direction.There current flowingthrough the device can not be controlled.

    STATIC CHARACTERISTICS OF DIAC:The VI characteristics in forward and reverse directions is divided into tworegions.1. Blocking state:For applied positive voltage is less than +VBO and negative voltage is lessthan VBO,the DIAC blocks the flow of current and behaves as an open switch.2. Conduction state:For applied positive voltage is greater than +VBO and negative voltage isgreater than VBO, the DIAC starts conducting and behaves as closed switch.

    PROCEDURE:

    1. Connections are given as per the circuit diagram.2. By increasing the supply voltage, the corresponding voltage and current arenoted down.3. The terminal of DIAC is reversed.4. By increasing the supply voltage, the corresponding voltage and current arenoted down.5. The graph is plotted.

    RESULT:The characteristics of DIAC in both directions are also plotted.

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    CIRCUIT DIAGRAM:

    DEVICE SYMBOL: PIN DIAGRAM:

    MODEL GRAPH:

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    11. b. STATIC CHARACTERISTICS OF TRIAC.

    EXPT NO:DATE :

    AIM:To determine the static characteristics of TRIAC in both direction and to calculatethe break over voltage, holding current and latching current.

    APPARATUS REQUIRED:

    1 Regulated power supply (0-30) V 22 Voltmeter (0-30) V MC 23 Ammeter (0-10) mA MC 14 Ammeter (0-100) mA MC 1

    5 TRIAC BT136 16 Resistor 1K_ 27 Bread board 18 Connecting wires

    THEORY:A TRIAC is a bidirectional thyristor with three temials.It is used extensively for thecontrol of power in ac circuits.When in operation a triac is equivalent to two SCRsconnected in antiparallel.the terminals are designated as MT1,MT2 and the gateG.Withno gate signal to gate,the triac will block both half cycles of the applied voltage in

    casepeak value of this voltage is less than the breakover voltage of Vb01 or Vbo2 ofthe triac.The turn on process of a triac arei) MT2 is positive and gate current is also positive.ii)MT2 is positive but gate current is negative.iii)MT2 is negative but gate current is positiveiv)Both MT2 aqnd gate current are negative.

    PROCEDURE:1. Connections are given as per the circuit diagram.

    2. The value of gate current IG is set to zero or minimum value by adjusting thegate supply voltage VGG.3. By varying the anode - cathode voltage VAK from 0 to 10V with a step of 2V,the corresponding values of IA is noted down.4. The gate voltage is gradually applied, until SCR fires, and then thecorresponding IG, VAK and IA are taken down. Then the supply voltage VAA isincreased and IA is noted down.5. The point at which the SCR fires gives the value of break over voltage VBO.6. A graph of VAK vs IA is to be plotted.7. The on state resistance can be calculated from the graph by using a formula.

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    TABULATION:

    Gate current , IG = ----------mA

    AnodeCathode

    voltage (VFK) (V)

    Anodecurrent (IA)

    (mA)

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    8. The gate supply voltage VGG is to be switched off.9. The ammeter reading is observed by reducing the anode cathode voltageVAK. The point at which the ammeter reading suddenly goes to zero gives thevalue of Holding current IH.10. The procedure is repeated for another set of gate current IG.

    RESULT:Thus the break over voltage, on state resistance, holding current and latchingcurrent of TRIAC have found out and the characteristics is also plotted.

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    CIRCUIT DIAGRAM:

    DEVICE SYMBOL: PIN DIAGRAM:

    MODEL GRAPH:

    TABULATION:

    I. Under DARK condition II. Under illumination

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    EXPT NO:DATE :

    12. a. STATIC CHARACTERISTICS OF PHOTO DIODE

    AIM:To determine the static characteristics of photo diode.

    APPARATUS REQUIRED:

    1 Photo diode QSD2030F 12 Voltmeter (0-15)v 13 Resistor 10_ 14 Ammeter (0-50)A 15 Lamp 100W 16 Regulated power supply (0-15) V 1

    7 Bread board 18 Connecting wires Req

    THEORY:If a PN junction is illuminated, hole- electron pairs are generated by the incidentlight energy. Minority charge carriers are swept across the junction. Increasingthe level ofillumination increases the number of charge carriers generated and thusincreases theamount of reverse current flowing. When the reverse bias voltage across aphoto-diode is

    removed, the available minority charge carriers will continue to be swept acrossthejunction by the barrier potential. To reduce the current to zero, it is necessary toforwardbias the junction by an amount equal to the barrier potential.

    PROCEDURE:

    Connections are given as per the circuit diagram. Light source is placed at a certain distance from photo diode. Supply voltage is varied from 0V and corresponding ammeter readings are

    noted. Voltage is reduced to zero and the corresponding ammeter reading is noted. Readings are tabulated and characteristics curves are drawn..

    RESULT:Thus the static characteristic of photo-diode is obtained

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    CIRCUIT DIAGRAM:

    DEVICE SYMBOL:

    MODEL GRAPH:

    TABULATION:

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    12. b. STATIC CHARACTERISTICS OF PHOTO TRANSISTOR

    AIM:To obtain the static characteristics of photo transistor.

    APPARATUS REQUIRED:

    1 Photo transistor L14G2 12 Voltmeter (0-30)v 13 Resistor 220_ 14 Ammeter (0-100)mA 15 Lamp 100W 16 Bread board 17 Regulated power supply (0-30) V 18 Connecting wires

    THEORY:If a collector-base junction in a photo transistor is illuminated, hole- electron pairsare generated by the incident light energy. Minority charge carriers are sweptacross the

    junction, ICBO increases. Increasing the level of illumination, increases the numberofcharge carriers generated and thus increases the amount of collector currentflowing.Photo transistor provides a much larger output current than photo diode.

    PROCEDURE: Connections are given as per the circuit diagram. Light source is placed nearer to the base of the photo transistor. Supply voltage is varied from 0V and corresponding ammeter readings arenoted. Readings are tabulated and characteristics curves are drawn.

    RESULT:Thus the static characteristic of photo-transistor is obtained.

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