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EDC Lab Manual 2nd Semester

Nov 27, 2014

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EDC Lab Manual 2nd semester

(EE2207) ELECTRON DEVICES & CIRCUITS LAB Sl.No. Expt.No. Date Name oI the Experiment Marks Signature 1 2 3 4 5 6 7 8 9 10 Sl.No. Expt.No. Date Name oI the Experiment Marks Signature 11 12 13 14 15 16 17 18 19 20 LIST OF EXPERIMENTS 1. Characteristics of PN junction diode 2. Characteristics of Zener diode 3. Characteristics of transistor under CE configuration 4. Characteristics of transistor under CB configuration 5. Characteristics of transistor under CC configuration 6. Characteristics of field effect transistor 7. Characteristics of uni junction transistor 8. Silicon controlled rectifier characteristics 9. Characteristics of DAC 10. Characteristics of photo diode 11. Characteristics of photo transistor 12. Single phase half wave and full wave rectifiers with capacitor filters 13. Series and parallel resonance circuits 14. Characteristics of TRAC 15. Single phase half wave and full wave rectifiers with inductive filters 16. Static characteristics of Thermistors 17. Differential amplifiers using FET 18. Study of CRO 19. Realization of passive filters 1. CHARACTERISTICS OF P-N 1UNCTION DIODE Expt.No: Date : AIM: To study the P-N iunction Diode characteristics under Iorward and reverse bias condition. APPARATUS REQUIREMENT: S.No. Equipment and Components Range Quantity 1. Power Supply (0-30)V 1 2. Ammeter (0-30)mA 1 (0-100)A 1 3. Voltmeter (0-10) V 1 (0-1) V 1 4. Diode IN 4007 1 5. Resistor 1K 1 THEORY : A PN iunction Diode is a two terminal iunction diode. It conduct only in one direction (only on Iorward biasing) FORWARD BIAS: On Iorward bias. initially no current Ilows due to barrier potential. As the applied voltage exceeds the barrier potential the charge carries gain suIIicient energy to cross the potential barrier and hence enter the other region. The holes which are maiority carriers in the P- region. become minority carriers on entering the N-regions and electrons REVERSE BIAS: On reverse bias. the maiority charge carriers are attracted towards the terminals due to the applied potential resulting in the winding oI the depletion region. There will be some current Ilows in the device due to thermally generated uniminority carries. this current is reIerred to as reverse saturation current (Io) and it increases with temperature. When the applied reverse voltage is increased beyond the certain limit. it results in break down. PROCEDURE: 1. Connection as per the circuit as per the diagram. 2. Vary the applied voltage V in steps oI 0.1V. 3. Note down the corresponding ammeter readings I. 4. Plot a graph between V&I. 5. Calculate the dynamic resistance v oV / oI. V A A RESULT: Thus the VI characteristics oI PN iunction diode were studied. 1. Forward dynamic Resistance 2. Reverse dynamic Resistance CIRCUIT DIAGRAM FORWARD BIAS: 1K (0-30) mA A (0-30) V (0-1) V IN4007 K REVERSE BIAS: 1K (0-30) mA K (0-30) V (0-1) V IN4007 A TABULATION: FORWARD BIAS: S.No Voltage(V) Current(mA) MODEL GRAPH: If(mA) VBR Vr(V) Vf(V) Ir(mA) CHARACTERISTICS OF ZENER DIODE Expt.No: Date : AIM: To determine the break down voltage oI a given zener diode. APPARATUS REQUIREMENT: S.No. Equipment and Components Range Quantity 1. Power Supply (0-30)V 1 2. Ammeter (0-30)mA 1 3. Voltmeter (0-10) V 1 4. Zener Diode FZ 6V 1 5. Resistor 1K 1 THEORY : FORWARD BIAS: A properly doped crystal diode. which has a sharp break down potential. As the applied potential increases it exceeds to better potential at one value and the charge carrier gain suIIicient energy to cross the potential barrier and enter the other region. REVERSE BIAS: When the reverse bias is applied due to minority carriers small amount oI current i.e.. reverse saturation current Ilows across the iunction. As the reverse bias is increased to break down voltage sudden rise in the current takes place due to zener eIIect. Zener eIIect normally oI PN iunction oI zener diode is heavily doped due to heavily doped. the depletion layer will be narrow. PROCEDURE: 1. Connection as per the circuit as per the diagram. 2. Vary the power supply such a way that the readings are taken in steps oI 0.1V 3. Plot the graph V & I . 4. Calculate the dynamic resistance v oV / oI. RESULT: V A V A Thus the breakdown voltage oI a given zener diode was determined. CIRCUIT DIAGRAM: FORWARD BIAS: 1K (0-30)mA - A (0-30) V FZ 6V (0-10) V - K - REVERSE BIAS: 1K (0-30)mA - K (0-30) V FZ 6V (0-10) V - A - TABULATION: FORWARD BIAS: S.No. Forward Bias Reverse Bias VR(Volts) IF(mA) VR(Volts) IF(mA) MODEL GRAPH: If(mA) I2 VBR I1 V r(V) V1 V1 V 2 V f (V) Ir(mA) 3a.CHARACTERISTICS OF CE CONFIGURATION USING B1T Expt.No: Date : AIM: To plot the transistor characteristics oI CE conIiguration. APPARATUS REQUIRED: S.No. Equipment and Components Range Quantity 1. Power Supply (0-30)V 2 2. Ammeter (0-100)A 1 (0-25)mA 1 3. Voltmeter (0-30) V 1 (0-1) V 1 4. Transistor BC 107 1 5. Resistors 10K. 1K. 1 THEORY : A BJT is a three terminal two-iunction semiconductor device in which the conduction is due to both the charge carrier. Hence it is a bipolar device and it ampliIier the sine waveIorm as they are transIerred Irom input to output. BJT is classiIied into two types NPN and PNP. A NPN transistor consists oI two N types in between which a layer oI P is sandwiched. The transistor consists oI three terminal emitter. collector and base . The emitter layer is the source oI the charge carriers and it is heartily doped with a moderate across sectional area . The collector collects the charge carries and hence moderate doping and large cross the sectional area. The base region acts a path Ior the movement oI the charge carries. In order to reduce the recombination oI holes and electrons the base region is lightly doped and is oI hollow cross sectional area. Normally the transistor operates with the EB Iorward biased. In transistor. the current is same in both iunctions. which indicates that there is a transIer oI resistance between the two iunctions. One to this Iact the transistor the transistor is known as transIer resistance oI transistor. PROCEDURE: INPUT CHARACTERISTICS: 1. Connect the circuit as per the circuit diagram. 2. Set VCE .vary VBE regular intervals oI steps and note down the corresponding IB reading . Repeat the above procedure Ior diIIerent values oI VCE. 3. Plot the graph : VBE Vs IB Ior a constant VCE. OUTPUT CHARACTERISTCS: 1. Connect the circuit as per the circuit diagram. 2. Set IB . vary VCE in regular intervals oI steps and note down the corresponding IC reading . Repeat the above procedure Ior diIIerent values oI IB . 3. Plot the graph : VCE Vs IC Ior a constant IB . RESULT: The transistor characteristics oI a common emitter (CE) conIiguration were plotted and studied. 1. hie 2. hIe 3. hre 4. hoe CIRCUIT DIAGRAM: (0 - 10) mA 10K

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