# ECE 4371, Fall, 2014 Introduction to Telecommunication Engineering/Telecommunication Laboratory

Mar 13, 2016

## Documents

ECE 4371, Fall, 2014 Introduction to Telecommunication Engineering/Telecommunication Laboratory. Zhu Han Department of Electrical and Computer Engineering Class 14 Oct. 20 th , 2014. Outline. Match Filter Equalizer Timing. Receiver Structure. - PowerPoint PPT Presentation

• ECE 4371, Fall, 2015

Introduction to Telecommunication Engineering/Telecommunication Laboratory

Zhu Han

Department of Electrical and Computer Engineering

Class 14

Oct. 13th, 2015

ECE 4371 Fall 2008

• OutlineMatch FilterEqualizerTiming

ECE 4371 Fall 2008

• Receiver StructureMatched filter: match source impulse and maximize SNRgrx to maximize the SNR at the sampling time/outputEqualizer: remove ISITiming When to sample. Eye diagramDecision d(i) is 0 or 1d(i)gTx(t)Noise na(t)?gRx(t)Figure 7.20

ECE 4371 Fall 2008

• Matched FilterInput signal s(t)+n(t)

Maximize the sampled SNR=s(T0)/n(T0) at time T0

ECE 4371 Fall 2008

• Matched filter exampleReceived SNR is maximized at time T0example:transmit filterreceive filter(matched)

ECE 4371 Fall 2008

• Matched Filter

ECE 4371 Fall 2008

• Matched Filter

ECE 4371 Fall 2008

• Matched Filter

ECE 4371 Fall 2008

• Since g(t)Matched Filter

ECE 4371 Fall 2008

• Properties of Matched Filters

ECE 4371 Fall 2008

• ECE 4371 Fall 2008

• EqualizerWhen the channel is not ideal, or when signaling is not Nyquist, There is ISI at the receiver side. In time domain, equalizer removes ISR. In frequency domain, equalizer flat the overall responses.In practice, we equalize the channel response using an equalizer

ECE 4371 Fall 2008

• Zero-Forcing EqualizerThe overall response at the detector input must satisfy Nyquists criterion for no ISI:

The noise variance at the output of the equalizer is:

If the channel has spectral nulls, there may be significant noise enhancement.

ECE 4371 Fall 2008

• Transversal Transversal Zero-Forcing Equalizer

If Ts

• Zero-Forcing Equalizer continueZero-forcing equalizer, figure 7.22 and example 7.3

Example: Consider a baud-rate sampled equalizer for a system for which

Design a zero-forcing equalizer having 5 taps.

ECE 4371 Fall 2008

• MMSE EqualizerIn the ISI channel model, we need to estimate data input sequence xk from the output sequence ykMinimize the mean square error.

ECE 4371 Fall 2008

ECE 4371 Fall 2008

• Decision Feedback EqualizerTo use data decisions made on the basis of precursors to take care of postcursorsConsists of feedforward, feedback, and decision sections (nonlinear)DFE outperforms the linear equalizer when the channel has severe amplitude distortion or shape out off.

ECE 4371 Fall 2008

• Different types of equalizersZero-forcing equalizers ignore the additive noise and may significantly amplify noise for channels with spectral nullsMinimum-mean-square error (MMSE) equalizers minimize the mean-square error between the output of the equalizer and the transmitted symbol. They require knowledge of some auto and cross-correlation functions, which in practice can be estimated by transmitting a known signal over the channelAdaptive equalizers are needed for channels that are time-varyingBlind equalizers are needed when no preamble/training sequence is allowed, nonlinearDecision-feedback equalizers (DFEs) use tentative symbol decisions to eliminate ISI, nonlinearUltimately, the optimum equalizer is a maximum-likelihood sequence estimator, nonlinear

ECE 4371 Fall 2008

• Timing ExtractionReceived digital signal needs to be sampled at precise instants. Otherwise, the SNR reduced. The reason, eye diagramThree general methodsDerivation from a primary or a secondary standard. GPS, atomic closkTower of base stationBackbone of InternetTransmitting a separate synchronizing signal, (pilot clock, beacon)Satellite Self-synchronization, where the timing information is extracted from the received signal itselfWirelessCable, Fiber

ECE 4371 Fall 2008

• ExampleSelf Clocking, RZ

Contain some clocking information. PLL

ECE 4371 Fall 2008

• Timing/Synchronization Block DiagramAfter equalizer, rectifier and clipperTiming extractor to get the edge and then amplifierTrain the phase shifter which is usually PLLLimiter gets the square wave of the signalPulse generator gets the impulse responses

ECE 4371 Fall 2008

• Timing JitterRandom forms of jitter: noise, interferences, and mistuning of the clock circuits.Pattern-dependent jitter results from clock mistuning and, amplitude-to-phase conversion in the clock circuit, and ISI, which alters the position of the peaks of the input signal according to the pattern.Pattern-dependent jitter propagates Jitter reductionAnti-jitter circuits Jitter buffers Dejitterizer

ECE 4371 Fall 2008

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