ECE 261 Krish Chakrabarty 1 Arithmetic Building Blocks Datapath elements Adder design Static adder Dynamic adder Multiplier design Array multipliers Shifters, Parity circuits
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ECE 261 Krish Chakrabarty 1 Arithmetic Building Blocks Datapath elements Adder design –Static adder –Dynamic adder Multiplier design –Array multipliers.

Dec 31, 2015

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• A Generic Digital ProcessorMEMORYDATAPATHCONTROLInput-Output

• Building Blocks for Digital Architectures Arithmetic unit- Bit-sliced datapath ( adder, multiplier, shifter, comparator, etc.) Memory- RAM, ROM, Buffers, Shift registers Control- Finite state machine (PLA, random logic.)- Counters Interconnect- Switches- Arbiters- Bus

• Bit-Sliced DesignBit 3Bit 2Bit 1Bit 0ControlTile identical processing elementsData-inData-outRegisterAdderShifterMultiplierSignalsDataControlMetal 2(control)Metal 1(data)

ABCoutS0000010110011110

ABCCoutS0000000101010010111010001101101101011111

• The Binary AdderABCoutSumCinFulladderSum = A B C = ABCi + ABCi + ABCi + ABCi Co = AB + BCi + ACi

• Sum and Carry as a functions of P, GDefine 3 new variable which ONLY depend on A, BGenerate (G) = ABPropagate (P) = A +B

• The Ripple-Carry Addere delay linear with the number of bitstd = O(N)Goal: Make the fastest possible carry path circuittd = (N-1)tcarry + tsum

• Complimentary Static CMOS Full AdderNote:1) S = ABCi + Co(A + B + Ci)2) Placement of Ci3) Two inverter stages for each CoO(N) delay

• Inversion PropertyInverting all inputs results in inverted outputs

• Minimize Critical Path by Reducing Inverting StagesCo,0Ci,0Co,1Co,2Co,3FAFAFAFAOdd CellEven CellExploit Inversion PropertyNeed two different types of cells, FA: no inverter in carry path A0A1B0A2B1B2B3A3S0S1S2S3

• A better structure: the Mirror Adder

• The Mirror AdderSymmetrical NMOS and PMOS chains identical rising and falling transitions if the NMOS and PMOS devices are properly sized. Maximum of two series transistors in the carry-generation circuitry. Critical issue: minimization of the capacitance at Co. Reduction of the diffusion capacitances important. The capacitance at Co composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell . Transistors connected to Ci placed closest to output.Only the transistors in carry stage have to be optimized for speed. All transistors in the sum stage can be minimal size.

• NP-CMOS Adder17 transistors,ignoring extra inverters for inputsand outputs

• Manchester Carry ChainP4G3G4VDDCo,4 Only nMOS transmission gates used. Why? Delay of long series of pass gates: add buffers

• Carry-Bypass AdderFAFAFAFAP0G1P0G1P2G2P3G3Co,3Co,2Co,1Co,0Ci,0FAFAFAFAP0G1P0G1P2G2P3G3Co,2Co,1Co,0Ci,0Co,3BP=PoP1P2P3Idea: If (P0 and P1 and P2 and P3 = 1)then Co3 = C0, else kill or generate.

• Manchester-Carry ImplementationCo,3

• Carry-Bypass Adder (cont.)Design N-bit adder using N/M equal length stagese.g. N = 16, M = 4What is the critical path?tp = tsetup + Mtcarry + (N/M-1)tbypass + Mtcarry + tsum , i.e. O(N)

• Carry-Select AdderSetup"0" Carry Propagation"1" Carry PropagationMultiplexerSum GenerationCo,k-1Co,k+3"0""1"P,GCarry VectorGenerate carry out for both 0 and 1 incoming carries4-bit block for bitsk, k+1, k+2, k+3

• Carry Select Adder: Critical Path

• Carry-Select Adder: Linear Configuration(1)(5)(5)(5)(6)(1)(7)(8)(5)(5)Are equal-sized blocks best?

• Linear Carry Select "0""1"Bit 0-3Bit 4-7Bit 8-11Bit 12-15S0-3S4-7S8-11S12-15Co,15Co,11Co,7Co,3Ci,0

• Square Root Carry Select "0""1"Co,15Co,11Co,7Co,3Ci,0(1)(4)(3)(3)(4)(1)(5)(6)(6)(5)Bit 0-1Bit 2-4Bit 5-8Bit 9-13i.e., O(N)

• Carry Look-Ahead - Basic Idea Delay independent of the number of bitsS0S1SN-1

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