Ec1316 Embedded Systems

7/23/2019 Ec1316 Embedded Systems

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ROEVER ENGINEERING COLLEGE

PERAMBALUR DEPARTMENT OF

ECE

SUBJECT NAME :EMBEDDED SYSTEMS

UNIT I

INTRODUCTION TO EMBEDDED SYSTEMS

Definition and classification Overview of processors and hardware units in an embeddedsystem Software embedded into the system Exemplary embedded systems Embedded

Systems on a hip !SO" and the use of #$SI desi%ned circuits&

ANSWER KEYS

PART A

1. Define: Eme!!e! S"#$em#

omputer hardware inte%rated with software for dedicated application&

%. Gi&e $'e ()*##ifi(*$i+n +f *n eme!!e! #"#$em.

Small scale' ( or )* bit microcontroller with little h+w and s+w,

-edium scale ' )* or ./ bit micro controller, DS0 or 1IS processor

Sophisticated enormous h+w 2 s+w and pro%rammable lo%ic arrays

,. W'*$ *-e $'e (+m+nen$# +f eme!!e! #"#$em '*-!/*-e0

0rocessor, timer, interrupt controller, display devices, I+O ports, power supply and

re3uired application circuits&

. W'*$ *-e $'e &*-i+2# f+-m# +f mem+-ie# in $'e #"#$em#0

14-, 1O-, 01O-, EE01O-, 5lash and its explanation&

3. W'*$ i# GPIB0

6eneral purpose interface bus follows IEEE 7(( bus standard, used to lin8 various

instruments to the systems&

4. N*me im+-$*n$ eme!!e! -+(e##+- ('i 2#e! in in!2#$-ie#0

5amily name

41- family 41- 9: and 41- ;:

INTE$ family i;*OT !7"

?ardware re3uiredA

0rocessor' -icro controller, internal bus' ( bit, processor architecture IS ,

01O-' (F>, 14-' /=* bytes on chip, I+O ports'multiple ports for motors and for

an%le encoders, 0@- for D4,4D

!iii" -obile phone !7"

?ardware re3uiredA

0rocessor' -ulti processor system on chip, internal bus' ./ bit, processor

architecture 1IS, caches and --U, 01O-' )->,EE01O-'./8b, 14-' )-> on

So, I+O ports'8eypad and display ports, transceiver, real time detection of an event or

si%nal, 0@- for D4, 4D, modulation demodulation, DS0 instruction&

!iv"#oi c e pr o ce ssor !7"

?ardware re3uiredA

0rocessor' -icroprocessor GDS0, internal bus' ./ bit, processor architecture

1IS, caches and --U, 01O-' )->,EE01O- 2 5lash'7->, 14-' )-> off'chip,

I+O ports'input port for speech and output port for replay, real time detection of an

event or si%nal, 0@- for D4, 4D, DS0 instruction& Or any four exemplary systems&

5. loc8 dia%ram !7"

14-, 1om, EE01O-, processor, timer 2 interrupt controller, 4SF modulator,

har%e pump ircuit, interfacin% I+O, Transceiver antenna on silicon, power supply&

Explanation of the above !7"


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6.


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Timer circuit suitably confi%ured in the system cloc8

Used for schedulers and real time pro%rammers

Example' %eneration of


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. Define -+$+(+)

The way of transmittin% messa%es on a networ8 by usin% a software for addin% the

additional bits li8e startin% bits, headers, addresses of source and destination, errorcontrol bits and endin% bits&

3. W'*$ i# -e*) $ime ()+(0

4 cloc8 that continuously %enerate interrupts at re%ular interval endlessly& 4n 1T

interrupt tic8s the other timer of the system&

4. W'*$ i# #"#$em ()+(0

4 cloc8 scaled to the processor cloc8 and which always increments without stoppin% orresettin% and %enerates interrupts at preset time intervals&

5. W'*$ i# $ime- +&e-f)+/0

4 state in which the no& of count inputs exceeded the last ac3uirable values and onreachin% that state and interrupt can be %enerated&

6. W'*$ i# $'e 2#e +f PISO *n! SIPO

0ISO SI0O

Used for serial bit reception in

synchronous mode

Used for serial bit transmission

in synchronous mode

9. W'*$ i# DLC0

?i%h level data level lin8 control protocol for synchronous communication between

primary and secondary& It is a bit oriented protocol&

1;. W'*$ i# 2*#i i!i-e($i+n*) +-$0

4 port with the dual advanta%e of usin% pull up circuits as per the volta%e and current

level re3uired when interfacin% it and usin% no full up circuit for a short period

sufficient to drive a $STT$ circuit&

11. W'*$ i# me*n$ " m*#$e- #)*&e (+mm2ni(*$i+n0

4 communication between two processors when one processor %uides the transmissionof the bits to a slave after receivin% ac8nowled%ement from the address slave&

1%. Define #+f$/*-e $ime-.

This is software that executes and increases or decreases a count variable on an

interrupt from a timer output or form a real time cloc8 interrupt& 4 software timer can

also %enerate interrupt on overflow of count value or on finishin% value of the count variable&


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1,. W'*$ i# I%C0

I/ is a serial bus for interconnectin% Is &It has a start bit and a stop bit li8e an

U41T& It has seven fields for start,9 bit address, definin% a read or a write, definin% byte as

ac8nowled%in% byte, data byte, N4F and end&

1. W'*$ *-e $'e i$# in I%C (+--e#+n!in $+0

It has seven fields for start,9 bit address, definin% a read or a write, definin% byte

as ac8nowled%in% byte, data byte, N4F and end

13. W'*$ i# * CAN 2#0 W'e-e i# i$ 2#e!0

4N is a serial bus for interconnectin% a central ontrol networ8& It is mostly

used in automobiles& It has fields for bus arbitration bits, control bits for address and data

len%th data bits, 1 chec8 bits, ac8nowled%ement bits and endin% bits&

14. W'*$ i# USB0 W'e-e i# i$ 2#e!0US> is a serial bus for interconnectin% a system& It attaches and detaches a device

from the networ8& It uses a root hub& Nodes containin% the devices can be or%aniHed

li8e a tree structure& It is mostly used in networ8in% the IO devices li8e scanner in a

computer system&

15. W'*$ *-e $'e fe*$2-e# +f $'e USB -+$+(+)0

4 device can be attached, confi%ured and used, reset, reconfi%ured and used, share

the bandwidth with other devices, detached and reattached&

16. E7)*in -ief)" *+2$ PCI *n! PCI? 2#e#.

0I and 0I+C buses are independent from the I>- architecture &0I+C is an

extension of 0I and support *7+)


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4 cloc8 %enerator&

Input and Output start 1e%isters

>uffers&

Transmitter+1eceiver control&

%%. W'*$ i# me*n$ " DLC0

?D$ stands for K?i%h $evel Data $in8 ontrol&

?D$ is a bit oriented protocol&

?D$ is a synchronous data $in8 layer&

%,. N*me $'e DLC># f-*me #$-2($2-e0

5la% 4ddress ontrol Data 5S 5la%

%. Li#$ +2$ $'e #$*$e# +f $ime-0

There are eleven states as follows

1eset state

Idle state

0resent state

Over flow state

Over run state

1unnin% state 1eset enabled state + disabled

5inished state

$oad enabled + disabled

4uto reload enabled + disabled

Service routine execution enabled + disabled

%3. N*me #+me (+n$-+) i$ +f $ime-0

Timer Enable

Timer start Up count Enable

Timer Interrupt Enable


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PART B

1. *= W'*$ *-e $'e $"e# +f I?O !e&i(e#0 E7)*in i$ /i$' e7*m)e#.


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9" 1eset enabled+disabled State

(" $oad enabled+disabled State

;" 4uto 1e'$oad enabled+disabled State

)


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)& >ytes !or frames" need not maintain a constant phase difference&

This mode facilitates handsha8in% between the serial transmitter and

receiver port&

/& Thou%h the cloc8 must tic8 at a certain rate to transmit bits of a sin%le byte !or frame"

serially,

It is always implicit to the asynchronous data receiver&

Transmitter does not transmit alon% with the serial stream of bits&

The receiver cloc8 does not maintain identical fre3uency and constant phase

difference with transmitter cloc8&

,. *= En2me-*$e $'e f+-m*$# +f i$# in * #"n('-+n+2# DLC -+$+(+) *#e! ne$/+-

!e&i(e


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5rame

7& Data bits ompulsory m frame bits transmit such that each bit is at theline for time R T or, each frame is at the line for

time mR T&

=& 5S !5rame

hec8Se3uence" bits

*& 5rame End fla%

bits

ompulsory

)* bits in standard format and ./ in extendedformat

ompulsory5la% bits at end are also !


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fi2-e: P*-*))e) in2$ P+-$8 +2$2$ +-$ *n! * i!i-e($i+n*) +-$ f+- (+nne($in $'e !e&i(e

ro are buffers at the input port and output port

Each port connects to the address bus si%nals, 4i, and 4 throu%h a port address decoder

I O1D and I O @ 1 are additional control si%nals for a port read and write&

8 = Li#$ +2$ (+n#i!e-*$i+n# /'en in$e-f*(in * !e&i(e +-$


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C'*-*($e-i#$i(# $*en in$+ (+n#i!e-*$i+n /'en in$e-f*(in * !e&i(e+-$


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=& 4n I+O device may consist of multiple %i%abit !*// -bps to .&)/= 6bps" transceiver!s"&

1oc8er I+O T- serial .&)/= 6bps transreceivers are the examples of circuits that provide

the support circuitry for this rate&

*& 4 device for I+O may inte%rate a SerDes !serialiHation and De'serialiHation" subunit&

SerDes is a standard subunit in a device&

The %reat advanta%e of the SerDes unit is that these operations are fast&

9& -ultiple I+O standards have been developed for I+O devices& 4dvanta%es of multiple

standard support devices are obvious&

(& I+O device may inte%rate a di%ital 0hysical odin% Sub layer !0S"& 4nalo% audio and

video si%nals can then be pulse code modulated !0-" at the sub layer&

The advanta%e of an in'built 0S at a port device is that there is no need of external

0- codin%&

;& 4 device for I+O may inte%rate an analo% 0hysical -edia 4ttachment !0-4" unit for

connectin% direct inputs and outputs of voice, music, video and ima%es&

advanta%e of an in'built 0-4 is that the device directly connects to the

physical media&

4. E7)*in '*-!/*-e $ime- *n! #+f$/*-e $ime-


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*-!/*-e $ime-:

Im+-$*n$ +in$# $+ e (+&e-e!:


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Fi2-e: '*-!/*-e $ime-4UD rate %enerator&

5. = En2me-*$e $'e 2#e# +f $ime- !e&i(e#8 e7)*in e*(' /i$' i$# *)i(*$i+n


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Uses of timer device!("

)& 1eal Time loc8 Tic8s !System ?eart >eats"&

/& Initiatin% an event after a preset delay time&

.& Initiatin% an event after a comparison!s" between the preset time!s" with counted

value!s"&

7& apturin% the count value at the timer on an event&

=& 5indin% the time interval between two events&

*& @ait for a messa%e from a 3ueue or mailbox or semaphore for a preset time when usin%

1TOS&

9& @atchdo% timer&

(& >aud or >it 1ate ontrol for serial communication on a line or networ8&

;& Input pulse countin% when usin% a timer

)


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read !or" write cycle

5ourth fields )control bit It defines whether the present data is an

4c8

5ifth fileds (bit It is for I device data byte

Sixth filed )bit It is a bit ne%'4c8!N4F"

Seventh ) bit It is a stop bit li8e U41T

Di*-*m# it

Slave 4ddress 1+@ 4F Data bits Stop

>it

Di#*!&*n$*e#:

Time ta8en by the 4l%orithm in the master hardware that analses the bits throu%h I/ &

Slave ?ardware does not provide for the hardware that supports it&

Inte%ratedircu

it)

Inte%ratedircuit/

Inte%ra

tedircuit

.


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6= =E7)*in $'e USB 2#0 ul8 data transfer

iii"Interrupt driven data transfer iv" Iso synchronous transfer

US> is a polled bus

It supports three types of pipes i" Streams ii"Default control iii"messa%e


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9= *=De#(-ie $'e CAN 2#0


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E%


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0I card has )* mb flash 1om

0I bus attachement and detachment of the system peripheral

Three identification number by which device identifies its addresss space i" I+o port ii"

memory location iii" confi%uration re%

*7 bytes at the standart device independent confi%uration re% in a 0I device


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UNITIII

PROGRAMMING CONCEPTS AND EMBEDDED PROGRAMMING IN C8C0ro%rammin% in 4ssembly $an%ua%e !4$0" vs hi%h level lan%ua%e pro%ram

elements -acros and functions Use of pointers NU$$ pointers Use of function calls

-ultiple function calls in a cyclic order in the main function pointers 5unction 3ueues andinterrupt service routines Lueue pointers oncepts of embedded pro%rammin% in GG

Obected oriented pro%rammin% Embedded pro%rammin% in GG pro%ram compilers ross compiler OptimiHation of memory codes

PART H A

1. A!&* n $* e # +f ' i ' )e& e ) )* n 2 *e +& e - *## e m )" ) * n 2 * e :


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4ll the ar%ument passes the values and none of the ar%ument is a pointer

whenever a callin% function calls that function&

4. R e( 2 - #i&e f2n ( $i+n i # n +$ 2 # e ! in e m e !! e ! #"#$ e m e ( * 2 # e : ecause of memory constraints&

5or example ST4F %oes after each recursive call and it may cho8e the

memory space availability&

5. E7* m )e f +- inf in i$e )++ : :


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It says the way in which processes are chosen to %et promotion from ready stateto runnin% state&

1,. Define '"e- e-i+!0It refers the duration of time considered and also it is the least common multiple of allthe

processes&

1. W'*$ i# #('e!2)*i)i$"0It indicates any execution schedule is there for a collection of process in the

systemZs functionality&

13. W'*$ *-e $'e $"e# +f #('e!2)in0)& Time division multiple access schedulin%&/& 1ound robin schedulin%&

14. W'*$ i# ("()+#$*$i( #('e!2)in0In this type of schedulin%, interval is the len%th of hyper period Z?Z& 5or this interval,

a cyclostatic schedule is separated into e3ual siHed time slots&

15. Define -+2n! -+in #('e!2)in0This type of schedulin% also employs the hyperperiod as an interval& The processesare run

in the %iven order&

16. W'*$ i# #('e!2)in +&e-'e*!0It is defined as time of execution needed to select the next execution process&

19. W'*$ i# me*n$ " (+n$e7$ #/i$('in0The actual process of chan%in% from one tas8 to another is called a context switch&

%;. Define -i+-i$" #('e!2)in04 simple scheduler maintains a priority 3ueue of processes that are in therunnable state&

%1. W'*$ i# -*$e m+n+$+ni( #('e!2)in01ate monotonic schedulin% is an approach that is used to assi%n tas8 priority

for apreemptive system&

%%. W'*$ i# (-i$i(*) in#$*n$0It is the situation in which the process or tas8 posses hi%hest response time&

%,. W'*$ i# (-i$i(*) in#$*n$ *n*)"#i#0It is used to 8now about the schedule of a system& Its says that based on theperiods %iven,

the priorities to the processes has to be assi%ned&

%. Define e*-)ie#$ !e*!)ine fi-#$ #('e!2)in0This type of schedulin% is another tas8 priority policy that uses the nearest deadline as


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thecriterion for assi%nin% the tas8 priority&

PART B

1. Di#(2## in !e$*i) *+2$ $'e *!&*n$*e# +f A##em)" L*n2*e *n! i' Le&e))*n2*e in eme!!e! C>0


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' ontrol structures and onditional statements ma8e the pro%ram'flow path desi%n

tas8s simple

' 0ortability of non processor specific codes exists& Therefore, when hardware

chan%es, only the modules for the device drivers, device mana%ement and initial

boot up record data need modifications&

' 4dditional advanta%e of usin% embeddedDE as a hi%h level lan%ua%e, insertin%

the assembly lan%ua%e codes in between the embeddedDE codin%& This is called

in line assembly&

%. E7)*in $'e f+))+/in -+-*mmin e)emen$# /i$' #2i$*)e #"n$*7 *n! e7*m)e#.*= In()2!e !i-e($+-ie#


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' Source files are pro%ram files for the functions of application software&

' Source files need to be compiled

' 4 source file will also possess the preprocessor directives of the application andhave the first function from where the processin% will start& This function is

called main function&

( . C+n f i 2 - * $ i+n f i) e #: oolean IntrEnable

?ere IntrEnable is a %lobal variable of >oolean datatype and isvolatile

' 0reprocessor onstants

E%A define false

Ec1316 Embedded Systems

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