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DSP C5000 DSP C5000 Chapter 22 Chapter 22 Implementation of Viterbi Implementation of Viterbi Algorithm/Convolutional Algorithm/Convolutional Coding Coding Copyright © 2003 Texas Instruments. All rights reserve Copyright © 2003 Texas Instruments. All rights reserve
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DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

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Page 1: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

DSP C5000DSP C5000

Chapter 22Chapter 22

Implementation of Viterbi Implementation of Viterbi Algorithm/Convolutional CodingAlgorithm/Convolutional Coding

Copyright © 2003 Texas Instruments. All rights reserved.Copyright © 2003 Texas Instruments. All rights reserved.

Page 2: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 2

ObjectivesObjectives

Explain the Explain the Viterbi AlgorithmViterbi Algorithm E.g.: detection of sequence of symbolsE.g.: detection of sequence of symbols

Example of application on the Example of application on the GSM convolutional codingGSM convolutional coding

Present its Present its implementation on the C54x implementation on the C54x Specific hardwareSpecific hardware Specific instructionsSpecific instructions

Page 3: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 3

Viterbi Algorithm (VA)Viterbi Algorithm (VA)

Dynamic programmingDynamic programming Finds the most likely state transitions in a state diagram, given a noisy sequence Finds the most likely state transitions in a state diagram, given a noisy sequence

of symbols or an observed signal.of symbols or an observed signal. Applications inApplications in

Digital communications:Digital communications: Channel equalization, Detection of sequence of symbolsChannel equalization, Detection of sequence of symbols Decoding of convolutional codesDecoding of convolutional codes

Speech recognition (HMM)Speech recognition (HMM) Viterbi can be applied when the problem can be formulated by a Markov chain.Viterbi can be applied when the problem can be formulated by a Markov chain.

Page 4: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 4

Markov ChainMarkov Chain

Markov process Markov process kk::

If values of If values of k k form a countable set, it is form a countable set, it is a Markov chain. a Markov chain. kk state of the Markov chain at time k state of the Markov chain at time k

k 1 k k 1 k 1 kp( / , ...) p( / )

Page 5: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 5

Example of Markov ProcessExample of Markov Process

X k X k p

XXkk is independent of is independent of XXk-ik-i, i=1 to p+1., i=1 to p+1.

If If XXkk values belong to a countable set, it is a Markov chain. values belong to a countable set, it is a Markov chain.

1( ,..., )k k k pX X

Page 6: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 6

Signal Generator Markov ChainSignal Generator Markov Chain

S fk k k ( , ) 1

The signal The signal SSkk depends on the transitions of a Markov chain depends on the transitions of a Markov chain kk..

1 1( , ,..., ) ( , )k k k p k kh X X X f

X k Sk

k

Page 7: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 7

Example: Detection of a Sequence of Symbols Example: Detection of a Sequence of Symbols in Noisein Noise

Ak hk

Sk

Nk

Yk

Emitted Emitted symbolssymbols

Equivalent Equivalent Discrete Discrete model of the model of the channel channel

NoiseNoise

Observed noisy Observed noisy sequencesequence

The problem of the The problem of the detection of a sequence of symbolsdetection of a sequence of symbols is to find is to find the best state sequence for a given sequence of observations Yk the best state sequence for a given sequence of observations Yk with k in the interval [1,K].with k in the interval [1,K].

Y S Nk k k S h Ak i k ii

p

1

Sk is a signal generated by a Markov chainSk is a signal generated by a Markov chain

Page 8: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 8

Example: Detection of a Sequence of Symbols Example: Detection of a Sequence of Symbols in Noisein Noise

Suppose:Suppose:

k

0A

1

h h h0 1 21 0 5 0 25 . .

S A A Ak k k k 1

2

1

41 2

Observed sequence Observed sequence YYk k = 0.2, 0.7, 1.6, 1.2= 0.2, 0.7, 1.6, 1.2

Possible values for non-noisy outputs Possible values for non-noisy outputs

Sk = Sk = 1.75, 1.50, 1.25, 0.75, 1.00, 0.50, 0.25, 0.00

Page 9: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 9

Example: Detection of a Sequence of Symbols Example: Detection of a Sequence of Symbols in Noisein Noise

k k k

k k k

k k k

A A

A A

S f

( , )

( , )

( , )

1

1 1

1

There are 4 states in the Markov chain.There are 4 states in the Markov chain.

The transition between the different states can be The transition between the different states can be represented by a represented by a State DiagramState Diagram, or by a , or by a TrellisTrellis..

Page 10: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 10

Example: Detection of a Sequence of Symbols Example: Detection of a Sequence of Symbols in Noise, in Noise, State DiagramState Diagram

00

01

11

10

(0,0)

(0,0.25)

(1,1.75)

(0,0.75)(1,1)

(1,1.25)

(1,1.5)

(0,0.5)

( , )A Sk k

= state= state ( , )A Sk k = (input, output)= (input, output)

Page 11: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 11

Example: Detection of a Sequence of Symbols Example: Detection of a Sequence of Symbols in Noise, in Noise, Trellis RepresentationTrellis Representation

k=0 k=1 k=5 k=K-2 k=K-1 k=Kk=4k=3k=2

Hypothesis: initial condition = state 00, final condition = state 00Hypothesis: initial condition = state 00, final condition = state 00

Trellis with 4 states: (0,0) (0,1) (1,0) (1,1)Trellis with 4 states: (0,0) (0,1) (1,0) (1,1)

Page 12: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 12

Example: 1 Stage of the TrellisExample: 1 Stage of the Trellisk+1kTime:Time: Ak/SkAk/Sk

States:States:

(A(Ak-1k-1, A, Ak-2k-2)) (0,0)(0,0)

(0,1)(0,1)

(1,0)(1,0)

(1,1)(1,1)

(0,0)(0,0)

(0,1)(0,1)

(1,0)(1,0)

(1,1)(1,1)

0/00/0

1/11/1

0/0.250/0.25

1/0.751/0.75

0/0.50/0.5

1/1.251/1.25

0/0.

750/

0.75

1/1.751/1.75

Page 13: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 13

Example: Detection of a Sequence of SymbolsExample: Detection of a Sequence of Symbols

Each path in the trellis corresponds to Each path in the trellis corresponds to an input sequence Ak.an input sequence Ak.

From the sequence of observations Yk, From the sequence of observations Yk, the receiver must choose among all the the receiver must choose among all the possible paths of the trellis, the path possible paths of the trellis, the path that best corresponds to the Yk for a that best corresponds to the Yk for a given criterion.given criterion.

To choose a path in the trellis, is To choose a path in the trellis, is equivalent to choose a sequence of states equivalent to choose a sequence of states kk, or of A, or of Akk or of S or of Skk..

We suppose that the criterion is a We suppose that the criterion is a quadratic distance.quadratic distance.

Page 14: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 14

Example: Detection of a Sequence of SymbolsExample: Detection of a Sequence of Symbols

min Y Sk kk

K

2

0

Choose the sequence that minimizes the total distance:Choose the sequence that minimizes the total distance:

The number of possible paths of length K in a trellis increases as The number of possible paths of length K in a trellis increases as MMKK, where M is the number of states., where M is the number of states.

The Viterbi algorithm allows to solve the problem with a The Viterbi algorithm allows to solve the problem with a complexity proportional to Kcomplexity proportional to K (not proportional to M (not proportional to MKK).).

It is derived from dynamic programming techniques (Bellman, It is derived from dynamic programming techniques (Bellman, Omura, Forney, Viterbi).Omura, Forney, Viterbi).

Page 15: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 15

Viterbi Algorithm, Basic ConceptViterbi Algorithm, Basic Concept

Let us consider the binary case: Let us consider the binary case: 2 branches arrive at each node2 branches arrive at each node 2 branches leave each node2 branches leave each node All the paths going through 1 node use one All the paths going through 1 node use one

of the 4 possible paths.of the 4 possible paths. If the best path goes through one node, If the best path goes through one node,

it will arrive by the better of the 2 it will arrive by the better of the 2 arriving branches.arriving branches.

Page 16: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 16

Viterbi Algorithm, Basic ConceptViterbi Algorithm, Basic Concept

The receiver keeps only one path, The receiver keeps only one path, among all the possible paths at the left among all the possible paths at the left of one node.of one node. This best path is called the survivor.This best path is called the survivor.

k-1 k

??

For each node the receiver stores For each node the receiver stores at time k: at time k: the cumulated distance from the the cumulated distance from the

origin to this node origin to this node the number of the surviving branch.the number of the surviving branch.

Page 17: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 17

Viterbi Algorithm: 2 Steps 1 of 3Viterbi Algorithm: 2 Steps 1 of 3

There are 2 steps in the Viterbi There are 2 steps in the Viterbi algorithmalgorithm A left to right step from k=1 to k=K in A left to right step from k=1 to k=K in

which the distance calculations are donewhich the distance calculations are done Then a right to left step called traceback Then a right to left step called traceback

that simply reads back the results from the that simply reads back the results from the trellis.trellis.

Page 18: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 18

Viterbi Algorithm: 2 steps 2 of 3Viterbi Algorithm: 2 steps 2 of 3

The left to right step from k=1 to k=K:The left to right step from k=1 to k=K: For each stage k and each node, calculate For each stage k and each node, calculate

the cumulated distance D for all the the cumulated distance D for all the branches arriving at this node.branches arriving at this node.

Distance calculations are done recursively:Distance calculations are done recursively: The cumulated distance at time k for a node i: D(k,i) The cumulated distance at time k for a node i: D(k,i)

reached by 2 branches coming from nodes m and n is reached by 2 branches coming from nodes m and n is the minimum of:the minimum of:

D(k-1,n) + d(n,i)D(k-1,n) + d(n,i) D(k-1,m) + d(m,i)D(k-1,m) + d(m,i) Where d(n,i) is the local distance on the branch from Where d(n,i) is the local distance on the branch from

node n at time k-1 to node i at time k.node n at time k-1 to node i at time k. d(n,i)=(Yk-Sk(n,i))d(n,i)=(Yk-Sk(n,i))22 where Sk(n,i) is the output when where Sk(n,i) is the output when

going from node n to node i.going from node n to node i.

k

??

ii

nn

mm

k-1

Page 19: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 19

Viterbi Algorithm: 2 steps 3 of 3Viterbi Algorithm: 2 steps 3 of 3

At the end of the first step:At the end of the first step: The receiver has an array of size KxM The receiver has an array of size KxM

containing for each node at each stage the containing for each node at each stage the number of the survivor,number of the survivor,

and the set of values=cumulated distances and the set of values=cumulated distances from the origin to each node of the last from the origin to each node of the last stage.stage.

The second step is called The second step is called traceback.traceback. It is simply the reading of the best path It is simply the reading of the best path

from the right to the left of the trellis.from the right to the left of the trellis. The best path arrives at the best final node, The best path arrives at the best final node,

so we just have to start from it and read the so we just have to start from it and read the array of survivors from node to node until array of survivors from node to node until the origin is reached.the origin is reached.

Page 20: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 20

Application of Viterbi Algorithm to the Application of Viterbi Algorithm to the Example of Sequence DetectionExample of Sequence Detection

Hypothesis: start from state 0Hypothesis: start from state 0

k=0 k=1

Y1=0.2

0.04

0.64

0.04

0.64

Local distances are written in greenLocal distances are written in green

Cumulative distances are written in orange.Cumulative distances are written in orange.

Yk are written in blue.Yk are written in blue.

Page 21: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 21

Application of Viterbi Algorithm to the Application of Viterbi Algorithm to the Example of Sequence DetectionExample of Sequence Detection

k=0 k=1 k=2

0.2 0.7

0.04

0.64

0.49

0.09

0.64

0.04

0.53

0.68

0.13

1.28

There is survivor choice to be made during this initialization step.There is survivor choice to be made during this initialization step.

Page 22: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 22

Application of Viterbi Algorithm to the Application of Viterbi Algorithm to the Example of Sequence DetectionExample of Sequence Detection

First survivor choiceFirst survivor choice

0.53

0.68

0.13

0.36

1.8225

0.1225

1.21

0.01

0.7225

0.0225

2.5025=min( 0.53+2.56,0.68+1.8225)

0.04

0.64

1.28

2.56

1.61.60.70.70.20.2

1.34=min( 0.13+1.21,1.28+0.7225)

0.8025=min( 0.53+0.36,0.68+0.1225)

0.14=min( 0.13+0.01,1.28+0.0225)

Page 23: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 23

Application of Viterbi Algorithm to the Application of Viterbi Algorithm to the Example of Sequence DetectionExample of Sequence Detection

Selection of survivorsSelection of survivors

0.53

0.68

0.13

2.5025

1.34

0.8025

0.04

0.64

0.14

Page 24: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 24

Next stage from k= 3 to k=4Next stage from k= 3 to k=4

Application of Viterbi Algorithm to the Application of Viterbi Algorithm to the Example of Sequence DetectionExample of Sequence Detection

2.5025

1.34

0.8025

0.14

1.44

0.04

0.925

0.0025

0.49

0.09

0.2025

0.3025

2.265

0.3425

1.3425

0.4425

1.21.21.61.6

Page 25: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 25

TracebackTraceback

Application of Viterbi Algorithm to the Application of Viterbi Algorithm to the Example of Sequence DetectionExample of Sequence Detection

0.3425

1.3425

0.4425

2.265

'0' '1' '1' '0'

Best path in yellowBest path in yellow

Page 26: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 26

Convolutional Coding (GSM Example)Convolutional Coding (GSM Example)

input bitStream b

K = Constraint Length = 5

+

+

R = Coding Rate = 0.5

G0(D) = 1 + D3 + D4

G1(D) = 1 + D + D3 + D4

noted in octal 23 and 33

G0

G1

z-1 z-1 z-1 z-1

output bitStream: 2 output bits for 1 input bit

Page 27: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 27

Convolutional Coding (GSM Example)Convolutional Coding (GSM Example)

Time t

State 2J

b3 b2 b1 0

State 2J+1

b3 b2 b1 1

Time t+1

State J

State J+8

1 b3 b2 b1

b3 b2 b10

Page 28: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 28

Convolutional Coding (GSM Example)Convolutional Coding (GSM Example)

J = 0 b3 b2 b1

J+8 = 1 b3 b2 b1

2J = b3 b2 b1 0

2J+1 = b3 b2 b1 1

k=0k=0 k=1k=1 k=2k=2 k=3k=3

Page 29: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 29

Convolutional DecodingConvolutional DecodingHard or Soft DecisionHard or Soft Decision

Hard decisionHard decision: data represented by a single bit => Hamming distance: data represented by a single bit => Hamming distance Soft decisionSoft decision: data represented by several bits => Euclidian or probabilistic distance: data represented by several bits => Euclidian or probabilistic distance

Example 3 bits quantized valuesExample 3 bits quantized values 011=most confidence value 011=most confidence value 111=less conf. neg. value111=less conf. neg. value 010010 110110 001001 101101 000=Less conf. pos. value000=Less conf. pos. value100=most conf. neg. val.100=most conf. neg. val.

For the GSM coding example, at each new step n, the receiver receives 2 hard or soft For the GSM coding example, at each new step n, the receiver receives 2 hard or soft values.values. Soft decision values will be noted SDSoft decision values will be noted SD00 and SD and SD11

Page 30: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 30

Evaluation of the Local Distance Evaluation of the Local Distance for Soft Decoding with R=0.5for Soft Decoding with R=0.5

SDSDnn = soft decision value = soft decision value GGnn(j) = expected bit value(j) = expected bit value

1

n nn 0

dist_loc( j) SD G ( j)

12

n nn 0

12 2n n n n

n 0

d( j) SD G ( j)

d( j) SD G ( j) 2SD G ( j)

Page 31: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 31

Evaluation of the Local DistanceEvaluation of the Local Distancefor Soft Decoding (cont.)for Soft Decoding (cont.)

1 12 2n n

n 0 n 0

SD and G ( j)

are the same for all possible paths (2 here)

1

n nn 0

dist_loc( j) SD G ( j)

Page 32: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 32

Evaluation of the Local DistanceEvaluation of the Local Distancefor Soft Decoding R=0.5for Soft Decoding R=0.5

dist_loc(j)=SDdist_loc(j)=SD00GG00(j)+SD(j)+SD11GG11(j)(j) 4 possible values (24 possible values (21/R1/R) :) :

d = SDd = SD0 0 + SD+ SD11

d’ = SDd’ = SD0 0 - SD- SD11

- d- d - d’- d’

Use of symmetryUse of symmetry Only 2 distances are calculatedOnly 2 distances are calculated Paths leading to the same state are complementaryPaths leading to the same state are complementary

Maximize distance instead of minimize because of Maximize distance instead of minimize because of the minus sign.the minus sign.

Page 33: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 33

Calculation of Accumulated Distances Calculation of Accumulated Distances using Butterfly Structureusing Butterfly Structure

One butterfly: 2 starting and ending states (joined by One butterfly: 2 starting and ending states (joined by the paths) are paired in a butterfly. the paths) are paired in a butterfly. For R=0.5 , state 2J and 2J+1 with J and J+8For R=0.5 , state 2J and 2J+1 with J and J+8

Symmetry is used to simplify calculationsSymmetry is used to simplify calculations One local_distance per butterfly is usedOne local_distance per butterfly is used Old possible metric values are the same for both new states => Old possible metric values are the same for both new states =>

minimum address manipulationsminimum address manipulations

Page 34: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 34

Butterfly Structure of the Trellis Diagram, Butterfly Structure of the Trellis Diagram, GSM ExampleGSM Example

G D D D

G D D D D

0 1

1 1

3 4

3 4

( )

( )

Old stateLocal distance d

d

-d

-d

New state

2J

2J+1

J

J+8

Soft decision values: SD0, SD1Soft decision values: SD0, SD1

Page 35: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 35

Implementation on C54x Implementation on C54x

To implement the Viterbi algorithm on To implement the Viterbi algorithm on C54x we need:C54x we need: Compare store and Select UnitCompare store and Select Unit One AccumulatorOne Accumulator Specific instructionsSpecific instructions

DADSTDADST Double-Precision Load With T Add orDouble-Precision Load With T Add or Dual 16-Bit Load With T Add/Subtract)Dual 16-Bit Load With T Add/Subtract)

DSADTDSADT Long-Word LoadLong-Word Load With T Add orWith T Add or Dual 16-Bit Load With T Subtract/Add)Dual 16-Bit Load With T Subtract/Add)

CMPS (Compare Select Store)CMPS (Compare Select Store)

Page 36: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 36

CSSU Compare Store and Select UnitCSSU Compare Store and Select Unit

Dual 16-bit ALU operations

T register input ALU as dual 16-bit operand

16-bit transition shift register (TRN)

One cycle store Max and Shift decision

=MUX=MUX

T

EB [15:0]

DB [15:0]CB [15:0]

TRN

TC

CS

S U

NIT

C16=1 ALU

32

16COMP

MSB/LSBMSB/LSBWRITEWRITESELECTSELECT

BH BLAH AL

Page 37: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 37

Structure of Viterbi Decoding ProgramStructure of Viterbi Decoding Program

InitializationInitialization Metric updateMetric update

In one symbol interval:In one symbol interval: 8 butterflies yield 16 new states.8 butterflies yield 16 new states.

This operation repeats over a number of symbol time intervalsThis operation repeats over a number of symbol time intervals TracebackTraceback

Page 38: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 38

Viterbi Instructions Viterbi Instructions CMPS, DADST, DSADTCMPS, DADST, DSADT

DADST Lmem,dst

DSADT Lmem,dst

Lmem ( 31-16 ) + (T) dst (39-16) Lmem ( 15 - 0 ) - (T) dst (15 - 0)

Lmem ( 31-16 ) - (T) dst (39-16)Lmem ( 15 - 0 ) + (T) dst (15 - 0)

C16 = 1C16 = 1

CMPS src, Smem

THEN :THEN :

(src(31-16)) (src(31-16)) Smem Smem

0 0 TC TC

(TRN << 1 ) + 0 (TRN << 1 ) + 0 TRN TRN

ELSE :ELSE :

(src(15-0)) (src(15-0)) Smem Smem

1 1 TC TC

(TRN << 1 ) + 1 (TRN << 1 ) + 1 TRN TRN

IF { [ src (31-16) ] > [ src (15-0) ] }

Page 39: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 39

DADST, DSADTDADST, DSADT

DSADT Lmem, dst; DSADT Lmem, dst; Lmem 32-bit operandLmem 32-bit operand

C16=1, ALU dual 16-bit operationsC16=1, ALU dual 16-bit operations, 2 additions or , 2 additions or subtractions in 1 cyclesubtractions in 1 cycle

C16=0, ALU standard mode, single operation C16=0, ALU standard mode, single operation double precisiondouble precision

C16=1C16=1 1 addition and 1 subtraction using the T register1 addition and 1 subtraction using the T register

C16=0, not of interest for ViterbiC16=0, not of interest for Viterbi DADST: dst=Lmem + (T+T<<16)DADST: dst=Lmem + (T+T<<16) DSADT: dst=Lmem - (T+T<<16)DSADT: dst=Lmem - (T+T<<16)

Page 40: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

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ESIEE, Slide 40

Viterbi Algorithm (VA) InitializationViterbi Algorithm (VA) Initialization

Processing modeProcessing mode SXM = 1SXM = 1 C16 =1 (Dual 16 bits Accumulator)C16 =1 (Dual 16 bits Accumulator)

Buffer pointersBuffer pointers Input, output buffers, transition table, Metric storage (circular buffer set Input, output buffers, transition table, Metric storage (circular buffer set

and enabled)and enabled) Initialization of metric valuesInitialization of metric values Block repeat counter = number of output bits -1Block repeat counter = number of output bits -1

Page 41: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

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ESIEE, Slide 41

VA Initialization (cont.)VA Initialization (cont.)

FR = Frame length in coded bitsFR = Frame length in coded bits Input buffer size = FR/RInput buffer size = FR/R Output buffer size = FS (packed in FS/16)Output buffer size = FS (packed in FS/16) Transition table size = 2Transition table size = 2K-1K-1FS/16FS/16 Metric storage = 2 buffers of size 2Metric storage = 2 buffers of size 2K-1 K-1 configured configured

in one circular buffer:in one circular buffer: Buffer size 2 x 2Buffer size 2 x 2K-1K-1. Register BK initialized at 2 x 2. Register BK initialized at 2 x 2K-1K-1

index pointer AR0=index pointer AR0= 22K-2K-2 + 1 + 1 All states except starting one 0 are set to the All states except starting one 0 are set to the

same metric value 8000hsame metric value 8000h

Page 42: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

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ESIEE, Slide 42

VA Metric UpdateVA Metric UpdateLoop for all Symbol IntervalsLoop for all Symbol Intervals

Calculate local distance between input and Calculate local distance between input and each possible path. For R=0.5, only 2 valueseach possible path. For R=0.5, only 2 values LD LD *AR1+,16,A*AR1+,16,A

;A=SD0(2i);A=SD0(2i) SUB SUB *AR1,16,A,B*AR1,16,A,B ;B=SD0(2i)-;B=SD0(2i)-

SD1(2i+1)SD1(2i+1) STHSTH B,*AR2+B,*AR2+

;tmp(0)=difference;tmp(0)=difference ADDADD *AR1+,16,A,B*AR1+,16,A,B ;B=SD0(2i);B=SD0(2i)

+SD1(2i+1)+SD1(2i+1) STHSTH B,*AR2B,*AR2 ;tmp(1)=sum;tmp(1)=sum

Page 43: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

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ESIEE, Slide 43

VA Metric Update (cont.)VA Metric Update (cont.)

Accumulate total distance for each stateAccumulate total distance for each state Using the split ALU, the C54x accumulates metrics for 2 paths Using the split ALU, the C54x accumulates metrics for 2 paths

in 1 cycle (if local dist in T) with DADST and DSADT.in 1 cycle (if local dist in T) with DADST and DSADT. Select and save minimum distanceSelect and save minimum distance Save indication of chosen pathSave indication of chosen path

The 2 last steps can be done in one cycle using CMPS The 2 last steps can be done in one cycle using CMPS (Compare Select Store) on the CSSU.(Compare Select Store) on the CSSU.

Page 44: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

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ESIEE, Slide 44

CMPS InstructionCMPS Instruction

Compare the 2 16-bit signed values in the Compare the 2 16-bit signed values in the upper and lower part of ACCUupper and lower part of ACCU

Store the maximum in memoryStore the maximum in memory Indicate the maximum by setting TC and Indicate the maximum by setting TC and

shifting this TC value in the transition shifting this TC value in the transition register TRN.register TRN.

Page 45: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

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ESIEE, Slide 45

VA Metric UpdateVA Metric Updateuse of Buffersuse of Buffers

Old metrics accessed in consecutive orderOld metrics accessed in consecutive order One pointer for addressing 2One pointer for addressing 2K-1K-1 words. words.

New metric accessed in order : New metric accessed in order : 0, 20, 2K-2K-2, 1, 2, 1, 2K-2K-2+1, 2, 2+1, 2, 2K-2K-2+2 ...+2 ... 2 pointers for addressing.2 pointers for addressing.

At the end, both buffers are swappedAt the end, both buffers are swapped The transition register TRN (16bits) must be saved every 8 butterflies (2 The transition register TRN (16bits) must be saved every 8 butterflies (2

bits per butterfly).bits per butterfly).

Page 46: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

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ESIEE, Slide 46

Viterbi Memory MapViterbi Memory Map

AR2 points on local distance and

AR1 to buffer of Soft Decision bits SD0 and SD1

Metrics 2*J & 2*J+1

Metrics J

Metrics J + 8

AR5

AR4

AR3

0

15 16

24

31

Relative location

Old states

New states

Page 47: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

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ESIEE, Slide 47

Metric Update Operations for 1 Symbol Metric Update Operations for 1 Symbol Interval with 16 StatesInterval with 16 States

Calculate local distanceCalculate local distance tmp(0)=diff, tmp(1)=sumtmp(0)=diff, tmp(1)=sum

Load T register Load T register T=tmp(1)T=tmp(1) Then 8 butterflies per symbol interval Then 8 butterflies per symbol interval

Direct butterflies = BFLY_DIR or Direct butterflies = BFLY_DIR or Reverse butterflies = BFLY_REVReverse butterflies = BFLY_REV

T is loaded with tmp(0)=diff after the 4T is loaded with tmp(0)=diff after the 4thth butterfly.butterfly.

Page 48: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

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ESIEE, Slide 48

Code for the Metric UpdateCode for the Metric Updatein a Direct Butterflyin a Direct Butterfly

LDLD *AR2 T*AR2 T ;load d in T;load d in T DADSTDADST *AR5,A*AR5,A ;D;D2J2J+d and D+d and D2J+12J+1-d-d DSADTDSADT *AR5+,B*AR5+,B ;D;D2J2J-d and D-d and D2J+12J+1+d+d CMPSCMPS A,*AR4+A,*AR4+ ;compares the distances ;compares the distances

ofof ;the 2 paths arriving at ;the 2 paths arriving at

JJ ;stores the ;stores the

best.TRN=TRN<<1.best.TRN=TRN<<1. ;TRN(0)=1 if D;TRN(0)=1 if D2J2J+M < D+M < D2J+12J+1--

M,M, ;TRN(0)=0 if D;TRN(0)=0 if D2J2J+M > D+M > D2J+12J+1--

MM CMPSCMPS B,*AR3+ B,*AR3+ ;;compares the distances compares the distances

ofof ;2 paths arriving at ;2 paths arriving at

J+2J+2(K-2),(K-2),

;stores the ;stores the best.TRN=TRN<<1.best.TRN=TRN<<1.

; TRN(0)=1 si D; TRN(0)=1 si D2J2J-M < -M < DD2J+12J+1+M,+M,

; TRN(0)=0 si D; TRN(0)=0 si D2J2J-M > -M > DD2J+12J+1+M+M

Page 49: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

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ESIEE, Slide 49

Metric Update Operations (cont.)Metric Update Operations (cont.)

1st butterfly BFLY_DIR1st butterfly BFLY_DIR New(0) = max(old(0)+sum, old(1)-sum)New(0) = max(old(0)+sum, old(1)-sum) New(8) = max(old(0)-sum, old(1)+sum)New(8) = max(old(0)-sum, old(1)+sum) TRN=xxxx xxxx xxxx xx08TRN=xxxx xxxx xxxx xx08

2nd butterfly BFLY_REV 2nd butterfly BFLY_REV New(1) = max(old(2)-sum, old(3)+sum)New(1) = max(old(2)-sum, old(3)+sum) New(9) = max(old(2)+sum, old(3)-sum)New(9) = max(old(2)+sum, old(3)-sum) TRN=xxxx xxxx xxxx 0819TRN=xxxx xxxx xxxx 0819

3rd butterfly BFLY_DIR 3rd butterfly BFLY_DIR new(2), new (10) from old(4), old(5)new(2), new (10) from old(4), old(5)

4th butterfly BFLY_REV4th butterfly BFLY_REV new(3), new (11) from old(5), old(6)new(3), new (11) from old(5), old(6)

Page 50: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

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ESIEE, Slide 50

Metric Update Operations (cont.)Metric Update Operations (cont.)

Load T register T = tmp(0)Load T register T = tmp(0) 5 th butterfly BFLY_DIR 5 th butterfly BFLY_DIR

new(4), new (12) from old(8), old(9)new(4), new (12) from old(8), old(9) 6 th butterfly BFLY_REV6 th butterfly BFLY_REV

new(5),new (13) from old(10),old(11)new(5),new (13) from old(10),old(11) 7 th butterfly BFLY_DIR 7 th butterfly BFLY_DIR

new(6),new (14) from old(12),old(13)new(6),new (14) from old(12),old(13) 8th butterfly BFLY_REV8th butterfly BFLY_REV

new(7),new (15) from old(14),old(15)new(7),new (15) from old(14),old(15) Store Store TRN = 0819 2A3B 4C5D 6E7FTRN = 0819 2A3B 4C5D 6E7F

Page 51: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

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ESIEE, Slide 51

Metric Update Operations (cont.)Metric Update Operations (cont.)

Update of metrics buffer pointers for next Update of metrics buffer pointers for next symbol interval :symbol interval : As metric buffers are set up in circular As metric buffers are set up in circular

buffer, no overhead.buffer, no overhead. Use Use *ARn+0%*ARn+0% in the last butterfly (AR0 was in the last butterfly (AR0 was

initialized with 2initialized with 2(K-2)(K-2)+1 = 9+1 = 9 Note long word incrementing Lmem: *ARn+Note long word incrementing Lmem: *ARn+

The transition data buffer pointer is The transition data buffer pointer is incremented by 1 (each TRN is a 16-bit incremented by 1 (each TRN is a 16-bit word)word)

Page 52: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

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ESIEE, Slide 52

VA Traceback FunctionVA Traceback Function Trace the maximum likelihood path backward through the trellis to obtain Trace the maximum likelihood path backward through the trellis to obtain

N bits.N bits. Final state known (by insertion of tail bits in the emitter) or estimated (best Final state known (by insertion of tail bits in the emitter) or estimated (best

final metric).final metric). In the transition buffer :In the transition buffer :

1 = previous state is the lower path1 = previous state is the lower path 0 = previous state is the upper path0 = previous state is the upper path

Previous state is obtained by shifting transition value in the LSB of the statePrevious state is obtained by shifting transition value in the LSB of the state

Time t+1

b3 b2 State Jb1

1 b3 b2 State J+8b1

0

Time t

b3 b2 b1State 2J 0

b3 b2 b1 1

TRN bitTRN bit

State 2J+1

Page 53: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

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ESIEE, Slide 53

VA Traceback Function (cont.)VA Traceback Function (cont.)

The data sequence is obtained from the The data sequence is obtained from the reconstructed sequence of states. reconstructed sequence of states. (MSB).(MSB).

The data sequence is (often) in reversed The data sequence is (often) in reversed order. order.

Page 54: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

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ESIEE, Slide 54

VA Traceback Function (cont.)VA Traceback Function (cont.)Transition Data BufferTransition Data Buffer

The transition data buffer has:The transition data buffer has: 22K-5K-5 transition words for each symbol interval. transition words for each symbol interval. For N trellis stages or symbol intervals, there are For N trellis stages or symbol intervals, there are

N 2N 2K-5K-5 words in the transition data buffer. words in the transition data buffer. For GSM, 2For GSM, 2K-5K-5 = 1. = 1.

Stored transition data are scrambled.Stored transition data are scrambled. E.g. GSM, 1 trans. Word/stage, state E.g. GSM, 1 trans. Word/stage, state

ordering:ordering: (MSB) 0819 2A3B 4C5D 6E7F (LSB)(MSB) 0819 2A3B 4C5D 6E7F (LSB)

Calculate position of the current state in the Calculate position of the current state in the transition data buffer for each symbol transition data buffer for each symbol interval.interval.

Page 55: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

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ESIEE, Slide 55

VA Traceback: Find the Word to Read in the VA Traceback: Find the Word to Read in the Transition Data BufferTransition Data Buffer

For a given node j at time t, find the correct For a given node j at time t, find the correct transition word and the correct bit in that transition word and the correct bit in that word.word. For the GSM example there is only 1 transition For the GSM example there is only 1 transition

word per symbol interval. word per symbol interval. In the general case, there are 2In the general case, there are 2K-5K-5 transition words transition words

and if the state number is written in binary:and if the state number is written in binary: j = bj = bK-2K-2 … b … b33 b b22 b b11 b b0, 0,

The number of the transition word for node j is obtained The number of the transition word for node j is obtained by setting MSB of j to 0 and shifting the result 3 bits to the by setting MSB of j to 0 and shifting the result 3 bits to the right.right.

Trn_Word_number(j) = bTrn_Word_number(j) = bK-2K-2 … b … b44 b b3, 3,

Page 56: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

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ESIEE, Slide 56

VA Traceback: Find Bit to read in the VA Traceback: Find Bit to read in the Correct Word of the Transition Data BufferCorrect Word of the Transition Data Buffer

Find the number of the correct bit in the Find the number of the correct bit in the transition word. transition word.

Number 0 = MSB, number 15 = LSB.Number 0 = MSB, number 15 = LSB.

If state number j = bIf state number j = bK-2K-2 b b33 b b22 b b11 b b00 in in binary,binary, Bit number (Bit#) in the in the transition Bit number (Bit#) in the in the transition

word is:word is: Bit # = Bit # = bb33 b b22 b b11 b b00 b bK-2 K-2 (for the GSM (for the GSM

example)example) Bit# = 2 x state +(state >> (K-2))&1Bit# = 2 x state +(state >> (K-2))&1 Bit# = 2 x state + MSB(state)Bit# = 2 x state + MSB(state)

This bit number (in fact 15-Bit#) is This bit number (in fact 15-Bit#) is loaded in T for next step.loaded in T for next step.

Page 57: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

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ESIEE, Slide 57

VA Traceback: Determine Preceding NodeVA Traceback: Determine Preceding Node

Read and test selected bit to determine the Read and test selected bit to determine the state in the preceding symbol interval t-1,state in the preceding symbol interval t-1, Instruction Instruction BITTBITT copy this bit in TC. copy this bit in TC. Set up Address in the transition buffer for next Set up Address in the transition buffer for next

iteration.iteration. Instruction Instruction BITTBITT (Test Bit Specified by T) (Test Bit Specified by T)

Tests bit n° 15-T(3-0)Tests bit n° 15-T(3-0) Update node value with new bitUpdate node value with new bit

New state obtained with inst. New state obtained with inst. ROLTCROLTC:: ROLTCROLTC shifts ACCU 1 bit left and shifts TC bit shifts ACCU 1 bit left and shifts TC bit

into the ACCU LSB.into the ACCU LSB. So if j = bSo if j = bK-2K-2 b b33 b b22 b b11 and transition bit = TC and transition bit = TC

The precedent node has number: bThe precedent node has number: b33 b b22 b b11 TC (for GSM) TC (for GSM)

Page 58: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

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ESIEE, Slide 58

VA Traceback Function (cont.)VA Traceback Function (cont.)

Traceback algorithm is implemented in Traceback algorithm is implemented in a loop of 16 stepsa loop of 16 steps The single decoded bits are packed in 16-The single decoded bits are packed in 16-

bits wordsbits words Bit reverse orderingBit reverse ordering

Page 59: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

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ESIEE, Slide 59

VA Traceback RoutineVA Traceback Routine A = state valueA = state value B = tmp storageB = tmp storage K = constraint lengthK = constraint length MASK = 2MASK = 2(K-5)(K-5)-1-1 ONE=1ONE=1 Final state is assumed to be 0Final state is assumed to be 0 AR2 points on the transition data bufferAR2 points on the transition data buffer TRANS_END=end address of trans. bufferTRANS_END=end address of trans. buffer AR3 points on the output bit bufferAR3 points on the output bit buffer OUTPUT = address of the output bit bufferOUTPUT = address of the output bit buffer NBWORDS = Nb of words of output buffer NBWORDS = Nb of words of output buffer

packed by packs of 16 bits.packed by packs of 16 bits.

Page 60: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

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ESIEE, Slide 60

VA Traceback Routine: InitializationVA Traceback Routine: Initialization

RSBXRSBX OVMOVM STMSTM #TRANS_END,AR2#TRANS_END,AR2 STMSTM #NBWORDS-1,AR1#NBWORDS-1,AR1 MVMMMVMM AR1, AR4AR1, AR4 STMSTM #OUTPUT+NBWORD-1,AR3#OUTPUT+NBWORD-1,AR3 LDLD #0,A#0,A ;init state = 0 here;init state = 0 here STMSTM #15,BRC#15,BRC ;for loop i;for loop i

Page 61: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

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VA Traceback Routine (cont.)VA Traceback Routine (cont.) backback RPTBRPTB TBEND-1TBEND-1 ;loop j=1 to 16;loop j=1 to 16 SFTLSFTL A,-(K-2),BA,-(K-2),B ANDAND ONE,BONE,B ADDADD A,1,BA,1,B ;add MSB;add MSB STLM STLM B,TB,T ;T=bit pos;T=bit pos MARMAR *+AR2(-2^(K-5))*+AR2(-2^(K-5)) BITT BITT *AR2*AR2 ROLTCROLTC A A TBENDTBEND STLSTL A,*AR3-A,*AR3- BANZDBANZD BACK,*AR1-BACK,*AR1- STMSTM #15,BRC#15,BRC ; end i; end i

Page 62: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

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ESIEE, Slide 62

VA Traceback Routine: Reverse Order of VA Traceback Routine: Reverse Order of BitsBits

MARMAR *AR3+*AR3+ ; start ; start outputoutput

LDLD *AR3, A*AR3, A RVSRVS SFTASFTA A,-1,A A,-1,A ;A>>1, C=A(0);A>>1, C=A(0) STMSTM #15,BRC#15,BRC RPTBRPTB RVS2-1RVS2-1 ROLROL BB ;B<<1, B(0)=C;B<<1, B(0)=C SFTASFTA A,-1,AA,-1,A ;A>>1, C=A(0);A>>1, C=A(0) RSV2RSV2 BANZDBANZD RVS,*AR4- RVS,*AR4- STLSTL B,*AR3+ B,*AR3+ ;save compl. word ;save compl. word LDLD *AR3,A*AR3,A ;load next word;load next word

Page 63: DSP C5000 Chapter 22 Implementation of Viterbi Algorithm/Convolutional Coding Copyright © 2003 Texas Instruments. All rights reserved.

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ESIEE, Slide 63

Additional ResourcesAdditional Resources

H. Hendrix, “Viterbi Decoding Techniques on the TMS320C54x Family”, Texas-Instruments spra071.pdf, June 1996.

Internet: Search on “Tutorial on Convolutional Coding with Viterbi Decoding”.