Designingenergyeﬃcient’ microprocessor:Howtoﬁght ... Memory ... [MHz] 8086 80286 386DX 486DX 486DX4 Pentium Pentium Pro Pentium II Pentium MMX Pentium III ... Delay buffers are

Designing energy-‐‑efficient microprocessor: How to fight

process variations Ruzica Jevtic

Berkeley Wireless Research Center

Moore’s law

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100100

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nmnm130nm130nm90nm90nm

70nm70nm50nm50nm

Gate LengthGate Length 65nm65nm45nm45nm

32nm32nm22nm22nm

0.7X every 2 years

180nm180nm250nm250nm

3=Source: Intel, IEDM presentations

10100.010.01

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Scaling consequences: •  Process variations •  Power has become critical!

(c) Ruzica Jevtic 2012

Scaling consequences

•  Fabrication: - Litography with liquids

- Use of difraction…

•  Consequences: - Random dopant fluctuations - Hot-carrier trapping…

•  Additional steps: - Optical Proximity Check

•  Design rules: - No corners - One direction lines…

J. Hartmann, ISSCC 2007 (c) Ruzica Jevtic 2012

11

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mm

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nmnm

130nm130nm90nm90nm

65nm65nm



193nm193nm

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10100.010.0119701970 19801980 19901990 20002000 20102010 20202020

45nm45nm32nm32nm

22nm22nm EUV 13nmEUV 13nm

567*8 9#)-'.4./1*.:*"-#*:;";0#*<:.0#=#0>?

Litography

•  Litography issues: 193nm wavelength for

lines as small as 30nm!

12

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193nm lightMask

193nm light

Lightintensity

Lightintensity

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1CD kNA

:(62(&;(.Presently: 193 nm (ArF excimer laser)(Distant?) future: EUV

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1930.25 50

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Presently: 0.92-1.35Immersion

?(;"),@.!-20*A0*+.ABPresently: 0.35 – 0.4Theoretical limit: 0.25

0.92NA

45nm technology beyond resolution limit


Process variations

•  Process corners: typical, fast and slow •  All corners coexist on the same wafer •  If we design for the worst case, it is too pessimistic! •  Need to know after fab chip features observation circuits

B. Nikolic, TCAS-‐‑I, 2011


Moore’s law

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2--22--21965 Data (Moore)1965 Data (Moore)

MicroprocessorMicroprocessorMemoryMemory

19601960 19651965 19701970 19751975 19801980 19851985 19901990 19951995 20002000 20052005 20102010

Source: IntelSource: IntelGraph from S.Chou, ISSCC’2005

!""#$%&'A)*')8B'6"&9

,-

13

!"#$%&'()*+,-./0+12

34

)*01/-5(627()8920.:;(<:/-10000100001010

Nominal feature sizeNominal feature size

mm

10001000

100100

11

0.10.1

nmnm130nm130nm90nm90nm

70nm70nm50nm50nm

Gate LengthGate Length 65nm65nm45nm45nm

32nm32nm22nm22nm

0.7X every 2 years


3=Source: Intel, IEDM presentations

10100.010.01

50nm50nm35nm35nm

19701970 19801980 19901990 20002000 20102010 20202020

~30nm~30nm

)8920.:;(>:/-(;-1>/8(?(1+@01:;(A-:/B*-(20C-(:A/-*(331@D

Scaling consequences: •  Process variations •  Power has become critical!


Scaling issues: Power

•  Operating voltage scaled to avoid device breakdown •  Not scaled enough to keep the performance boosting up

•  Power has become a critical design constraint

3

Frequency Trends in Intel's Microprocessors

10000Pentium 4 Core2

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Power issues •  Power became an issue before variations: - battery life for mobile devices

- power limits performance! - performance is what sells the product!

•  Power classification: - Dynamic power (60%)

- Static power (30%) exp(Vdd)

P = sw ! f !Vdd2 !C


Power-‐‑performance trade-‐‑offs •  The best way to reduce power (both leakage and

active) is to reduce the power supply

•  How to maintain throughput under reduced supply?

•  Introducing more parallelism/pipelining •  Dynamic voltage scaling with variable throughput

Energy

Performance (c) Ruzica Jevtic 2012

Overview

•  Dynamic voltage and frequency scaling

•  Control voltage through DC-DC converters •  Conclusions

•  Error detection and correction circuits


Impact of Dynamic Variations

MSFF D

CLK

Q MSFF

CLK

VCC Droop

CLK

D

D

Setup Time Timing with VCC Droop

Timing with Nominal VCC

Timing Guardband

Ø Guardbands required to ensure correct operation within the presence of dynamic variations

K. Bowman, CMOS Emerging Tech. Workshop, 2009 (c) Ruzica Jevtic 2012

Timing-‐‑Error Detection Error-‐‑Detection Sequential (EDS)

D

CLK

Q

ERROR

MSFF

LATCH

MSFF

CLK

VCC Droop

CLK

D

ERROR

Data Arrives Late

Error Detected

[1] P. Franco, et al., VLSI Test Symp., 1994. [2] M. Nicolaidis, VLSI Test Symp., 1999. [3] D. Ernst, et al., MICRO, 2003.

RAZOR


Recovery mechanism DAS et al.: A SELF-TUNING DVS PROCESSOR USING DELAY-ERROR DETECTION AND CORRECTION 795

Fig. 3. Distributed pipeline recovery mechanism.

corrupting the state of the shadow latch. Delay buffers are re-quired to be inserted in those paths which fail to meet this min-imum path delay constraint imposed by the shadow latch. Theinsertion of delay buffers incurs power overhead because ofthe extra capacitance added. A large shadow latch samplingdelay requires a greater number of delay buffers to be inserted,thereby increasing the power overhead. However, a small sam-pling delay implies that the voltage difference between the pointof first failure and the point where shadow latch fails is less and,thus, reduces the voltage margin available through Razor timingspeculation. Hence, the shadow latch sampling delay representsthe tradeoff between power overhead due to delay buffers andthe voltage margin available for Razor subcritical mode of op-eration. Using suitable clock chopping techniques, the durationof the positive phase of the propagated clock can be configuredas required so as to exploit the above tradeoff.

A key point to note is the fact that the hold constraint im-posed by the shadow latch only limits the maximum durationof the positive clock phase and has no bearing upon the clockfrequency. Thus, a “Razor”-ed pipeline can still be operated atany frequency as required as long as the positive clock phase issufficient to meet the minimum path delay constraint. In our de-sign, for a sampling delay of 3.0 ns which is approximately halfthe cycle time at 140 MHz, it was required to add 2388 delaybuffers to satisfy the short path constraint on 207 RFFs (7.4%of the total number of flip-flops). The power overhead due tothese buffers was less than 3% of the nominal chip power.

Correct pipeline state is recovered in the event of a timingerror by engaging a distributed pipeline recovery mechanism, asdescribed in [1], which is based on a counter-flow pipeline archi-tecture [9]. The primary requirement of the recovery mechanismis to prevent corrupt state being committed to storage in memoryor the register file before being validated by Razor. In [1], wehave discussed two possible ways in which this can be achieved.A centralized pipeline recovery mechanism uses thesignal as a global clock-gating signal to stall the pipeline fora single cycle while the errant flip-flop recovers correct state.This incurs only a one-cycle recovery penalty but imposes sig-nificant timing restrictions on the signal which needsto be distributed through the entire chip in less than one cycle.In contrast, the distributed pipeline recovery mechanism placesnegligible restrictions on the cycle time at the expense of ex-tending recovery over several cycles.

Fig. 3 conceptually illustrates the working principle of thedistributed pipeline recovery mechanism. When a Razor erroroccurs, two actions are taken. First, the computation in the stage

following the errant stage is nullified by a “bubble” signal whichindicates to the next and subsequent stages that the pipeline slotis invalid. Second, a backward propagating flush train is trig-gered by asserting the stage identifier (ID) of the failing stage.In the following cycle, the correct value from the Razor shadowlatch data is injected back into the pipeline, allowing the errantinstruction to continue with its correct inputs. In addition, theflush train begins propagating the ID of the failing stage in theopposite direction of instructions. At each stage, the flush traininserts a bubble in the corresponding pipeline stage as well as inthe immediately preceding stage. (Two stages must be nullifiedbecause the main pipeline appears to move twice as fast rela-tive to the flush train.) When the flush ID reaches the start of thepipeline, the flush control logic restarts the pipeline at the in-struction following the errant instruction. In the event that mul-tiple stages experience errors in the same cycle, all will initiaterecovery but only the Razor error closest to write-back (WB)will complete. Earlier recoveries will be flushed by later ones.

III. TRANSISTOR-LEVEL DESIGN OF THE RFF

Fig. 4 shows the transistor level circuit schematic of the RFF.In the absence of a timing error, the RFF behaves as a standardpositive edge triggered flip-flop. The error comparator is a semi-dynamic XOR gate which evaluates when the data latched by theslave differs from that of the shadow in the negative clock phase.The error comparator shares its dynamic node with themetastability detector which evaluates in the positive phase ofthe clock when the slave output could become metastable. Thus,the RFF signal is flagged when either the metastabilitydetector or the comparator evaluate.

This, in turn, evaluates the dynamic gate to generate thesignal by ORing together the error signals of indi-

vidual RFFs (Fig. 5), in the negative clock phase. Thesignal incurs significant routing and gate capacitance as it isrouted to every flip-flop in the pipeline stage and needs to bedriven by strong drivers. For an RFF, the serves tooverwrite the master with the shadow latch data. Hence, theslave gets the correct data at the next positive edge.

The needs to be latched at the output of the dynamicOR gate so that it retains state during the next positive phase(recovery cycle) during which it disables the shadow latch toprotect state. In addition, the also disables all regular,non-“Razor”-ed flip-flops in the pipeline stage to preserve thestate that was latched in the errant cycle. This is required tomaintain the temporal consistency of all flip-flops in the pipelinestage. The stack of three pMOS transistors in the shadow latch

•  Correct data restored in the following clock cycle •  All previous pipeline stages have to be flushed •  Program counter resumes at the next instruction


Razor – issues

Good idea but has a lot of issues: -  Duty cycle constraints the shortest path -  Metastability at the output of the main FF -  The longest paths changed if a latch is added to FF

D Q

D Q

Short path

Long path D Q

Shadow Latch

CLK

ERROR!


Improvements

ü  Lower clock power ü  Data metastability solved -‐‑ Additonal buffers needed for short paths

ü  No added buffers for short paths ü  Data metastability detected w/o

additional detector - Detection window tuned in prefab

D Q

*

*

*

*

EN

ERROR

PG RISING

PG FALLING

LATCH

ERROR

ARM’10 Intel’09


Tunable Replica Circuit (TRC)

EDS

Calibration Bits

error

Logic stages: Ø  Inverter Ø NAND Ø NOR Ø  Pass gates Ø Repeated interconnects

J. Tschanz, et al., Symp. VLSI Circuits, 2009. (c) Ruzica Jevtic 2012

TRC – cont’d

1132009 Symposium on VLSI Circuits Digest of Technical Papers

•  Not so accurate as EDS, but no interfering with the longest path •  If properly tuned, no recovery mechanism needed


Observation circuits -‐‑ summary Advantages:

ü Reduce margins for process variations ü EDS:

•  enable instruction recovery •  detect errors in pipeline stages

ü  TRC: •  capture clock-to-data delay per pipeline stage •  have low design overhead

Disadvantages: -  EDS:

•  Adding buffers for short paths •  Metastability issues •  The longest path is affected by additional circuits

-  TRC: •  Cannot detect local dynamic variations •  Requires margin between TRC & the longest path •  Requires post-silicon calibration (c) Ruzica Jevtic 2012

Overview


•  Control voltage through DC-DC converters

•  Conclusions



DVFS

5

Typical MPEG IDCT Histogram

9

DesiredThroughput

Compute-intensive andlow-latency processes

Processor Usage Model

g p

Maximum Processor Speed

10

timeSystem Idle

Background andhigh-latency processes

• Maximize Peak Throughput• Minimize Average Energy/operation

System Optimizations:BurdISSCC’00Burd, ISSCC’00


DVFS – cont’d

7

1.0

LK

CMOS Circuits Track Over VDD

InverterRingOscRegFileSRAM

0.5

orm

aliz

ed m

ax. f

C

13

0VT 2VT 3VT 4VT

No

VDD

Delay tracks within +/- 10%BurdISSCC’00

Vary !CLK,VDD1 2 Dynamically adapt

Dynamic Voltage Scaling (DVS)

Vary !CLK,VDD

Delivered

Throughput

1 2 Dynamically adapt

14

time

• Dynamically scale energy/operation with throughput.• Always minimize speed minimize average energy/operation.• Extend battery life up to 10x with the exact same hardware!

BurdISSCC’00

Burd, ISSCC’00


Traditional DVFS

•  Traditional DVFS use a ring oscillator for frequency detection (Xscale, PowerPC, Pentium M, …)

•  Impossible to use nowadays: ring oscillator frequency change does not reflect the cpu frequency change

•  Different paths have different behavior with Vdd change

Counter

+ -‐‑ Fcpu_av

DC-‐‑DC

uP Ring Oscillator

... fcpu

Burd, ISSCC’00


Resilient DVFS

•  Resilient DVFS use TRCs and EDS as freq. indicator •  Two options: TRC+EDS or EDS with recovery

Fcpu_av DC-‐‑DC

uP

CLK Cntrl

EDS with recovery Slow down

J. Tschanz, et al., Symp. VLSI Circuits, 2009.

Slow down

Max. path delay Speed up

EDS TRC


RAVEN microprocessor

•  Implemented in the newest technology: 28nm! (apple i5/i7 cores in 32nm, altera chips in 28nm)

•  Mobile applications: battery life important!

•  Manycore architecture: exploiting parallelism! •  Error detection circuits for observation:

improvement over ARM architecture! •  Unconventional DVFS scheme


Motivation -‐‑ DVFS •  Single core

E

Perf

" Two cores

E

Perf

" Performance dictated by the slower core " In a conventional DVFS synchronous system


Goal •  Manycore

E

Perf

" Make sure to operate at the optimal energy-performance point

Instead of operating here

Would like to operate here

10x


Per-Core Supply/Clock Control

PLL

EDS

EDS

EDS

EDS

FIFO

FIFO FIFO

FIFO

DC-‐‑DC DC-‐‑DC

DC-‐‑DC DC-‐‑DC


DVFS on manycore processor

•  Allow the ripple at the output and track the voltage through clock generation for beler energy-‐‑efficiency

Control Clock

Generator

fdesired

DC-‐‑DC

Tracking

TRC

EDS uP

Delay

Energy


Overview



•  Conclusions

•  Control voltage through DC-DC converters


DC-‐‑DC converters

Two phases: 1. Loading the energy

from the battery 2. Transferring loaded

energy to the output


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Switched Capacitor DC-‐‑DC Converter

•  Advantages: - Fully integrated on a chip - Smaller area (no inductive components) - Large power density •  Disadvantages:

- Discrete output voltage - Low efficiency

ñ

Vin

Cfly

Φ1

Φ1 Φ2

Φ2

Φ2

Vout

Vout

Φ1 Vout Vin


0.43V

0.55V

0.78V

0.96V

Vin [V] ra)o Vout [V]

1 1/2 0.5

1 2/3 0.67

1 1/3 Too small

H-‐‑P. Le, ISSCC 2011

Discrete points solution

1.8 1/2 0.9

Range[V] 0.45 – 0.55

0.55 – 0.71

Too small

0.79 – 0.96


Efficiency solution

Efficiency can be improved by more than 10%!

Loss conventional our approach


DVFS details

Vin Vout

Energy

Delay

Vref

Vout=1/2 VinVout=2/3 Vin ...

Configuration

Fcpu_av

Clock gen.Clock gen.

DC-‐DC

TRC

...EDSEDS

uP

Tracking

Vo

clk

•  Set the ripple size at the optimal energy-‐‑delay point


Overview


•  Dynamic voltage and frequency scaling •  Control voltage through DC-DC converters

•  Conclusions


Summary •  Process variations introduce difficulties in circuit

design •  Power is a critical design constraint

•  Observation circuits needed in order to avoid too conservative design decisions (EDS and TRC)

•  Multicore/manycore architectures open spatial

dimension for energy optimization through DVFS

•  Fine granularity V-F control enabled through performance observation and DC-DC converters


Acknowledgement

Marie Curie FP7 People program


Designingenergyeﬃcient’ microprocessor:Howtoﬁght ... Memory ... [MHz] 8086 80286 386DX 486DX 486DX4 Pentium Pentium Pro Pentium II Pentium MMX Pentium III ... Delay buffers are

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