Decoders, Encoders, Multiplexers BIL- 223 Logic Circuit Design Ege University Department of Computer Engineering
Decoders, Encoders, Multiplexers BIL- 223 Logic Circuit Design Ege University Department of Computer Engineering.
Dec 13, 2015
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Decoders, Encoders, Multiplexers
BIL- 223 Logic Circuit Design
Ege UniversityDepartment of Computer
Engineering
Decoding - the conversion of an n-bit input code to an m-bit output code with
n £ m £ 2n such that each valid code word produces a uniqueoutput code Circuits that perform decoding are called decoders Functional blocks for decoding are called
n-to-m line decoderswhere m £ 2n, and generate 2n (or fewer)
minterms forthe n input variables
Decoding
1-to-2-Line Decoder
AD
AD
1
0
A D1 D0
0 0 1
1 1 0D0
D1A
2-to-4-Line Decoder
A1 A0 D3 D2 D1
D0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
D0
D1
D2
D3
2-to-4-linedecoder
A0
A1
2-to-4-Line Decoder
A1 A0 D3 D2 D1 D0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
013
012
011
010
AAD
AAD
AAD
AAD
A1
A0D0
D1
D2
D3
Enabling Enabling permits an input signal to pass
through to an output Disabling blocks an input signal from
passing through to an output, replacing it with a fixed value
XF
EN
(a)
ENX
F
(b)
2-to-4-Line Decoder w/ Enable
En
A1
A0
D3
D2
D1
D0
0 X X 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
013
012
011
010
AEnAD
AEnAD
AAEnD
AAEnD
D0
D1
D2
D3
2-to-4-linedecoder
A0
A1
En
2-to-4-Line Decoder w/ Enable
En
A1
A0
D3
D2
D1
D0
0 X X 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
013
012
011
010
AEnAD
AEnAD
AAEnD
AAEnD
A1
A0D0
D1
D2
D3
En
3-to-8-Line Decoder
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0
Truth Table
3-to-8-Line Decoder (1)
3-to-8 Line decoder
1-to-2-Line decoders
4 2-input ANDs 8 2-input ANDs
2-to-4-Linedecoder
D0A 0
A 1
A 2
D1
D2
D3
D4
D5
D6
D7
3-to-8-Line Decoder
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0
Truth Table
3-to-8-Line Decoder (2)
A2 A1 A0 D7
D6
D5
D4
D3
D2
D1
D0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0
D0
D1
D2
D3
2-to-4-linedecoder
A0
A1
En
D0
D1
D2
D3
D0
D1
D2
D3
2-to-4-linedecoder
A0
A1
En
D4
D5
D6
D7
A0
A1
A2
Implementing Combinational Logic with Decoder
D0
D1
D2
D3
3-to-8-linedecoder
A0
A1
A2
D4
D5
D6
D7
5,7)M(0,1,2,3,Z)Y,F2(X,
m(1,2,6,7)Z)Y,F1(X,
X
Y
ZF1
F2
Encoding Encoding - the opposite of decoding - the
conversion of an m-bit input code to a n-bit output code with n £ m £ 2n such that each valid code word produces a unique output code
Circuits that perform encoding are called encoders
An encoder has 2n (or fewer) input lines and n output lines which generate the binary code corresponding to the input values
M-to-N-Line Encoder (M2N)
D0
D1
D2
D3
2-to-4-lineDecoder
A0
A1
En
D0
D1
D2
D3
4-to-2-lineEncoder
A0
A1
Ac
4-to-2 Encoder
D3 D2 D1 D0 A1 A0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
Since Dx=1 only in one column at a time A0 = D1 + D3A1 = D2 + D3
00 01 11 10
00 X 0 X 1
01 0 X X X
11 X X X X
10 1 X X X
D3 D2D1 D0
D0D2or D3D1A0
For A0
00 01 11 10
00 X 0 X 0
01 1 X X X
11 X X X X
10 1 X X X
D3 D2D1 D0
D0D1or D3D2A1
For A1
8-to-3 EncoderD7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
Since Dx=1 only in one column at a time A0 = D1 + D3 + D5 + D7A1 = D2 + D3 + D6 + D7A2 = D4 + D5 + D6 + D7
Priority Encoder If more than one input value is 1, then
the encoder just designed does not work. One encoder that can accept all possible
combinations of input values and produce a meaningful result is a priority encoder.
Among the 1s that appear, it selects the most significant input position (or the least significant input position) containing a 1 and responds with the corresponding binary code for that position.
8-to-3 Priority Encoder
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 Active
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 0 1 X 0 0 1 1
0 0 0 0 0 1 X X 0 1 0 1
0 0 0 0 1 X X X 0 1 1 1
0 0 0 1 X X X X 1 0 0 1
0 0 1 X X X X X 1 0 1 1
0 1 X X X X X X 1 1 0 1
1 X X X X X X X 1 1 1 1
4-to-2 Priority Encoder
D3 D2 D1 D0 A1 A0 Active
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 X 0 1 1
0 1 X X 1 0 1
1 X X X 1 1 1
00 01 11 10
00 0 0 0 0
01 1 1 1 1
11 1 1 1 1
10 1 1 1 1
D3 D2D1 D0
D3D2A1
For A1
Or using simplification property
D2D3D2D3D3A1
4-to-2 Priority Encoder
D3 D2 D1 D0 A1 A0 Active
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 X 0 1 1
0 1 X X 1 0 1
1 X X X 1 1 1
00 01 11 10
00 0 0 1 1
01 0 0 0 0
11 1 1 1 1
10 1 1 1 1
D3 D2D1 D0
D1D2D3A0
For A0
Or using simplification property
D1D2D3D1D2D3D3A0
4-to-2 Priority Encoder
D3 D2 D1 D0 A1 A0 Active
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 X 0 1 1
0 1 X X 1 0 1
1 X X X 1 1 1
00 01 11 10
00 0 1 1 1
01 1 1 1 1
11 1 1 1 1
10 1 1 1 1
D3 D2D1 D0
D0D1D2D3Active
For Active
4-to-2 Priority Encoder Schematic
D3D2A1
D1D2D3A0
D0D1D2D3Active
D3
D2
D1
D0
A1
A0
Active
8-to-3 Priority Encoder (A2)D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 Activ
e
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 0 1 X 0 0 1 1
0 0 0 0 0 1 X X 0 1 0 1
0 0 0 0 1 X X X 0 1 1 1
0 0 0 1 X X X X 1 0 0 1
0 0 1 X X X X X 1 0 1 1
0 1 X X X X X X 1 1 0 1
1 X X X X X X X 1 1 1 1
D7D6D5D4
D7D6D5D4D5
D7D6D5D6D4D5D6
D7D6D7D5D6D7D4D5D6D7A2
8-to-3 Priority Encoder (A1)D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 Activ
e
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 0 1 X 0 0 1 1
0 0 0 0 0 1 X X 0 1 0 1
0 0 0 0 1 X X X 0 1 1 1
0 0 0 1 X X X X 1 0 0 1
0 0 1 X X X X X 1 0 1 1
0 1 X X X X X X 1 1 0 1
1 X X X X X X X 1 1 1 1
D7D6D3D4D5D2D4D5
D7 D6D3)D2D3(D4D5
D7D6D3D4D5D2D3D4D5
D7D6D3D4D5D6D2D3D4D5D6
D7D6D7D3D4D5D6D7D2D3D4D5D6D7A1
8-to-3 Priority Encoder (A0)D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 Activ
e
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 0 1 X 0 0 1 1
0 0 0 0 0 1 X X 0 1 0 1
0 0 0 0 1 X X X 0 1 1 1
0 0 0 1 X X X X 1 0 0 1
0 0 1 X X X X X 1 0 1 1
0 1 X X X X X X 1 1 0 1
1 X X X X X X X 1 1 1 1
D7D5D6D3D4D6D1D2D4D6
D7D5)D3)D1D2(D4(D6D7D5)D3)D1D2D3(D4(D6
D7D5)D3D4D1D2D3D4(D6 D7D5)D3D4D5D1D2D3D4D5(D6
D7D5D6D3D4D5D6D1D2D3D4D5D6
D7D5D6D7D3D4D5D6D7D1D2D3D4D5D6D7A0
8-to-3 Priority Encoder (All)D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 Activ
e
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 0 1 X 0 0 1 1
0 0 0 0 0 1 X X 0 1 0 1
0 0 0 0 1 X X X 0 1 1 1
0 0 0 1 X X X X 1 0 0 1
0 0 1 X X X X X 1 0 1 1
0 1 X X X X X X 1 1 0 1
1 X X X X X X X 1 1 1 1
D7D6D5D4D3D2D1Active
D7D5D6D3D4D6D1D2D4D6A0
D7D6D3D4D5D2D4D5A1
D7D6D5D4A2
Selecting of data or information is a critical function in digital systems and computers
Circuits that perform selecting have: A set of information inputs from which the
selection is made A single output A set of control lines for making the selection
Logic circuits that perform selecting are called multiplexers
Selecting
Multiplexers A multiplexer selects information from an
input line and directs the information to an output line
A typical multiplexer has n control inputs (Sn - 1, … S0) called selection inputs, 2n information inputs (I2n
- 1, … I0), and one output Y
A multiplexer can be designed to have m information inputs with m < 2n as well as n selection inputs
Multiplexers (Mux) Functionality: Selection
of a particular input Route 1 of N inputs (A)
to the output F Require selection
bits (S) En(able) bit can disable
the route and set F to 0
F
A0
A1
A2
A3S1 S0
En
4-to-1Mux
N2log
Multiplexers (Mux) w/out Enable
S1 S0 F
0 0 A0
0 1 A1
1 0 A2
1 1 A3
F
A0
A1
A2
A3S1 S0
4-to-1Mux
30121101 001 ASSAS0SASSASSF
Logic Diagram of a 4-to-1 Mux (1)
30121101 001 ASSAS0SASSASSF S1
S0
A0
A1
A2
A3
F
Logic Diagram of a 4-to-1 Mux (2)
2-to-22-line decoder 22 ´ 2 AND-OR
S1Decoder
S0
Y
S1Decoder
S0
Y
S1Decoder
43 2 AND-ORS0
Y
I2
I3
I1
x
Multiplexers (Mux) w/ Enable
En S1 S0 F
0 X X 0
1 0 0 A0
1 0 1 A1
1 1 0 A2
1 1 1 A3
30121101 001
30121101 001
ASEnSAS0EnSASSEnASSEn
)ASSAS0SASSASS(EnF
F
A0
A1
A2
A3S1 S0
En
4-to-1Mux
4-to-1 Mux w/ Enable Logic
)ASSAS0SASSASS(EnF 30121101 001 S1
S0
A0
A1
A2
A3
F
En
4-to-1 Mux w/ Enable Logic
30121101 001 ASEnSAS0EnSASSEnASSEnF S1
S0
A0
A1
A2
A3
F
En
Reduce one Gate Delayby using 4-input AND gate for the 2nd level
En
Quadruple 2-to-1 Line Mux
F[3:0]
SEL
En
2-to-1Mux
A3..0
B3..0
A[3:0]
B[3:0]
En SEL F[3:0]
0 X 0000
1 0 A[3:0]
1 1 B[3:0]
Quadruple 2-to-1 Line Mux
En SEL
F[3:0]
0 X 0000
1 0 A[3:0]
1 1 B[3:0]
SEL
B0
A0 F0
B3
A3
F3
B1
A1
F1
B2
A2
F2
En
Fx=Ax·En·SEL+Bx·En·SEL
Combinational Logic Implementationwith Multiplexers
7) 6, 2, m(1,C)B,F(A,
ABCCABCBACBAC)B,F(A,
F
A0
A1
A2
A3
S1 S0
8-to-1Mux
S2
A4
A5
A6
A7
0
00
0
1
1
1
1
Each input in a MUX is a minterm
A B C
Combinational Logic Implementationwith Multiplexers
7) 6, 2, m(1,C)B,F(A,
ABCCABCBACBAF
A B F
0 0
0 1
1 0
1 1
Combinational Logic Implementationwith Multiplexers
7) 6, 2, m(1,F
ABCCABCBACBAF
A B F
0 0 C
0 1 C
1 0 0
1 1 1
F
A0
A1
A2
A3S1 S0
En
4-to-1Mux
A B
C
C
0
1
5 V
Combinational Logic Implementationwith Multiplexers
7) 6, 2, m(1,F
ABCCABCBACBAF
B C F
0 0
0 1
1 0
1 1
Combinational Logic Implementationwith Multiplexers
7) 6, 2, m(1,F
ABCCABCBACBAF
B C F
0 0 0
0 1 A
1 0 1
1 1 A
F
A0
A1
A2
A3S1 S0
En
4-to-1Mux
B C
A
A
5V
Design Example: Gray to Binary Code
Design a circuit with multiplexers to convert a 3-bit Gray code to a binary code
GrayA B C
Binaryx y z
0 0 0 0 0 01 0 0 0 0 11 1 0 0 1 00 1 0 0 1 10 1 1 1 0 01 1 1 1 0 11 0 1 1 1 00 0 1 1 1 1
Demultiplexers (DeMux)
F
A0
A1
A2
A3S1 S0
4-to-1Mux
A
D0
D1
D2
D3S1 S0
1-to-4DeMux
DeMux OperationsS1 S0 D3 D2 D1 D0
0 0 0 0 0 A
0 1 0 0 A 0
1 0 0 A 0 0
1 1 A 0 0 0A
D0
D1
D2
D3S1 S0
1-to-4DeMux
ASSD
ASSD
ASSD
ASSD
013
012
011
010
DeMux OperationsS1 S0 D3 D2 D1 D0
0 0 0 0 0 A
0 1 0 0 A 0
1 0 0 A 0 0
1 1 A 0 0 0
ASSD
ASSD
ASSD
ASSD
013
012
011
010
D0
D1
D2
D3
A
S1
S0
DeMux Operations w/ Enable
En S1 S0 D3 D2 D1 D0
0 X X 0 0 0 0
1 0 0 0 0 0 A
1 0 1 0 0 A 0
1 1 0 0 A 0 0
1 1 1 A 0 0 0
D0
D1
D2
D3
A
S1
S0
En
Other Selection Implementations
Three-state logic in place of AND-OR
Gate input cost = 14 compared to 22 (or 18) for gate implementation
I0
I1
I2
I3
S1
S0
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