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Chapter 3: Section 3.2.4

ARM & Cortex-M4 User Manuals

Interrupt-Driven Input/Output

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Interrupt I/O

Busy/wait is very inefficient.

CPU cant do other work while testing device.

Hard to do simultaneous I/O.

Interrupts allow a device to change the flow of control inthe CPU.

Causes subroutine call to handle device.

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Interrupt interface

CPU

status

reg

data

regmechanism

PC

intr request

intr ack

data/address

IR

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Interrupt behavior

Based on subroutine call mechanism.

Interrupt forces next instruction to be a subroutine call

to a predetermined location.

Return address is saved to resume executingforeground program.

Context switched to interrupt service routine

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Interrupt physical interface

CPU and device are connected by CPU bus.

CPU and device handshake:

device asserts interrupt request;

CPU asserts interrupt acknowledge when it can handle the

interrupt.

(See ARM interrupt support)

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Example: interrupt-driven main

program

mai n( ) {whi l e ( TRUE) {

i f ( got char ) { / / set by i nt r r out i ne

OUT_DATA = achar ; / / wr i t e charOUT_STATUS = 1; / / set stat usgot char = FALSE; / / r eset f l ag}

}other processing.

}

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Example: character I/O handlers

#def i ne I N_DATA ( *( ( vol at i l e unsi gned byte *) 0xE0028018) )

#def i ne I N_STATUS ( *( ( vol at i l e unsi gned byte *) 0xE002801C) )

voi d i nput _handl er ( ) {

achar = I N_DATA; / / gl obal var i abl egot char = TRUE; / / si gnal mai n pr og

I N_STATUS = 0; / / r eset st at us

}

voi d out put _handl er ( ) {} / / i nt er r upt si gnal s char done

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Example: interrupt I/O with buffers

Queue for characters:

head tailhead tail

a

leave one empty slot

to allow full buffer to

be detected

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Buffer-based input handler

voi d i nput _handl er ( ) {char achar ;

i f ( f ul l _buf f er ( ) ) er r or = 1;

el se {

achar = I N_DATA; / / r ead char

add_char ( achar ) ; } / / add t o queue

I N_STATUS = 0; / / r eset st at us

i f ( nchar s >= 1) { / / buf f er empt y?

OUT_DATA = r emove_char ( ) ;

OUT_STATUS = 1; }} / / above needed t o i ni t i at e out put

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Interrupts vs. Subroutines CPU checks interrupt lines between instructions

Interrupt handler starting address:

fixed in some microcontrollers

usually provided as a pointer

CPU saves its state, to be restored by the interrupt handler Push items on a stack

And/Or: Save items in special registers

Handler should save any other registers that it may use

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Priorities and vectors

Two mechanisms allow us to make interrupts more specific: Prioritiesdetermine what interrupt gets CPU first.

Vectorsdetermine what code is called for each type of

interrupt.

Mechanisms are orthogonal: most CPUs provide both.

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Prioritized interrupts

CPU

device 1 device 2 device n

L1 L2 .. Ln

interruptacknowledge

interruptrequests

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Interrupt prioritization

Masking: interrupt with priority lower than current priorityis not recognized until pending interrupt is complete.

Non-maskable interrupt(NMI): highest-priority, nevermasked.

Often used for power-down. Handler may choose to enable other interrupts (allows

handler to be preempted)

CPU may also have bit(s) in its status register to enable ormask interrupt requests.

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I/O sequence diagram

:foreground :input :output :queue

empty

a

empty

b

bc

c

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Example: Prioritized I/O

:interrupts :foreground :A :B :C

B

A,B

C

A

high priority low priority

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Interrupt vectors

Allow different devices to be handled by different code.

Interrupt vector table:

Directly supported by CPU architecture and/or

Supported by a separate interrupt-support device/function

handler 0

handler 1

handler 2

handler 3

Interrupt

Vector Table

Head

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Interrupt vector acquisition

:CPU :device

receive

requestreceive

ack

receive

vector Synchronous msg

Asynchronous msg

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Generic interrupt mechanism

intr?N

Y

Assume priority selection is

handled before this point.

N

ignore

Y

ack

vector?Y

N

timeout?

Y

bus error

call table[vector]

intr priority >currentpriority?

continueexecution

Device sends vector

CPU calls handler &

Software processes the request

CPU acknowledgesthe request

CPU detects interrupt request

N

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Sources of interrupt overhead

Handler execution time. Interrupt mechanism overhead.

Register save/restore.

Pipeline-related penalties.

Cache-related penalties. Interrupt latency= time from activation of interrupt signal

until event serviced.

ARM worst-case latency to respond to interrupt is 27 cycles:

2 cycles to synchronize external request. Up to 20 cycles to complete current instruction.

3 cycles for data abort.

2 cycles to enter interrupt handling state.

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Exception

Exception: internally detected error.

Example: divide by 0

ARM: undefined opcode, data abort, memory error

Exceptions are synchronous with instructions but unpredictable.

Build exception mechanism on top of interrupt mechanism.

Exceptions are usually prioritized and vectorized.

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Trap

Trap(software interrupt): an exception generated by aninstruction.

Ex: Enter supervisor mode.

ARM uses SWI instruction for traps.

Cortex uses SVC instruction (supervisor call)