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C YCLIC R EDUNDANCY C HECK(CRC) : BY : NTH M.VAMSHIDH of,ECE. (07B61A04A9) ECE- IV B
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Page 1: CRC MY PPT

CYCLIC REDUNDANCY CHECK(CRC)

GUIDE: BY:P.SRIKANTH M.VAMSHIDHAR REDDY

Asst.Prof,ECE. (07B61A04A9)

ECE- IV B

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ERROR DETECTION PROCESS

compare

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• one of most common and powerful checks• for block of k bits transmitter generates an

(n-k)bit frame check sequence (FCS)• transmits n bits which is exactly divisible by

some number• receiver divides frame by that number

– if no remainder, assume no error

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Procedures to generate CRC

• Modulo 2 arithmetic • Polynomials• Digital logic

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Modulo 2 arithmectic

• Modulo 2 arithmetic uses binary addition or subtraction with no carries which is nothing but exclusive-OR(XOR) operation.

• For example 1111 1111

+1010 -0101

0101 1010

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• T=n-bit frame to be transmitted• D=k-bit block of data,the first k bits of T• F=(n-k)-bit FCS,the last (n-k)bits of T• P=pattern of n-k+1 bits;this is predetermined divisor T=2 D+F• T should be exactly divisible by P.• We get F as the remainder by dividing 2 D by P.• We add this remainder to the T ie T=2 D+R=Qp+R

n-k

n-k

n-k

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• Does this R satisfy condition that T/p have no remainder?• To see that consider

• However, any binary number added to itself modulo 2 yields zero.Thus T/p=Q.There is no remainder T exactly divisible by p.Thus FCS generated easily.

• This T is transmitted and divided by same p on the receiver side if remainder is zero no error, otherwise it request retransmission. This is explained by the following example.

T =2 D+R =2 D +Rp p p p

n-k n-k

But we haveTp

Rp

Rp = + + Q

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Polynomials• We can use a polynomial to represent a binary word. • In this process all values express as the polynomials in

a dummy variable X, with binary coefficients.• Each bit from right to left is mapped onto a power

term.• The rightmost bit represents the “0” power term. The

bit next to it the “1” power term, etc.• If the bit is of value zero, the power term is deleted

from the expression.

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CRC generation

• Given a Specific Polynomial p(x) called the generator, and a Data Message D(x), Calculate a Frame Check Sequence (FCS), or Checksum

• Append the FCS (Checksum) to the Data Message for Transmission

• At the Receiver, Recalculate the Checksum, and Check with the Transmitted Value

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Algorithm

• Multiply xr D(x), where r = degree of p(x)• Divide xr D(x)/p(x) = R(x)

– R(x) = Reminder of Divide Operation

• Transmit xr D(x) + R(x) = T(x)• At the Receiver, Recalculate the R(x) and

Check Equal to the Transmitted FCS• Errors Occurred in Transmission if Not equal

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CRC error detection

• all single bit errors, if p(X) has more than one nonzero term.• All double bit errors,as long asp(X) has a factor with at least three

terms.• Any odd number of errors,as long as p(X) contains a factor X+1• Any burst error for which the length of the burst is less than or

equal to the length of FCS.

Popular generator polynomials• CRC-12=X^12+X^11+X^3+X^2+X+1• CRC-CCITT=X^16+X^12+X^5+1• CRC-16=X^16+X^15+X^2+1• CRC-32=X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7

+X^5+X^4+X^2+X+1

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Digital Logic• crc can be achieved by using a dividing circuit consisting of XOR

gates and string of 1-bit storage shift register devices.• Each device has an o/p line, which indicates value currently stored,

and an i/p line.• At clock times, the value in the storage device is replaced by the

value indicated by its i/p line.

The circuit is implemented as follows:1. The register contains n-k bits,equal to the length of the FCS.2. There are up to n-k XOR gates.3. The presence or absence of a gate corresponds to the presence of a

term in the divisor polynomial,p(X),excluding term 1 and X^n-k.

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Cn-k-2Cn-k-1 C1 C0Inpuit(k bits)

Switch 1

Outputn bits

A

A

B

B

Switch 2An-k-1 An-k-2 A2 A1

General CRC Architecture

.……

.……

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The operation explained by the following example.

Data D=1010001101 D(X)=x^9+x^7+x^3+x^2+1

Divisor=110101 p(X)=x^5+x^4+x^2+1

C3C4 C1 C0Inpuit(10 bits)

Switch 1

Output(15 bits)

A

A

B

Switch 2

C2

B

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C4 C3 C2 C1 C0 c4xorc3xorI c4xorc1xorI c4xorI I=input

Initial 0 0 0 0 0 1 1 1 1

Step 1 1 0 1 0 1 1 1 1 0

Step 2 1 1 1 1 1 1 1 0 1

Step 3 1 1 1 1 0 0 0 1 0

Step 4 0 1 0 0 1 1 0 0 0

Step 5 1 0 0 1 0 1 0 1 0

Step 6 1 0 0 0 1

0 0 0 1

Message to be sent

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Conclusion

• I have presented a methodology and example calculations to determine the crc codes.

• Over copper wire or fiber ,the error rate is much lower, so error detection and retransmission is usually more efficient there for dealing with the occasional error.

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References• Computer Networks, 4th edition,2003 by Andrew S.Tanenbaum,published

by pearson education.• Wireless communications and Networks, 2nd edition by William

Stallings,published by Dorling Kindersley.• Advanced electronic communications system, 6th edition by Wayne tomasi

published by Dorling Kindersley.• IEEE 802.3 Cyclic Redundancy Check. Author: Chris Borrelli.

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In a cyclic code, those e(x) errors that are divisible by g(x) are not caught.

Received codeword (c(x) + e(x))/g(x) = c(x)/g(x) + e(x)/gx

The first part is by definition divisible the second part will determine the error. If “0” conclusion -> no error occurred.

Note: that could mean that an error went undetected.

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Which of the following g(x) values guarantees that a single-bit error is caught? For each case, what is the error that cannot be caught?a. x + 1 b. x3 c. 1

Solutiona. No xi can be divisible by x + 1. Any single-bit error can be caught.b. If i is equal to or greater than 3, xi is divisible by g(x). All single-bit errors in positions 1 to 3 are caught.c. All values of i make xi divisible by g(x). No single-bit error can be caught. This g(x) is useless.

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Find the status of the following generators related to two isolated, single-bit errors.a. x + 1 b. x4 + 1 c. x7 + x6 + 1 d. x15 + x14 + 1

Solutiona. This is a very poor choice for a generator. Any two errors next to each other cannot be detected.b. This generator cannot detect two errors that are four positions apart.c. This is a good choice for this purpose.d. This polynomial cannot divide xt + 1 if t is less than 32,768. A codeword with two isolated errors up to 32,768 bits apart can be detected by this generator.

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❏ All burst errors with L ≤ r will be detected.❏ All burst errors with L = r + 1 will be detected with probability 1 – (1/2)r–1.❏ All burst errors with L > r + 1 will be detected with probability 1 – (1/2)r.