CPLD Board - Students Guide

CPLD Board Students guide

Engineering College of Copenhagen

EIT department

Lautrupvang 15

2750 Ballerup

Denmark

Ref. : JRH

Hardware rev. : 10

Firmware rev. : 6

Software ver. : 1.1

Date : November 25th 2004

Table of contentsHardware guide....................................................................................................................................... 2

Powering the CPLD board.................................................................................................................................................. 2

The on-board peripherals................................................................................................................................................... 3The 12 switches...............................................................................................................................................................................................................3

The 12 LEDs.....................................................................................................................................................................................................................3

The 3 push buttons.........................................................................................................................................................................................................3

The 6 multiplexed 7-segment displays.......................................................................................................................................................................3

The clock signals.............................................................................................................................................................................................................4

The USB connector..........................................................................................................................................................................................................4

The expansion connector...............................................................................................................................................................................................6Ground pins..................................................................................................................................................................................... 7

Power pins....................................................................................................................................................................................... 7

General purpose I/O signals............................................................................................................................................................... 7

Dedicated input pins......................................................................................................................................................................... 7

Clock signals.................................................................................................................................................................................... 7

The setup menu................................................................................................................................................................... 8Menu: Clock frequency...................................................................................................................................................................................................8

Menu: Push button debounce.......................................................................................................................................................................................8

Menu: Display mode.......................................................................................................................................................................................................8

Menu: USB mode.............................................................................................................................................................................................................9

Menu: Firmware..............................................................................................................................................................................................................9

Software guide...................................................................................................................................... 10

PC and software requirements....................................................................................................................................... 10

Installing the CBProg programming software.............................................................................................................. 10

Installing the USB driver...................................................................................................................................................11

Using CBProg......................................................................................................................................................................12

Appendix................................................................................................................................................ 13

Tables of pin locations......................................................................................................................................................13

STUDENTS GUIDE TO THE CPLD BOARD ENGINEERING COLLEGE OF COPENHAGEN PAGE 1 OF 13

Hardware guideThis section of this guide will cover the hardware aspects you need to be aware of when using this CPLD Board. The

main part of this board is a Xilinx Coolrunner II CPLD with 256 macrocells (XC2C256-TQ144-7) available to your

designs. From the CPLD, you have access to the following:

1. 12 switches.

2. 12 LEDs.

3. 3 push buttons.

4. 6 multiplexed 7-segment displays.

5. A clock signal fixed at 6 MHz.

6. Another clock signal ranging from

600 kHz down to 1 Hz.

7. An USB 1.1 connector for data

transfer to and from a PC.

8. A 64 way DIN41612 expansion

connector.

Some of these peripherals can be set

up using the hardware setup menu

available on the board it self. This

menu will be discussed later.

Powering the CPLD boardYou can supply power to the board in two ways: from the USB connector or from the external power connector. In

either case, you need to move the jumper JP1 to the appropriate position. The jumper must be placed on the two left-

most pins of JP1, when you power the board from the USB connector (position “USB”). If you supply power from the

external power connector, the jumper must be positioned on the two right-most pins (position “EXT”).

The two fuses above JP1 named F2 (the left-most) and F1 (the right-most) protect the board and power supplies

when powering the board from the USB and the external power connector respectively. Do NOT replace these fuses

with a higher rating than stated on the board (below the fuses).

When the board is USB powered, the board will request 300 mA from your PC. If this is not available, your operating

system will reject the CPLD board. You can try another USB port or remove other USB equipment from your PC,

before connecting the CPLD board.

If you want to supply power to the board via the external power connector, you can use both DC and AC power

supplies.

Make sure the power supply provides a voltage no lower than 5 VDC and no higher

than 28 VDC (20 VAC in case of an AC supply).When you use external power, the USB transceiver is turned off. It is possible though, to use external power while

using the USB connector. In that case place JP1 in the “EXT” position.


The on-board peripheralsAs mentioned above you have access to a number of peripherals in your CPLD design. The sections below explains

these in detail. You will also find the necessary information about the pin locations.

The 12 switches

The 12 switches each have two positions. When a switch is pointing down, you will read a '0' in your CPLD from that

specific switch. When it is pointing up, you will read a '1'. The switches are numbered from 0 to 11 starting from the

right. The following table shows the pin locations of your CPLD.

Switch 11 10 9 8 7 6 5 4 3 2 1 0

Location P2 P4 P6 P9 P11 P13 P15 P17 P19 P21 P23 P25

The 12 LEDs

The light emitting diodes (LEDs) are all active high – i.e. they light up, when you apply a '1' to them. They turn off,

when you output a '0'. These LEDs are located as seen in the table below.

LED 11 10 9 8 7 6 5 4 3 2 1 0


The 3 push buttons

The push buttons located to the left of the displays are all active high. When you push a button, you will read a '1'

from it and a '0' when it is released. You will find these buttons as indicated by the table below.

Push button 2 1 0

Location P107 P116 P126

Please notice that the operation of the push buttons can be changed by a setting in the setup menu. The board can

deliver the push button signals to your design either debounced or not debounced. “Debounced” means that the noise

coming from the mechanical button is removed, before the signal enters your CPLD. The default setting is “not

debounced”, but it can be enabled in the setup menu as discussed later.

The 6 multiplexed 7-segment displays

The signals related to the display depends on the settings in the “Display mode” sub-menu as discussed later. You

have the option to use only one display (the right-most one), have total access to the display (“Raw display” option)

or use the multiplexing circuit built in (“Full display”). If you select the “One display” mode, you have a simple 8 bit

interface, where each bit represents one segment of the active 7-segment display. In that case the pin locations will

look as shown below.

Segment A B C D E F G DP

Location P103 P104 P112 P113 P120 P121 P131 P132

If you decide to use the raw display, in addition to the signals mentioned above, you will have to control 6 more

signals, telling the display what 7-segment display has to be active. This is called “strobe signals”. These 6 signals are

located as shown below.

Strobe 5 4 3 2 1 0

Location P105 P106 P114 P115 P124 P125

The strobe signals are active low – i.e. if you pull f.ex. “Strobe 4” low ('0'), the second display from the left will turn


on, showing the segment data present on the segment signals mentioned above. “Strobe 5” affects the left-most

display, and “Strobe 0” affects the right-most one. Note that only one strobe signal should be low at any point in time

– the remaining strobe signals should be held high ('1').

Finally, you have the option of utilizing the built-in display multiplexer (“Full display”). In this mode you can regard

the display as a kind of memory (or “port”), consisting of a 6 words deep memory with each word being 8 bits wide.

Signal Write Enable Write Strobe Address

WE Wr A(2) A(1) A(0)

Location P105 P106 P115 P124 P125

The six displays will be memory-mapped according to the address signals seen in the table above. The memory-map

will be defined as seen below.

Address Display

1112 = 7 Not used

1102 = 6 Not used

1012 = 5 5

1002 = 4 4

0112 = 3 3

0102 = 2 2

0012 = 1 1

0002 = 0 0

The update a cipher in the display using the “Full” mode, follow the diagram shown below.

The clock signals

You have two clock signals available to your CPLD design. One is fixed at 6 MHz (we name this “ClkFast”), and one is

variable (named “ClkSlow”) according to a setting in the setup menu. In any case they are located as seen below:

Clock signal ClkFast ClkSlow

Location P30 P38

Refer to the section discussing the “Clock frequency” setting for further information about the available frequencies of

the ClkSlow signal.

The USB connector

The CPLD board includes a USB 1.1 connector enabling you to do data transfers to and from a PC at up to 1 MByte/s.

From within your CPLD you have direct access to the necessary data and control signals of the USB transceiver

FT245BM from FTDI Chip. It provides a simple 8 bit parallel interface to the USB channel. If you need to utilize this,

refer to the FTDI Chip web site (http://www.ftdichip.com) and browse the site for the data sheets, drivers and

application notes.


WE

Wr

A(2:0)

Segment(7:0)

Display address

Segment data

At the rising edge of Wr, the data present on the segmentsignal lines is stored in the display with the address specifiedby the address signals. WE must be high, when the risingedge on Wr occurs. The data on the segment and addressmust be held stable at least 50 ns before and after the risingedge on Wr.

The USB signals available to you are listed in the table below.

Data bit 7 6 5 4 3 2 1 0 Signal Rd RxF Wr TxE

Location P110 P111 P117 P118 P119 P128 P129 P130 Location P135 P133 P136 P134

The USB signals are dependant on a setting in the setup menu. If you want to transfer data to and from a PC using

the USB channel, you need to select the appropriate setting in the “USB mode” sub-menu.

The USB connector can also be used to program the CPLD, if you use the supplied programming software (“CBProg”).

Make sure all four jumpers below the USB connector are placed at the right-most

position to enable CPLD programming via the USB connector.


The expansion connector

This connector is located along the right edge of the board. It provides power, clock signals and a number of bi-

directional signals to and from add-on boards. This connector makes it possible to expand the capabilities of the CPLD

board. Because of the complexity of the connector, we will present the pin locations of the connector in a drawing of

the connector as seen from the add-on board side – i.e. looking into the connector on the CPLD board.

The illustration shows the 64 pins of the connector consisting of:

8 ground pins.

8 power pins.

5 groups of pins each consisting of 8 general purpose I/O signals (in total 40 I/O signals).

6 dedicated input pins – one of these (P32) is a global clock input to your CPLD.

2 clock signal outputs (“ClkFast” and “ClkSlow”).

These pin categories will be explained in detail below. Note that all signals pins are 5

V tolerant, because of the transceivers protecting the CPLD board. You can interface

the CPLD board to 5 V digital logic, even though the CPLD on the CPLD board is

using 3.3 V only. The figure to the right illustrates the guaranteed (worst-case) input

and output voltage ranges of the signal pins. You must obey the input voltage range

shown in the illustration – otherwise the CPLD board might not recognize your digital

signals correctly. The output voltage range is defined as 0 volts to 3.3 volts, which

should accommodate most kinds of logic used on expansion boards. One problem

exists, however, when interfacing 5 volt CMOS logic to the expansion connector,

because the internal transceivers are not able to signal a guaranteed logical '1' to

this technology. When a signal pin is configured as an output, as low as 2.2 volts can

be seen, when the signal pin is high. This is not enough for a 5 volt CMOS IC to

recognize the signal as being high. If you built an expansion board using 5 volt logic,

you should consult the data sheets of the integrated circuits you use to determine, if

the problem exists in your case. Some of these problems can be minimized by using

pull-up resistors on these expansion connector outputs (pull up these signals to your

5 volt power supply). The output voltage range illustrated is based on data sheet information, when you load the

output as much as allowable (±24 mA). You can obtain further information about the transceivers protecting the CPLD

board by looking at the data sheet (Texas Instruments SN74LVC245A-N).


0

1

+5.00 V

0.00 V

+0.80 V

+2.00 V

0

1

+3.30 V

0.00 V

+0.55 V

+2.20 V

Inputvoltage range

Outputvoltage range

+Vex

t

+3.3

V/1

A

+Vex

t

+3.3

V/1

A

GN

D

P101

P98

P96

P94

P87

P85

P82

P80

GN

D

P61

P66

P69

P71

P50

P52

P54

P57

GN

D

P39

P41

P43

P45

P28

Clk

Fast

P33

P35

GN

D

+1.8

V/1

A

+1.8

V/1

A

GN

D

P100

P97

P95

P92

P86

P83

P81

P79

GN

D

P64

P68

P70

P74

P51

P53

P56

P58

GN

D

P40

P42

P44

P46

P31

P32

P34

Clk

Slo

w

GN

D

+Vbus

+Vbus

DIR

OE

P48

P49

DIR

OE

P59

P60

DIR

OE

P75

P76

DIR

OE

P78

P77

DIR

OE

P91

P88

A32

C32

A1

C1

PORT E PORT D PORT C PORT B PORT A

Do not apply negative or higher voltages than 5 V to any of the signal pins of the

expansion connector.If you decide to design an add-on board to the CPLD board, you should be aware of

the pin numbering of the DIN connector used. You would probably want to use the

angled female counterpart to the expansion connector, and the pin numbering of this

counterpart is in a way mirrored. This means that, seen from your board, the pin named

A1 in the expansion connector of the CPLD board will be named A32 on your add-on

board. Remember, the numbering are mirrored, the A and C rows are not!

Ground pins

These pins are the common ground of all signal. Unless your add-on board has special ground requirements, it is not

necessary to connect your ground to all ground pins of the connector.

Power pins

The CPLD board provides the power supplies used internally to the expansion connector – i.e. +3.3 V and +1.8 V.

Make sure you do not draw more than 1 A from each power supply - i.e. 1 A from

the +3.3 V supply and 1 A from the +1.8 V supply.The +Vext pins can be used to provide power to the CPLD board from your add-on board. It is the same as powering

the CPLD board via the external power connector. You can also power the CPLD board via the external power

connector and use the +Vext pins to power your add-on board directly. This makes it possible to step-down the

external power supply voltage to the voltage needed by your add-on board.

The +Vbus pins provides the USB bus power directly to your board. The voltage coming from an USB hub falls within

the range +4.5V to +5.5V. Take care not to overload these power pins - “overload” means no more than 300 mA

should be drawn from the USB hub in total (including the CPLD board requirements).

General purpose I/O signals

These signals provide the main interface to and from your add-on board. The signals are arranged in groups (ports) of

8 signals each. These signals are either inputs or outputs, depending on the level of the “DIR” signal of each port

(seen above each port). When the DIR signal is '0', all signals in that port are inputs to the CPLD board. When the DIR

signal is '1', all signals are outputs. For example, if P91 is '1', all signals in that port (Port A - P92, P94, P95, P96,

P97, P98, P100 and P101) are outputs.

Each port also has an “OE” signal. “OE” means “Output enable” and is used to disable (tri-state) the entire port. This

signal is active low – i.e. when OE is '0', all signals in that port are active, and when OE is '1' all signals are tri-stated.

This is, by the way, the default value, so you need to control both DIR and OE, if you want to use any of the I/O

ports.

Dedicated input pins

In addition to the general I/O signals discussed above, the expansion connector provides 6 more signals with a fixed

data direction as inputs. The 6 inputs are general purpose outputs, where one of them (P32) is fed to your CPLD's

GCK1 input - GCK inputs are global clock inputs. The remaining 5 inputs can be used as you like – you could f. ex.

use these inputs for letting the add-on board determine the DIR and OE signals of the ports mentioned above (if you

connect these inputs to the corresponding DIR and OE outputs in your CPLD design).

Clock signals

The 2 clock signals present on the CPLD board, ClkFast and ClkSlow, can be found in the expansion connector as seen

in the illustration. If you use these clock signals for synchronizing your add-on board design, you should consider

placing a low pass filter on the desired clock signal on your add-on board to ensure signal integrity of the clock signal

- an RC low-pass filter consisting of 100 ohms and 10 pF should be adequate.


The setup menuThe CPLD board features a setup menu for

adjusting the functionality of some of the

peripherals mentioned above. The menu is entered

by pressing and holding the setup push button (in

the lower left corner of the board) for about one

second. When the setup menu is active, the LED

just above the setup button will flash. The display

will now be used to visualize the menu by using the

left-most and the right-most display. The left-most

display shows the currently selected sub-menu.

The right-most display shows the current setting of

that sub-menu. Your CPLD design looses control of

the display and the two push buttons PB2 and PB1,

when the setup menu is activated.

When the setup is active, the setup button is used

to go to the next sub-menu by pushing and

releasing the button within one second. The left-

most display will at all times reflect the currently

active sub-menu. The settings can be changed by

pushing either PB2 or PB1 next to the setup button.

When you are done configuring the board, press

and hold the setup button for about one second

again – the setup menu will then deactivate, and

your design regains control of the push buttons and

display.

Menu: Clock frequency

The setting of this sub-menu determines the

frequency of the ClkSlow clock signal. As seen in

the illustration to the right, it is possible to adjust

the ClkSlow frequency in the range from 1 Hz up to

600 kHz. The frequencies have a tolerance of ±80

ppm.

If you select “Manual clock”, you can use the setup

button to generate manual transitions on the

ClkSlow signal by pushing and quickly releasing the

button, when you have exited the setup menu. The

setup LED will show the current logic level of the

ClkSlow signal by lighting up when ClkSlow is high

and vice versa.

Menu: Push button debounce

The three push buttons can be debounced, before the signals enter your CPLD. This sub-menu setting determines if

this feature is enabled or disabled.

Menu: Display mode

This sub-menu determines how the display operates. If you want access to only one 7-segment display, select “One

display”. If you want to control the entire display yourself, select “Raw display”. If you need to use the built-in display

multiplexer, select the “Full display” option. For further information see the section describing the display earlier in

this document.


Clock frequency

Push button debounce

Display mode

USB mode

Firmware version

10 0 Hz = 1 Hz

600 kHz

105 Hz = 100 kHz

104 Hz = 10 kHz

103 Hz = 1 kHz

102 Hz = 100 Hz

101 Hz = 10 Hz

Manual clock

Disabled

Enabled

Raw display

Full display

JTAG

Data

Version

Sub-menu selection:Push and quickly releasethe setup button

Sub-menu setting:Push and quickly release PB2 orPB1 to go up or down respectively.

One display

Menu: USB mode

The USB channel can operate in two modes: Data or JTAG mode. When you want to program your CPLD via the

supplied programming software, CBProg, this mode should be set to “JTAG”. If you want to do data transfer to and

from your PC via USB, select “Data”.

Menu: Firmware

This sub-menu shows the current firmware running in the board. This is a service information and should not be of

concern to the user.


Software guideThis section describes the installation and use of the supplied Microsoft Windows software (CBProg) for use with the

CPLD board. The software is used for programming the CPLD via USB.

The installation is done in two steps:

1. Installing the software package.

2. Connecting a CPLD Board to your PC and installing the supplied USB driver.

When you install the supplied software package, the USB driver for the CPLD Board will be installed in a separate

folder located in the folder you choose to install CBProg to.

Do not start the CBProg application, until you have installed the USB driver for at

least one CPLD Board.The following sections describe the installation steps and how to use the CBProg application in details.

PC and software requirementsPC with an available USB 1.1 port. The USB port must be able to supply at least 300 mA.

Microsoft Windows with USB support (for example Windows XP).

Functioning installation of Xilinx WebPack or Foundation (version 6 or later).

Installing the CBProg programming softwareStart “CPLD Board Programmer Setup.exe” and follow the instructions as seen in the pictures below. When the

installation has completed, the CBProg application, the CPLD Board USB driver and this guide have been copied to

your PC.


Installing the USB driverWhen you connect a CPLD board to your PC for the first time, Windows asks for an USB driver. This driver must be

installed correctly. The following describes the installation of this driver by using Windows XP as an example. The

pictures below support the example.

1. Connect the CPLD board to your PC.

2. Windows will report that it has found new hardware. Wait until the “Found New Hardware Wizard” appears.

3. Select “Install from a list or specific location (Advanced)” and click “Next >”.

4. Point the Wizard to the location of the driver. The driver has been installed in a folder called “Driver” where you

installed the CBProg software. Click “Next >”.

5. Click “Continue Anyway” in the Windows Logo Certification warning window.

6. Windows inform you that the driver has been successfully installed (hopefully!). Click “Finish”.

Note that you need to install a driver for every CPLD Board you connect. Even though it is the same kind of board, the

built-in serial number is different, and Windows requires a separate driver for each board – you can use the same

driver for all boards.


Using CBProgWhen you execute the CBProg application, the main

window will appear as seen to the right. The illustration

points out seven important areas in the window.

1. This area reflects the current CPLD Board status. The

two LEDs (circles) to the left must be green, before

you can commence the programming of the CPLD

Board. The first LED will be red, if no CPLD Board is

connected to the PC at all. This will also happen, if the

USB driver is not installed correctly. The second LED

will be red, if JTAG Mode is not enabled in the setup

menu of the board.

2. This area shows some information about the currently connected board.

3. Here, you can monitor the progress of the currently active operation.

4. If both LEDs are green in the CPLD Board status area, you can push this button to open the JEDEC file (*.JED)

containing your design. The JEDEC file is generated by WebPack/Foundation. Make sure you do not open JEDEC

files intended for other CPLDs, because CBProg can not determine, if the selected JEDEC file is valid for the CPLD

Board.

5. When a JEDEC file has been opened, you push this button to start the programming operation. This takes a few

seconds, and CBProg will inform of the progress in the progress information area (3).

6. Push this button to do a quick erase of the CPLD. This is not necessary under normal circumstances – the

programming operation includes an erasure of the CPLD before commencing the actual programming.

7. Pushing this button will open a test window, enabling you to verify the functionality of the display, the LEDs, the

switches and the push buttons.


1

2

4

5

6

3

7

Appendix

Tables of pin locations

Switch 11 10 9 8 7 6 5 4 3 2 1 0


LED 11 10 9 8 7 6 5 4 3 2 1 0


Push button 2 1 0

Location P107 P116 P126

Segment A B C D E F G DP

Location P103 P104 P112 P113 P120 P121 P131 P132

Strobe 5 4 3 2 1 0

Location P105 P106 P114 P115 P124 P125

Signal Write Enable Write Strobe Address

WE Wr A(2) A(1) A(0)

Location P105 P106 P115 P124 P125

Clock signal ClkFast ClkSlow

Location P30 P38

Data bit 7 6 5 4 3 2 1 0 Signal Rd RxF Wr TxE

Location P110 P111 P117 P118 P119 P128 P129 P130 Location P135 P133 P136 P134


CPLD Board - Students Guide

Documents

supplied programming

push button

external power

clock signal

push button

external power

jedec file

clock frequency