CPE/EE 421 Microcomputers ¾

Alexander Milenkovich 1

CPE/EE 421/521 Microcomputers 1

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CPE/EE 421Microcomputers

THE 68000 CPU HARDWARE MODEL

Instructor: Dr Aleksandar MilenkovicLecture Notes

S21


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THE 68000 CPU HARDWARE MODELChapter 4

68000 interface

Timing diagram

Minimal configuration using the 68000


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Figure 4.14

A 68000 Read Cycle


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3 tcyc = tCLAV + tacc + tDICL



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Timing Example

68000 clock 8 MHz tCYC = 125 ns

68000 CPU tCLAV = 70 ns

68000 CPU tDICL = 15 ns

What is the minimum tacc?

3 tCYC = tCLAV + tacc + tDICL

375 = 70 + tacc + 15

tacc = 290 ns


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Figure 4.15

Extended Read Cycle

DTACK* did not go low at least 20ns before the falling edge of state S4

Designer has to provide logic to control DTACK*


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Figure 4.18

Memory Timing Diagram

The 6116 static memory component2K x 8bit memory – byte-oriented!Two 6116’s configured in parallel to allow word accessesEleven address inputs


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Figure 4.17

Assumptions:R/W* is high for the duration of the read cycleOE* is low

Memory Timing Diagram, cont’d(min 200ns – address stable)

(max 200ns)

(max 15ns)

Data is floating

(max 50ns)

(usually derived from UDS*/LDS*)



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HD00

D07

D08

D15

A12

A23

A01

A11

A01

A11

A01

A11

Figure 4.19

Connect

ing T

he

6116 R

AM

to a

68000 C

PU

No operation111100Lower byte read010100Upper byte read101000

Word read000000No operation11XX1XNo operation11XXX1OperationCS2*CS1*LDS*UDS*RAMCS*AS*

OutputsInputs


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Figure 4.20

Connec

ting T

he

6116 R

AM

to a

68000 C

PUTim

ing D

iagra

m

Turnoff time70+10+60 =

140ns

70ns

10ns

60ns


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HTiming Example

68000 clock 8 MHz tCYC = 125 ns68000 CPU tCLAV = 70 ns68000 CPU tDICL = 15 nsWhat is the minimum tacc?3 × tCYC > tCLAV + tacc + tDICL

375 > 70 + tacc + 15tacc < 290 ns (or tAA from the timing diagram, access time)

For the 12.5MHz version of 68000 tCYC = 80 ns68000 CPU tCLAV = 55 ns68000 CPU tDICL = 10 ns3×80 > 55 + tacc + 10tacc < 175 ns

Remember, maximum tAA for the 6116 RAM was 200 ns


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68000 Write Cycle

68000 transmits a byte or a word to memory or a peripheral

Essential differences:The CPU provides data at the beginning of a write cycleOne of the bus slaves (see later) reads the data

In a read cycle DS* and AS* were asserted concurrentlyThis will be not a case here!

Reason for that: 68000 asserts DS* only when the contents of data bus have stabilized

Therefore, memory can use UDS*/LDS* to latch data from the CPU



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HSimplified write cycle timing diagram

In a write cycle: UDS*/LDS* is asserted

one cycle after AS*

Figure 4.22


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Figure 4.23

Follow this sequence of events in a write cycle:

Address stableAS* assertedR/W* brought lowData validDS* asserted


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Figure 4.24

Write Cycle Timing Diagram of a 6116 RAM

Address setup time(min 20ns)

Address valid to end of write(min 120ns)

Write pulse width(min 90ns)

Write recovery time(min 10ns)


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Write Cycle Timing Diagram of a 6116 RAM, cont’d

Write cycle ends with either CS* or WE* being negated (CS* and WE* internally combined)

An address must be valid for at least tAS nanoseconds before WE* is asserted

Must remain valid for at least tWR nanoseconds after WE* is negated

Data from the CPU must be valid for at least tDW nanoseconds before WE* is negated

Must remain valid for at least tDH nanoseconds after the end of the cycle



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Designing a Memory Subsystem, an example

Design a M68000 memory subsystem usingTwo 32K × 8 RAM chips residing at address $00 8000Two 8K × 8 RAM chips residing in the consecutive windowLS 138 (3 to 8 decoder) and basic logic gates

Solution32K is 4 × 8K

=> Let’s split the address space into 8K modulesIn total, we have five (4+1) 8K windowsTo address each line in 8K window

=> 13 bits (23*210 = 213 = 8K)To address five modules we need 3 bitsDon’t forget that there is no A0, we will use LDS/UDS


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A Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

B

C

LS138

E1

E2

E3

A14

A16A15

AS*

LDS*

A17

A23

...

R1CSL*

RAM2*Vcc

RAM1*

UDS*

R2CSL*

R1CSU*

R2CSU*

A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00

address within 8K modulemodule address

UDSLDS

0 0 8 0 0 0


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RAM32Kx8

A0

A14

...

CE*OE*

D0

D7D6

D5

D4

D3

D2

D1

RAM32Kx8

A0

A14

...

CE*OE*

D0

D7D6

D5

D4

D3

D2

D1

RAM8Kx8

A0

A12

...

CE*OE*

D0

D7D6

D5

D4

D3

D2

D1

WE*

A13

A1

A15

A1

D7D6D5D4D3D2D1D0

A1..A23

A15

A1

D0..D15

R/W*

R1CSL* R1CSLU*

R2CSL* R2CSLU*

RAM8Kx8

A0

A12

...

CE*OE*

D0

D7D6

D5

D4

D3

D2

D1

WE*

A13

A1

R/W*

WE*R/W* WE*R/W*

D7D6D5D4D3D2D1D0

D15D14D13D12D11D10D9D8

D15D14D13D12D11D10D9D8


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Figure 4.9

Interrupt Control Interface (details later)

priority

low

high



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Data bus

Address bus

Control bus

Arbitration bus

Slave module

Memory

Master module

Local memory

CPU

I/O

Master module

Local memory

CPU

I/O

Bus Arbitration ControlWhen 68000 controls the address and data buses, we call it the bus master

The 68000 may allow another 68000 or DMA controller to take control over buses

In the system with only one bus master, 68000 would have permanent control of the address and data buses


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HBus Arbitration Control, cont’d

68000 must respond to BR* request (it cannot be masked)

Assertion of BG* indicates that the bus will be given up at the end of present bus cycle

Requesting device waits until AS*, DTACK*, and BGACK* have been negated, and only then asserts its own BGACK* output

Old master negates its BG*, and BR* can be asserted by another potential master


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Figure 4.27a

Data Bus Contention in Microcomputers

Situation where more than one device attempts to drive the bus simultaneously

Example: Two memory modules, M1 selected during read cycle 1, M2 selected during read cycle 2

Assumption: M1 has data bus drivers with relatively long turn-off timesM2 has data bus drivers with relatively short turn-on times


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Long turn-off time

Data Bus Contention in Microcomputers, cont’d

Short turn-on time



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HBus Contention and Data Bus Transceivers

Data bus transceiver – consists of a transmitter (driver) and a receiverDriver – tristate output, can be driven high, low, or internally disconnected form the rest of the circuitTwo control inputs: Enable (active low) and DIR (direction)Dynamic data bus contention


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Minimal Configuration Using The 68000


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DESIGN CONSTRAINTS

Used in stand-alone mode

Classroom teaching aid

16 KB EPROM-based monitor

Speed is not important

At least 4 KB RAM

1 serial and 1 parallel port

Memory expandable

No interrupts and multiple processors


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MAJOR COMPONENTS

ROM – Two 8K × 8 components

RAM – Two 2K × 8 components

Parallel – 6821 Peripheral Interface Adapter (PIA)

Serial – 6850 Asynchronous Comm. Interface Adapter (ACIA)



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DESIGH CHOICES

Chose the location of ROM (16KB) and RAM (8 KB) within the address space (16 MB)

Unimportant, as long as the reset vectors are located at $00 0000

Chose the location of memory-mapped peripherals

Control of DTACK* (is delay applied or not?)


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The 68000’s Reset Sequence

Fetch SSP fromaddress 0

RESET SEQUENCE

Set SR S bit to 1Set SR T bit to 0

Set SR mask to 111

Transfer longwordto SSP

Fetch initial PC fromaddress 4

Transfer longwordto PC

Begin processing inthe supervisor state

Bus erroroccurs?

Double buserror

Bus erroroccurs?

FATALERROR


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REMEMBER

When the RESET* pin is asserted for the appropriate duration:

SR = $2700SSP is loaded with the longword @ $00 0000PC is loaded with the longword @ $00 0004


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Blo

ck D

iagra

m o

f a

68000-b

ased

mic

roco

mpute

r

Figure 4.43



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Memory and Peripheral Components

We assigned address lines to address pins, and data lines to data pins.

Before designing logic that will generate chip select signals, we have to decide about RAM/ROM location.

To assure that the reset vector location is at $00 0000, let’s situate 16 KB of ROM at $00 0000


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Mem

ory

and P

erip

her

al C

om

ponen

ts

Figure 4.44


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Control Section

We will divide the memory space $00 0000 - $01 FFFF into eight blocks of 16 KB (IC1a,b, IC2a, IC3)

16 KBytes of ROM are at $00 0000 to $00 3FFF

Where is the RAM situated? Peripherals?

Note: there is no delay applied to DTACK*.

What will happen if we access non-decoded memory?


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Contr

ol Sec

tion

Figure 4.45



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HDifferent approaches to memory arrangement

Largest memory window (16 KB)[MEMORY GAPS]

A23 A17A16A15A14A13 A1

SELECT DECODER

DECODER


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HDifferent approaches to memory arrangement, cont’d

Smallest memory window (4 KB)[NO MEMORY GAPS]

A23 A15A14A13A12A11 A1

SELECT DECODER

DECODER

A Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

B

C

E1

E2

E3

A12

A14A13

ROM (16 KB)4 Windows (Blocks)

RAM

A23...

AS*A15

Vcc


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HHow can we make it better?

ROM is EPROM-based, and thus slower

With EPROMs from the same generation, we’ll need wait states, maybe even with RAM components

Watchdog for non-decoded memory addresses


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How

can

we

mak

e it b

ette

r?

Figure 4.46



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HHow can we make it better? Cont’d

CONTROL OF INTERRUPTSUse 74LS148 priority encoder to provide 7 levels of interrupt

EXTERNAL BUS INTERFACECPU can supply only the limited current to drive the busSOLUTION: Bus drivers (buffers)


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HDTACK* Generation

DTACK* generator based on a shift register

Figure 4.72


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HDTACK* GenerationShift register and its timing diagram


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HDTACK* GenerationShift register and its timing diagram



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HDTACK* GenerationDTACK* generator based on a counter

Figure 4.74

CPE/EE 421 Microcomputers ¾

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