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chap05. ppt

Jan 27, 2017

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Page 1: chap05. ppt

Chapter 5

ComputerOrganization

(計算機組織 )

Page 2: chap05. ppt

Distinguish between the three components of a computer Distinguish between the three components of a computer hardware.hardware.List the functionality of each component.List the functionality of each component.

Understand memory addressing and calculate the number ofUnderstand memory addressing and calculate the number ofbytes for a specified purpose.bytes for a specified purpose.

After reading this chapter, the reader should After reading this chapter, the reader should be able to:be able to:

OOBJECTIVESBJECTIVES

Distinguish between different types of memories.Distinguish between different types of memories.

Understand how each input/output device works. Understand how each input/output device works.

Continued on the next slideContinued on the next slide

Page 3: chap05. ppt

Understand the systems used to connect different Understand the systems used to connect different components together.components together.

Understand the addressing system for input/outputUnderstand the addressing system for input/outputdevices.devices.

Understand the program execution and machine cycles.Understand the program execution and machine cycles.

OOBJECTIVES (continued)BJECTIVES (continued)

Distinguish between programmed I/O, interrupt-drivenDistinguish between programmed I/O, interrupt-drivenI/O and direct memory access (DMA).I/O and direct memory access (DMA).

Understand the two major architectures used to define Understand the two major architectures used to define the instruction sets of a computer: CISC and RISC. the instruction sets of a computer: CISC and RISC.

Page 4: chap05. ppt

Figure 5-1

Computer hardware (subsystems)

Page 5: chap05. ppt

CENTRALCENTRALPROCESSINGPROCESSING

UNITUNIT(CPU)(CPU)

5.15.1

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Figure 5-2

CPU

Page 7: chap05. ppt

MAIN MEMORYMAIN MEMORY

5.25.2

Page 8: chap05. ppt

Table 5.1 Memory unitsTable 5.1 Memory units

UnitUnit------------kilobyte

megabytegigabyteterabytepetabyteexabyte

Exact Number of bytesExact Number of bytes------------------------

210 bytes220 bytes230 bytes240 bytes250 bytes260 bytes

ApproximationApproximation------------103 bytes106 bytes109 bytes1012 bytes1015 bytes1018 bytes

Page 9: chap05. ppt

Figure 5-3

Main memory

Page 10: chap05. ppt

Memory addresses are defined usingMemory addresses are defined usingunsigned binary integers. unsigned binary integers.

Note:Note:

Page 11: chap05. ppt

Example 1Example 1

A computer has 32 MB (megabytes) of memory. How many bits are needed to address any single byte in memory?

SolutionSolution

The memory address space is 32 MB, or 2The memory address space is 32 MB, or 22525 (2 (255 x x 222020). This means you need). This means you needloglog22 2 22525 or 25 bits, to address each byte. or 25 bits, to address each byte.

Page 12: chap05. ppt

Example 2Example 2

A computer has 128 MB of memory. Each word in this computer is 8 bytes. How many bits are needed to address any single word in memory?

SolutionSolution

The memory address space is 128 MB, which The memory address space is 128 MB, which means 2means 22727. However, each word is 8 (2. However, each word is 8 (233) bytes, ) bytes, which means that you have 2which means that you have 22424 words. This words. This means you need logmeans you need log22 2 22424 or 24 bits, to address or 24 bits, to address each word.each word.

Page 13: chap05. ppt

Memory Types

• RAM (Random access memory):– SRAM (Static RAM) (flip-flop gates)– DRAM (Dynamic RAM)

• ROM (Read only memory)– PROM (programmable)– EPROM (erasable programmable)– EEPROM (electronically erasable programmable)

Page 14: chap05. ppt

A simple flip-flop circuit

Set

Reset

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Setting the output of a flip-flop to 1

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Setting the output of a flip-flop to 1 (continued)

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Setting the output of a flip-flop to 1

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Another way of constructing a flip-flop

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Figure 5-4

Memory hierarchy

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Figure 5-5

Cache

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INPUT / OUTPUTINPUT / OUTPUT

5.35.3

Page 22: chap05. ppt

Figure 5-6

Physical layout of a magnetic disk

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Figure 5-7

Surface organization of a disk

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Figure 5-8

Mechanical configuration of a tape

Page 25: chap05. ppt

Figure 5-9

Surface organization of a tape

Page 26: chap05. ppt

Figure 5-10

Creation and use of CD-ROM

Page 27: chap05. ppt

Table 5.2 CD-ROM speedsTable 5.2 CD-ROM speeds

SpeedSpeed------------

1x2x4x6x8x

12x16x24x32x40x

Data RateData Rate------------------------

153,600 bytes per second307,200 bytes per second614,400 bytes per second921,600 bytes per second1,228,800 bytes per second1,843,200 bytes per second 2,457,600 bytes per second3,688,400 bytes per second 4,915,200 bytes per second6,144,000 bytes per second

ApproximationApproximation------------150 KB/s300 KB/s600 KB/s900 KB/s1.2 MB/s1.8 MB/s2.4 MB/s3.6 MB/s4.8 MB/s6 MB/s

Page 28: chap05. ppt

Figure 5-11

CD-ROM format

Page 29: chap05. ppt

Figure 5-12

Making a CD-R

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Figure 5-13

Making a CD-RW

Page 31: chap05. ppt

Table 5.3 DVD capacitiesTable 5.3 DVD capacities

FeatureFeature---------------------------------single-sided, single-layersingle-sided, dual-layer

double-sided, single-layerdouble-sided, dual-layer

CapacityCapacity------------

4.7 GB8.5 GB9.4 GB17 GB

Page 32: chap05. ppt

SUBSYSTEMSUBSYSTEMINTERCONNECTIONINTERCONNECTION

5.45.4

Page 33: chap05. ppt

Figure 5-14

Connecting CPU and memory using three buses

Page 34: chap05. ppt

Figure 5-15

Connecting I/O devices to the buses

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Figure 5-16

SCSI controller(Small Computer System Interface)

Daisy Chain

Page 36: chap05. ppt

Figure 5-17

FireWire controller(IEEE 1394)

Page 37: chap05. ppt

Figure 5-18

USB controller(Universal Serial Bus)

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Figure 5-19

Isolated I/O addressing

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Figure 5-20

Memory-mapped I/O addressing

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PROGRAMPROGRAMEXECUTIONEXECUTION

5.55.5

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Figure 5-21

Steps of a cycle

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Figure 5-22

Contents of memory and register before execution

Page 43: chap05. ppt

Figure 5-23.a

Contents of memory and registers after each cycle

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Figure 5-23.b

Contents of memory and registers after each cycle

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Figure 5-23.c

Contents of memory and registers after each cycle

Page 46: chap05. ppt

Figure 5-23.d

Contents of memory and registers after each cycle

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Figure 5-24

Programmed I/O

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Figure 5-25

Interrupt-driven I/O

Page 49: chap05. ppt

Figure 5-26

DMA connection to the general bus

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Figure 5-27

DMA input/output

Page 51: chap05. ppt

TWO DIFFERENTTWO DIFFERENTARCHITECTURESARCHITECTURES

5.65.6

Page 52: chap05. ppt

Two different architectures

• CISC (Complex Instruction Set Computer)– Intel

• RISC (Reduced Instruction Set Computer)– PowerPC