Basic Computer Organization CH-4 Richard Gomez 6/14/01 Computer Science Quote: John Von Neumann If people do not believe that mathematics is simple, it.

Basic Computer Basic Computer Organization CH-4Organization CH-4

Richard GomezRichard Gomez

6/14/016/14/01

Computer ScienceComputer Science

Quote: John Von Neumann

If people do not believe that mathematics is simple,

it is only because they do not realize how complicated life is.

3 Fundamental 3 Fundamental Components of ComputerComponents of Computer

The CPU (ALU, Control Unit, Registers)The CPU (ALU, Control Unit, Registers) The Memory Subsystem (Stored Data)The Memory Subsystem (Stored Data) The I/O subsystemThe I/O subsystem (I/O devices)(I/O devices)

I/O DeviceSubsystem

Address Bus

Data Bus

Control BusCPU Memory

Subsystem

Each of these Components Each of these Components are connected through are connected through

Buses.Buses.

BUS - Physically a set of wires. The BUS - Physically a set of wires. The components of the Computer are components of the Computer are connected to these buses.connected to these buses.

Address BusAddress Bus Data BusData Bus Control BusControl Bus

Address BusAddress Bus

Used to specify the address of the Used to specify the address of the memory location to access.memory location to access.

Each I/O devices has a unique address. Each I/O devices has a unique address. (monitor, mouse, cd-rom)(monitor, mouse, cd-rom)

CPU reads data or instructions from CPU reads data or instructions from other locations by specifying the other locations by specifying the address of its location.address of its location.

CPU always outputs to the address bus CPU always outputs to the address bus and never reads from it.and never reads from it.

Data BusData Bus

Actual data is transferred via the Actual data is transferred via the data bus.data bus.

When the cpu sends an address to When the cpu sends an address to memory, the memory will send memory, the memory will send data via the data bus in return to data via the data bus in return to the cpu.the cpu.

Control BusControl Bus

Collection of individual control signals.Collection of individual control signals. Whether the cpu will read or write Whether the cpu will read or write

data.data. CPU is accessing memory or an I/O CPU is accessing memory or an I/O

devicedevice Memory or I/O is ready to transfer Memory or I/O is ready to transfer

datadata

I/O Bus or Local BusI/O Bus or Local Bus

In today’s computers the the I/O In today’s computers the the I/O controller will have an extra bus controller will have an extra bus called the I/O bus.called the I/O bus.

The I/O bus will be used to access The I/O bus will be used to access all other I/O devices connected to all other I/O devices connected to the system.the system.

Example: PCI busExample: PCI bus

Instruction CyclesInstruction Cycles

Procedure the CPU goes through to Procedure the CPU goes through to process an instruction.process an instruction.

1. Fetch - get instruction1. Fetch - get instruction 2. Decode - interperate the 2. Decode - interperate the

instructioninstruction 3. Execute - run the instruction.3. Execute - run the instruction.

Process of an InstructionProcess of an Instruction(Define fetch)(Define fetch)

When CPU is ready the it will assert the When CPU is ready the it will assert the read control signal.read control signal.

Depending on the CPU the read can be Depending on the CPU the read can be active high (1) or low (0).active high (1) or low (0).

After being asserted the subsystem will After being asserted the subsystem will return the data through the data bus.return the data through the data bus.

The CPU will then receive this data and The CPU will then receive this data and store into one of its registersstore into one of its registers

Process of an InstructionProcess of an Instruction(Define Decode)(Define Decode)

Now the CPU will decode the Now the CPU will decode the instruction.instruction.

The CPU will determine the sequences The CPU will determine the sequences of commands needed to perform.of commands needed to perform.

Each instruction can require different Each instruction can require different sequences of operations.sequences of operations.

This is perform within the CPU with no This is perform within the CPU with no system buses.system buses.

Process of an InstructionProcess of an Instruction(Define Execute)(Define Execute)

The CPU will now execute the The CPU will now execute the instruction.instruction.

This sequence will vary from This sequence will vary from different instructions.different instructions.

Read or write data to memory or Read or write data to memory or I/O subsystem.I/O subsystem.

Timing Diagram:Timing Diagram: Memory Read Memory Read

Address is placed at beginning of clockAddress is placed at beginning of clock after one clock cycle the CPU asserts the read.after one clock cycle the CPU asserts the read. Causes the memory to place its data onto the data bus.Causes the memory to place its data onto the data bus. CLK : System Clock used to synchronizeCLK : System Clock used to synchronize

CLK

AddressBus

Bus

Read

Data

Timing Diagram :Timing Diagram : Memory Write Memory Write

CPU places the Address and data on the first clock cycle.CPU places the Address and data on the first clock cycle. At the start of the second clock the CPU will assert the At the start of the second clock the CPU will assert the

write control signal.write control signal. This will then start memory to store data.This will then start memory to store data. After some time the write is then deasserted by the CPU After some time the write is then deasserted by the CPU

after removing the address and data from the after removing the address and data from the subsystem.subsystem.

CLK

AddressAddress Bus

Data Bus

Read

Data

I/O read and Write CyclesI/O read and Write Cycles

The I/O read and Write cycles are The I/O read and Write cycles are similar to the memory read and write.similar to the memory read and write.

Memory mapped I/O : Same sequences Memory mapped I/O : Same sequences as input output to read and write.as input output to read and write.

The processor treats an I/O port as a The processor treats an I/O port as a memory location.memory location.

This results in the same treatment as a This results in the same treatment as a memory access.memory access.

CPU organizationCPU organization

CPU controls the ComputerCPU controls the Computer The CPU will fetch, decode and The CPU will fetch, decode and

execute instructions.execute instructions. The CPU has three internal The CPU has three internal

sections: register section, ALU and sections: register section, ALU and Control UnitControl Unit

Register SectionRegister Section

Includes collection of registers and a Includes collection of registers and a bus.bus.

Processor’s instruction set architecture Processor’s instruction set architecture are found in this section.are found in this section.

Non accessible registers by the Non accessible registers by the programmer. These are to be used for programmer. These are to be used for registers to latch the address being registers to latch the address being accessed and a temp storage register.accessed and a temp storage register.

Arithmetic/Logic Unit Arithmetic/Logic Unit (ALU)(ALU)

Performs most Arithmetic and Performs most Arithmetic and logical operations.logical operations.

Retrieves and stores its Retrieves and stores its information with the register information with the register section of the CPU.section of the CPU.

Memory SubsystemMemory Subsystem

2 Types of Memory:2 Types of Memory:– ROM : Read Only MemoryROM : Read Only Memory

Program that is loaded into memory and Program that is loaded into memory and cannot be changed also retains its data cannot be changed also retains its data even without power.even without power.

– RAM : Random Access MemoryRAM : Random Access Memory Also called read/write memory. This type Also called read/write memory. This type

of memory can have a program loaded and of memory can have a program loaded and then reloaded. It also loses its data with no then reloaded. It also loses its data with no power.power.

Different ROM ChipsDifferent ROM Chips Masked ROM : Masked ROM :

ROM that is programmed with data when ROM that is programmed with data when fabricated. Data will not change once fabricated. Data will not change once installed. Hardwired.installed. Hardwired.

Programmable ROM (PROM) :Programmable ROM (PROM) : Capable of being programmed by the user Capable of being programmed by the user

with a ROM programmer. Not hardwired.with a ROM programmer. Not hardwired. Erasable PROM (EPROM) :Erasable PROM (EPROM) :

Much like the PROM this EPROM can be Much like the PROM this EPROM can be programmed and then erased by light.programmed and then erased by light.

EEPROM : EEPROM : Another form of EPROM but is Another form of EPROM but is

reprogammable electrically.reprogammable electrically.

Different RAM ChipsDifferent RAM Chips

Dynamic RAM (DRAM) : Dynamic RAM (DRAM) : Leaky capacitors. Caps are charged and Leaky capacitors. Caps are charged and

slowly leak until they are refreshed to there slowly leak until they are refreshed to there original data locations. Ex. Computer RAMoriginal data locations. Ex. Computer RAM

Static RAM (SRAM) :Static RAM (SRAM) : Much like a register. The contents stay valid Much like a register. The contents stay valid

and does not have to be refreshed. SRAM is and does not have to be refreshed. SRAM is faster than DRAM but cost more Ex. Cachefaster than DRAM but cost more Ex. Cache

– Each RAM chip has 2^n * m. n address Each RAM chip has 2^n * m. n address inputs and m bidirectional data pinsinputs and m bidirectional data pins

Internal Memory Internal Memory OrganizationOrganization

ROM and RAM have similar internal organization.ROM and RAM have similar internal organization. Internal linear Organization. Ex. 8 X 2 ROM Chip:Internal linear Organization. Ex. 8 X 2 ROM Chip:

A2

A1

A0 Decoder

01234567

3-8

E

CE

OE D0

0

D1

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

Internal Memory Cont.Internal Memory Cont.

This chip has 3 Address inputsThis chip has 3 Address inputs 2 data outputs2 data outputs 16 bits of internal storage arranged as 8 16 bits of internal storage arranged as 8

2-bit locations2-bit locations The 3 address bits will be decoded to select The 3 address bits will be decoded to select

one of the 8 locations only if CE is active (1).one of the 8 locations only if CE is active (1). With both CE and OE enabled the buffers With both CE and OE enabled the buffers

are enabled and data is allowed to flow out.are enabled and data is allowed to flow out.

Internal Memory Cont.Internal Memory Cont.

As the # of locations increases the As the # of locations increases the size of the address decoder size of the address decoder needed in linear organization needed in linear organization becomes very large.becomes very large.

To get around this problem we can To get around this problem we can use multi-dimensions of decoding.use multi-dimensions of decoding.

The size of an n to 2^n decoder is The size of an n to 2^n decoder is said to be O(2^n)said to be O(2^n)

Memory SubsystemMemory Subsystem Memory subsystem is the Memory subsystem is the

combination of memory chipscombination of memory chips Example : 8 x 2 chips can be Example : 8 x 2 chips can be

combined to make an 8 x 4 combined to make an 8 x 4 memory.memory.

Both chips will receive the same 3 Both chips will receive the same 3 address inputs from the bus, as well address inputs from the bus, as well as the CE and OE signals.as the CE and OE signals.

The data pins of the first chip are The data pins of the first chip are connected to bits 3 and 2 and the connected to bits 3 and 2 and the other to 1 an 0 of the data busother to 1 an 0 of the data bus

Memory Subsystem Cont.Memory Subsystem Cont.

When the CPU reads data it places the When the CPU reads data it places the address on the address bus.address on the address bus.

Both chips will read in bits A1, A2, and Both chips will read in bits A1, A2, and A0 and decodeA0 and decode

Since both chips are using the same CE Since both chips are using the same CE and OE either both chips are active or and OE either both chips are active or not.not.

To the CPU it will act just like an 8 x 4 To the CPU it will act just like an 8 x 4 memory chip.memory chip.

Von Neumann and Von Neumann and Harvard architecturesHarvard architectures

Are similar in implementation using this diagram.Are similar in implementation using this diagram.

They differ in how data is arranged in memory.They differ in how data is arranged in memory. The Neumann uses mixed memory module while The Neumann uses mixed memory module while

the Harvard uses separate memory modules for the Harvard uses separate memory modules for data and instructionsdata and instructions

I/O DeviceSubsystem

Address Bus

Data Bus

Control BusCPU

MemorySubsystem

Von Neumann and Von Neumann and Harvard architecturesHarvard architectures

Modern computers today predominantly use the Modern computers today predominantly use the Neumann architecture.Neumann architecture.

Although it will also use some elements of the Although it will also use some elements of the harvard architecture.harvard architecture.

The difference is the PC will assign sections of The difference is the PC will assign sections of memory to either instructions or data.memory to either instructions or data.

Although this is not a true Harvard architecture Although this is not a true Harvard architecture because that system requires that a memory module because that system requires that a memory module always be assign the same one of the two.always be assign the same one of the two.