Computer Engineering AddSub page 1 Basic Building Blocks Multiplexer + Demultiplexer Adder
Basic Building Blocks
Jan 05, 2016
+. Basic Building Blocks. Adder. Multiplexer. Demultiplexer. The Program Counter. There is a special register inside the processor. Big enough to hold an instruction address (32 bits) . Called the program counter (PC). Zero ext. Branch logic. 0. A. ALU. 4. B. +. 31. +. - PowerPoint PPT Presentation
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Computer Engineering AddSub page 1
Basic Building Blocks
Multiplexer
+
Demultiplexer Adder
Computer Engineering AddSub page 2
The Program Counter
There is a special register inside the processor.
Big enough to hold an instruction address (32 bits).
Called the program counter (PC).
Computer Engineering AddSub page 3
Branch
logic
Sgn/Ze
extend
Zero ext.
ALU
A
B
31
0
4+
+
Computer Engineering AddSub page 4
Fetch - Execute
Fetch:– Send the value in the PC to the instruction memory.
– The instruction memory gives out one instruction.
Execute:– Carry out the fetched instruction.
– Also: PC := PC+4;
Fetch Execute 108 times per second
Computer Engineering AddSub page 5
Branch
logic
Sgn/Ze
extend
Zero ext.
ALU
A
B
31
0
4+
+
Computer Engineering AddSub page 6
Branch
logic
Sgn/Ze
extend
Zero ext.
ALU
A
B
31
0
4+
+
Computer Engineering AddSub page 7
The Register File
32 word (32 bit) registers. r0 is special:
– Read: always zero.
– Write: allowed, but won´t change it.
r31 is special:– Hard-wired return address (lab1).
Computer Engineering AddSub page 8
Branch
logic
Sgn/Ze
extend
Zero ext.
ALU
A
B
31
0
4+
+
Computer Engineering AddSub page 9
Add Instructions
32 bit operands.
Example:– Add rd rs rt.– rd := rs + rt.
There is also:– Addu rd rs rt.
These are not add signed and add unsigned.The “u”-variant ignores overflow.
Opcode rs rt rd
5556
Computer Engineering AddSub page 10
Branch
logic
Sgn/Ze
extend
Zero ext.
Add rd rs rt
ALU
A
B
31
0
4+
+
Computer Engineering AddSub page 11
Branch
logic
Sgn/Ze
extend
Zero ext.
Add rd rs rt
ALU
A
B
31
0
4+
+
Computer Engineering AddSub page 12
Branch
logic
Sgn/Ze
extend
Zero ext.
Add rd rs rt
ALU
A
B
31
0
4+
+
Computer Engineering AddSub page 13
Branch
logic
Sgn/Ze
extend
Zero ext.
Add rd rs rt
ALU
A
B
31
0
4+
+
Computer Engineering AddSub page 14
Branch
logic
Sgn/Ze
extend
Zero ext.
Add rd rs rt
ALU
A
B
31
0
4+
+
Computer Engineering AddSub page 15
Branch
logic
Sgn/Ze
extend
Zero ext.
Add rd rs rt… next instr
ALU
A
B
31
0
4+
+
Computer Engineering AddSub page 16
Sub Instructions
32 bit operands.
Example:– Sub rd rs rt– rd := rs - rt
There is also:– Subu rd rs rt
These are not sub signed and sub unsignedThe “u”-variant ignores overflow
Computer Engineering AddSub page 17
How to Negate
Y := -X?
Sub rd $0 rt ($0 means r0)
rd := 0 - rt
Careful: Neg Not
Computer Engineering AddSub page 18
Compare Instructions
Signed integers:– Slt rd rs rt
– if rs < rt then rd := 1
else rd := 0
Unsigned integers:– Sltu rd rs rt
– if rs < rt then rd := 1
else rd := 0
Computer Engineering AddSub page 19
Immediate Variants
of the arithmetic instructions:
Addi rt rs Imm Addiu rt rs Imm
Slti rt rs Imm Sltiu rt rs Imm
Imm sign-extend No sub instruction
Computer Engineering AddSub page 20
Sign/Zero extension
The immediate field is 16 bits
But most operations work on 32 bits!
Zero extension Sign extension
Immediate
xxxxxxxxxxxxxxxx Immediate0000000000000000 Immediate
Bit 15, the Sign bit, is copied into bits 16 - 31
x
0151631 0151631
Computer Engineering AddSub page 21
Branch
logic
Sgn/Ze
extend
Zero ext.
ALU
A
B
31
0
4+
+
Computer Engineering AddSub page 22
Branch
logic
Sgn/Ze
extend
Zero ext.
Addi rt rs Imm
ALU
A
B
31
0
4+
+
Computer Engineering AddSub page 23
Branch
logic
Sgn/Ze
extend
Zero ext.
Addi rt rs Imm
ALU
A
B
31
0
4+
+
Computer Engineering AddSub page 24
Branch
logic
Sgn/Ze
extend
Zero ext.
Addi rt rs Imm
ALU
A
B
31
0
4+
+
Computer Engineering AddSub page 25
Branch
logic
Sgn/Ze
extend
Zero ext.
Addi rt rs Imm
ALU
A
B
31
0
4+
+
Computer Engineering AddSub page 26
Branch
logic
Sgn/Ze
extend
Zero ext.
Addi rt rs Imm… next instr
ALU
A
B
31
0
4+
+
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