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Atmel 11121S 32 Bit Cortex A5 Microcontroller SAMA5D3 Summary Datasheet

Nov 03, 2014

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ARM-based Embedded MPUSAMA5D3 SeriesSUMMARY DATASHEET

DescriptionThe Atmel SAMA5D3 series is a high-performance, power-efficient embedded MPU based on the ARM Cortex -A5 processor, achieving 536 MHz with power consumption levels below 0.5 mW in low-power mode. The device features a floating point unit for high-precision computing and accelerated data processing, and a high data bandwidth architecture. It integrates advanced user interface and connectivity peripherals and security features. The SAMA5D3 series features an internal multi-layer bus architecture associated with 39 DMA channels to sustain the high bandwidth required by the processor and the high-speed peripherals. The device offers support for DDR2/LPDDR/LPDDR2 and MLC NAND Flash memory with 24-bit ECC. The comprehensive peripheral set includes an LCD controller with overlays for hardware-accelerated image composition, a touchscreen interface and a CMOS sensor interface. Connectivity peripherals include Gigabit EMAC with IEEE1588, 10/100 EMAC, multiple CAN, UART, SPI and I2C. With its secure boot mechanism, hardware accelerated engines for encryption (AES, TDES) and hash function (SHA), the SAMA5D3 ensures anti-cloning, code protection and secure external data transfers. The SAMA5D3 series is optimized for control panel/HMI applications and applications that require high levels of connectivity in the industrial and consumer markets. Its lowpower consumption levels make the SAMA5D3 particularly suited for battery-powered devices. There are four SAMA5D3 devices in this series. Table 1-1 SAMA5D3 Devices shows the differences in the embedded features. All other features are available on all derivatives; this includes the three USB ports as well as the encryption engine and secure boot features.

This is a summary document. The complete document is available on the Atmel website at www.atmel.com.

11121BSATARM08-Mar-13

1.

FeaturesCore ARM Cortex-A5 Processor with ARM v7-A Thumb2 Instruction Set CPU Frequency up to 536 MHz 32 Kbyte Data Cache, 32 Kbyte Instruction Cache, Virtual Memory System Architecture (VMSA) Fully Integrated MMU and Floating Point Unit (VFPv4) Memories One 160 Kbyte Internal ROM Single-cycle Access at System Speed, Embedded Boot Loader: Boot on NAND Flash, SDCard, eMMC, serial DataFlash, selectable Order One 128 Kbyte Internal SRAM, Single-cycle Access at System Speed High Bandwidth 32-bit Multi-port Dynamic Ram Controller supporting 512 Mbyte 8 bank DDR2/LPDDR/LPDDR2 Independent Static Memory Controller with SLC/MLC NAND Support with up to 24-bit Error Correcting Code (PMECC) System running up to 166 MHz Power-on Reset Cells, Reset Controller, Shut Down Controller, Periodic Interval Timer, Watchdog Timer and Real-time Clock Boot Mode Select Option, Remap Command Internal Low-power 32 kHz RC Oscillator and Fast 12 MHz RC Oscillators Selectable 32768 Hz Low-power Oscillator and 12 MHz Oscillator One 400 to 1000 MHz PLL for the System and one PLL at 480 MHz optimized for USB High Speed 39 DMA Channels including two 8-channel 64-bit Central DMA Controllers 64-bit Advanced Interrupt Controller Three Programmable External Clock Signals Programmable Fuse Box with 256 fuse bits, 192 of them available for Customer Low Power Management Shut Down Controller Battery Backup Registers Clock Generator and Power Management Controller Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities Peripherals LCD TFT Controller with Overlay, Alpha-blending, Rotation, Scaling and Color Space Conversion ITU-R BT. 601/656 Image Sensor Interface Three HS/FS/LS USB Ports with On-Chip Transceivers One Device Controller One Host Controller with Integrated Root Hub (3 Downstream Ports) One 10/100/1000 Mbps Gigabit Ethernet Mac Controller (GMAC) with IEEE1588 support One 10/100 Mbps Ethernet Mac Controller (EMAC) Two CAN Controllers with 8 Mailboxes, fully Compliant with CAN 2.0 Part A and 2.0 Part B Softmodem Interface Three High Speed Memory Card Hosts (eMMC 4.3 and SD 2.0) Two Master/Slave Serial Peripheral Interface Two Synchronous Serial Controllers Three Two-wire Interface up to 400 Kbits supporting I2C Protocol and SMBUS Four USARTs, two UARTs, one DBGU Two Three-channel 32-bit Timer/Counters

SAMA5D3 Series [SUMMARY DATASHEET]11121BSATARM08-Mar-13

2

One Four-channel 16-bit PWM Controller One 12-channel 12-bit Analog-to-Digital Converter with Resistive Touch-Screen function Write Protected Registers Security TRNG: True Random Number Generator Encryption Engine AES: 256-bit, 192-bit, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications TDES: Two-key or Three-key Algorithms, Compliant with FIPS PUB 46-3 Specifications SHA: Supports Secure Hash Algorithm (SHA1, SHA224, SHA256, SHA384, SHA512) Atmel Secure Boot Solution I/O Five 32-bit Parallel Input/Output Controllers 160 I/Os Input Change Interrupt Capability on Each I/O Line, Selectable Schmitt Trigger Input Individually Programmable Open-drain, Pull-up and Pull-down Resistor, Synchronous Output, Filtering Slew Rate Control on High Speed I/Os Impedance Control on DDR I/Os Package 324-ball LFBGA, pitch 0.8 mm

Table 1-1.

SAMA5D3 Devices SAMA5D31 SAMA5D33 X X X X X X X X SAMA5D34 X X X X X X X X X SAMA5D35

LCDC GMAC EMAC CAN0, CAN1 HSMCI2 UART0 UART1 TC1

X

SAMA5D3 Series [SUMMARY DATASHEET]11121BSATARM08-Mar-13

3

2.

Block Diagram

Figure 2-1. SAMA5D3 Block DiagramDH S DH DP SD /HH M/ SD HH PA G1 SD 25 MA GT CK -G GTXCK 12 XE -G 5CK GC N RX -G C O GRRS, TX K X G E GR ER CO R - L GT X0- GRX X GR D GM 0-G X7 V D TX7 ER C, G EF MD ET C X K IO EC EN R ER SD V E T X 0- E , E R X 0 R XE EM -ET X1 R DC X1 ,E LC MD LCD-D D_ AT0 IO LC V -L D_ SY CD LC PC NC _ D_ K , L DA DE , LC CD T23 N, D_ _H LC D S IS I_D D_ ISP YN C PW IS OI_P IS M IS CK I_D1 I_H 1 SY NC , IS I_V SY NC DD R_ CA LP DD R_ CA LN

NT RS T TD I TD O TM TC S/SW K/S D WC IO LK JTA GS EL

TST

BMS

HH S HH DPC SD H H MC HH SDP SD B MB VB G

SysCFIQ IRQ

JTAG / SWDAICIn-Circuit Emulator

HS Trans

HS Trans

HS Trans

PIO

DDR_VREF DDR_A0-DDR_A13 DDR_D0-DDR_D31 DDR_DQM[3..0] DDR_DQS[3..0]

PIO

DRXD DTXD PCK0-PCK2

DBGU

PC PB

PA HS USB Device DMA GMAC 10/100/1000 EMAC 10/100 LCD ISI

Cortex-A5PLLA PLLUTMIICache 32 KB MMU BIU

VFP DCache 32 KB

HS EHCI USB HOST DMA

DDR2 LPDDR2 512 MB

XIN XOUT

Osc12 MHz

PMC

DMA

DMA

DMA

DMA

12 MHZ RC Osc WDT RCXIN32 XOUT32 SHDN WKUP VDDBU NRST OSC 32K

I/DPIT4 GPBR EBI

DDR_DQSN[3..0] DDR_CS DDR_CLK,DDR_CLKN DDR_CKE DDR_RAS, DDR_CAS DDR_WE DDR_BA[2..0] D0-D15 A21/NANDALE A22/NANDCLE NRD/NANDOE NWE/NWR0/NANDWE NCS3/NANDCS NANDRDY A0/NBS0 A1-A20 A23-A25 NWR1/NBS1 NCS0,NCS1,NCS2 NWAIT

Multi-Layer MatrixRTC RSTCTRNG SHA AES TDES DMA

SHDC POR POR PIOA PIOC PIOE

NAND Flash Controller MCL/SLC ECC (4 KB SRAM)

PIOB PIOD

ROM 160 KB

SRAM0 64 KB

SRAM1 64 KB

8-CH DMA0

8-CH DMA1

Peripheral Bridge

Reduced Static Memory Controller

PIO

DMA CAN0 CAN1 TWI0 TWI1 TWI2

DMA USART0 USART1 USART2 USART3

DMA

DMA SPI0 SPI1

DMA SSC0 SSC1

DMA MCI0/MCI1/MCI2 SD/SDIO eMMC TC0, TC1 TC2, TC3 TC4, TC5

DMA 4-CH PWM

UART0 UART1

Real-time Events

DMA 12-CH 12-bit ADC TouchScreen SMD

PIO

PN CA RX NT 0-C X0 A -C NR A X TW NT 1 TW D0 X1 CK -TW 0TW D2 CK CT 2 S RT 03 SCS03 RDK0X 3 TX 0-3 UR D0 D -3 UT X0NP UR XD CS DX 0 1, NP -UT 1 XD CS 1 2, NP C NP S3 C SP S0 C M K O M SI TK ISO 0 TF -TK TD 0-T 1 F RD 0-T 1 0 D RF -RD1 0 1 RK -RF 0 1 M -RK CI 1 M 0_C C M I1_ DA CI C 2 D M _C A C D M I0_ A CI C M MC 1_CK CI I K M 0_D 2_C CI A K M 1_D [7..0 CI A ] 2 [ TI _D 3..0 O A ] TI A0 [3.. O -T 0] TC B0 IO -T A PW LK0 IOB5 M -TC 5 LK PW H0 5 PW ML PW M 0-P MH FI W 3 0- M PW L3 M TS FI AD 3 TR IG AD 0 AD UL 1 AD UR 2 AD LL GP 3 AD A LR 5- D4 G P TS PAD I AD 11 VR EF

DIB

SPI0_, SPI1_

CA

SAMA5D3 Series [SUMMARY DATASHEET]11121BSATARM08-Mar-13

DI

BN

4

3.

Signal DescriptionTable 3-1 gives details on the signal names classified by peripheral.Signal Description List Function Type Active Level Frequency (MHz) Comments

Table 3-1.

Signal Name

Clocks, Oscillators and PLLs XIN XOUT XIN32 XOUT32 VBG PCK0 - PCK2 Main Oscillator Input Main Oscillator Output Slow Clock Oscillator Input Slow Clock Oscillator Output Bias Voltage Reference for USB Programmable Clock Output Input Output Input Output Analog Output

Shutdown, Wake-up Logic SHDN WKUP Shut-Down Control Wake-Up Input ICE and JTAG TCK/SWCLK TDI TDO TMS/SWDIO JTAGSEL Test Clock/Serial Wire Clock Test Data In Test Data Out Test Mode Select/Serial Wire Input/Output JTAG Selection Reset/Test NRST TST NTRST BMS Microcontroller Reset Test Mode Select Test Reset Signal Boot Mode Select I/O Input Input Input Debug Unit - DBGU DRXD DTXD Debug Receive Data Debug Transmit Data Input Output Advanced Interrupt Controller - AIC IRQ FIQ External Interrupt Input Fast Interrupt Input Input Input Low Input Input Output I/O Input Output Input

PIO Controller - PIOA - PIOB - PIOC - PIOD - PIOE PA0 - PAxx PB0 - PBxx PC0 - PCxx PD0 - PDxx PE0 - PExx Parallel IO Controller A Parallel IO Controller B Parallel IO Controller C Parallel IO Controller D Parallel IO Controller E I/O I/O I/O I/O I/O

SAMA5D3 Series [SUMMARY DATASHEET]11121BSATARM08-Mar-13

5

Table 3-1.

Signal Description List (Continued) Function Type Active Level Frequency (MHz) Comments

Signal Name

External Bus Interface - EBI D0 - D15 A0 - A25 NWAIT Data Bus Address B