Arm9 Ucos Ii

- 1 - 임베디드 시스템 교육센터

교육 목표 및 대상

교교 육육 목목 표표

Real-Time OS와 ARM9의 이해

Real-Time OS 시스템을직접 작성해보는 개발 경험 축적

임베디드 시스템 개발자의 능력 배가

대대 상상

프로그램 언어(ASM,C)사용 가능자 및 임베디드시스템 개발 경험자

Real-Time OS나 ARM에 대한 개념을 공부하고자 하는 개발자, 연구책임자 및 학생


교육 구성

학학 습습

RTOS의 이해

uC/OS-II의 이해

ARM920T의 이해

S3C2410의 이해

실실 습습

SMDS2410 시스템 실습

ARM9 프로세서 제어

uC/OS - ARM9 포팅

RTOS 태스크 모델링


RTOS 개념



OS 란?

Operating System의 약자

사전적 의미 : 효율적 조작을 목적으로 하는 제어 프로그램

일반 응용 프로그램들이 각자의 작업을 수행하기 위해 시스템 자원을 요구 할 때 서로 간의충돌 없이 효율적으로 사용할 수 있도록 자원을 관리하고 프로그램들의 작업 명령을 받아서처리 하는 시스템 소프트웨어

Ex) DOS, Windows 98/NT, Mac OS, UNIX, Linux, OS/2…


RTOS 란?

Real-Time Operating System의 약자

Real-Time Concepts 상대적인 관점임(vs. 일반적인 OS 처리)

극히 짧은 시간 내에 제공되어야 하는 서비스는DSP나 ASIC 등으로 특화 되어 H/W Real-Time으로 분류

일반적 의미 : 주어진 제약 시간 안에 할당된 일을처리할 수 있는 S/W Real-Time을 의미

Cf) Hard real-time, Soft real-time

RT Systems : 제어 시스템에서, 요구하는 시간 내에 결과를 출력하는 시스템


RTOS 시스템의 구조

H/W

S/WOS

Device Driver

Application

(Task)

Application

(Task)

Memory

Management

Comm.

Management

Task

Management

Time

Management

KernelScheduler


RTOS의 적용 분야

RTOS는 여러 시스템에 적용되나 특히 임베디드 시스템에 많이 사용됨

일반 OS 시스템 설계보다 디자인이 더 어려움

시간 제약이 있는 시스템에 사용영상, 의료, 음향 기계 등의 시간 의존적 시스템

흐름 제어, 엔진제어, 로봇 등의 자동화 시스템

복합 기능의 가전 기기 등

네트워크 접속, 고성능 전화 설비 등 통신 시스템


프로그래밍 방식 분류

순차적 단순 프로그래밍간단한 제어 시스템에 유리

Ex) Foreground/Background 방식

OS를 기반으로 한 프로그래밍일반적으로 큰 프로그램에 유리

프로그램의 모듈화가 용이함

Scheduler를 이용한 Multi-Task가 가능함

메모리/IO 등의 자원 관리가 쉬움

OS에 필요한 overhead(메모리, CPU 등) 존재

Ex) Dos, WinCE, pSOS, VxWorks, Embedded Linux, Nucleus, Xinu, IOS, uC/OS, eCOS 등


Foreground/Background

Background : Function을 이용하여원하는 기능을 불러 프로그램을 무한 수행하는 것

Foreground : 인터럽트에 의해ISR(Interrupt Service Routine)을 수행하는것


OS Based Programming

일반 Embedded OS 기반PC와 같이 시간적으로 처리지연이 발생해도 문제가 없으며, 다양한 App. S/W가 지원되는 경우 유리

WinCE : 친숙한 개발환경, License, Guarantee…Embedded Linux : Free, 개발 환경 구축 필요

Real-Time OS 기반정확한 처리시간이 필요한 임베디드 시스템에 적합

VxWorks : License, Guarantee…RTLinux : 일반 리눅스 커널의 Scheduler를 변경

In-house RTOS(자체 개발한 OS) : RTOS 시장의50%이상으로 유료 or 무료


OS 기본 개념

Task, Resource, Event

Critical Section, Mutual Exclusion, Deadlock

Multi-Tasking, Context Switching

Kernel, Scheduler

Non-Preemptive, Preemptive

Priority, CPU Utilization

Synchronization

Inter-task Communication

Reentrancy

Interrupts, Clock Tick


Task, Resource, Event

Task= Thread

하나의 간단한 프로그램으로 CPU를 사용하는 작업

각각의 우선순위, 스택 영역을 가짐

Resource 태스크가 사용하는 Entity(프로세서, I/O, 메모리 등)

Shared Resource여러 Task에 의해 공용되는 자원

EventTask에게 작업을 시작하도록 지시할 수 있는 상황

신호나 메시지를 주고 받음


Critical Section, Mutual Exclusion

Critical Section여러 Task 들이 공유 자원에 접근하는 코드 부분

Mutual Exclusion오류 방지를 위해 배타적으로 공유 자원을 사용함

방법 : Test & Set, Scheduler 정지, Semaphore 등

Deadlock공유 자원 문제로 Task들이 서로 끝없이 기다리게되는 상태를 말함

주로 대규모 Multi-Task Kernel에서 일어남

해결책 : 사전 자원 점유, 자원 해제 순위, Semaphore 등의 사용


Multi-tasking

정확히는 Multi-programming

Scheduling을 통하여 Task를 전환하여 여러작업들이 동시에 수행되는 것처럼 보이게 하는것

모듈 구조의 Application을 제공

실시간 Application에서의 복잡성을 줄여줌

CPU의 활용도를 극대화

한 순간에 한 개의 Task 만이 수행 될 수 있으므로 다른 Task는 대기 준비 모드


Context Switching

Multi-task가 가능하도록 Task를 바꾸기 위한교환 과정

다른 Task를 수행하기 위해 현재 수행 중인Task의 Context를 스택에 저장

새로운 태스크의 Context를 불러들임

실제 작업을 위한 시간이 아니므로 Overhead

* Context : CPU Register, Stack 등의 자원


Kernel

OS 핵심 기능의 집합체

Task간의 Communication, Task 관리를 위한Multi-tasking 시스템 관리자

Context Switching과 같은 기본적인 서비스를제공

CPU 사용률 향상을 위해 필수적으로 필요한세마포어, 메일박스, 메시지큐, Time Delay등의 통신 방식 제공

선점, 비선점 커널


Scheduler

다음 수행할 작업을 결정하는 커널의 한 부분

대부분의 실시간 커널은 우선순위에 기반배타적 우선순위 방식

동일 우선순위 허용 방식

Kernel이 어떠한 Scheduling 방식을 채택했는가에 따라 분류

Non-Preemptive Kernel

Preemptive Kernel

Ex) Time Slice, Round-Robin, FIFO, EDF...


Non-Preemptive Kernel

현재 진행중인 프로세스가 CPU 사용을포기하기 전까지는다른 프로세스가 진입할 수 없는 구조

장점 : 짧은Interrupt Latency

단점 : 나쁜 Task-Level Response


Preemptive Kernel

높은 우선순위의 Task가 언제라도 CPU의 제어권을 넘겨 받을 수 있도록 대기

거의 모든 Real-time 시스템의 체제가 선점 커널을사용

장점 : Deterministic

단점 : 자원 관리에 복잡한알고리즘이 필요


Priority

Task 처리의 우선 순위를 뜻함Static Priorities : 컴파일 시에 결정되어 프로그램수행 중에 바꿀 수 없는 우선순위 방식

Dynamic Priorities : 프로그램 수행 중에 우선 순위가 바뀔 수 있음

Priority Inversion Problem : Real-Time Kernel에서 많이 발생되는 문제

T A S K 1 (H )

T A S K 2 (M )

T A S K 3 (L )( 1 )

( 2 ) ( 3 )

( 4 )

( 5 )

( 6 )

( 7 )

( 8 )

( 9 )

( 1 0 )

( 1 1 )

( 1 2 )

우 선 순 위 역 전


CPU Utilization

일반적으로 높은 우선순위의 작업이 작업 실행횟수가 더 많음


Reentrancy

코드의 재진입 가능 여부를 나타냄

1개 이상의 Task가 동작할 때 공유자원을 오류 없이사용할 수 있는 함수


Synchronization

Synchronization : Event 발생을 생성하거나기다리게 하여 작업의 시작을 맞추거나 알려주는 것

Semaphore등으로 신호를 전달할 수 있음


Event Flags

여러 Event가 발생하였을 때 Task의 동기화를 위한 장치

Disjunctive Sync. : Task 가 어떠한 Event 에도 반응하여 동기화되는 것

Conjunctive Sync. : 모든 Event가 다 발생해야지 동기화 되는 것


Inter-task Communication

= IPC(Inter Process Communication)

Task 혹은 ISR이 다른 Task 들과 정보 교환을목적으로 통신하는 것

보통 전역 데이터나 메시지 전달 방식을 사용

전역 변수 사용시 접근의 배타성 확보 필요

통신 방법Semaphore, Mutual Exclusion (MUTEX)

Mailbox, Message Queue

Event Flags


Interrupts

하드웨어 메커니즘

불특정한 시간에 발생하는 Event에 대해 ISR을 만들어 이를 처리할 수 있게 CPU 할당을 해주는 서비스

실시간 시스템에서는 가능한 한 Interrupt Disable Time이 적도록 해야 함

Interrupt Nesting

Interrupt Latency, Response, Recovery

NMI(Non-maskable Interrupts)


Clock Tick

주기적인 특별한 인터럽트로 시스템의 심장

간격은 10~200ms사이

주기가 짧을수록 시스템에 부하를 많이 줌


uC/OS-II



uC/OS 란?

Jean J. Labrosse의 저서인 “The Real-Time Kernel”에 속한 부록

Code가 몇 개의 파일로 되어 있는가장 간단한 구조의 RTOS임

도서와 같이 제공되어 RTOS의 학습에 적합

최근 License를 부여하고 있으나학습용에는 필요 없음

uC/OS-II가 상용 소프트웨입니다.

국내 라이센스 진행 절차는 디오이즈에서 수행합니다. (www.dioiz.com)


특징(1/2)

코드의 대부분이 이식이 가능한 C로 구성

임베디드 시스템을 위해 OS의 ROM화 가능

옵션설정으로 메모리(ROM, RAM 등)의 크기조정 가능

선점형 실시간 커널로서 동작하므로 높은 우선순위 태스크의 응답시간이 빠름

64개까지의 Multitasking 가능(8개는 시스템이사용)

기능이나 서비스의 실행시간 예측 가능


특징(2/2)

Task의 Stack 크기를 각기 다르게 설정 가능

Stack 체크 기능이 있음

IPC(Event Flag, Mailbox, Message Queue, Semaphore, Mutex) 제공

Fixed-sized memory partition

Time-related function

255레벨의 Nesting Interrupts 가능

파일 시스템, Network에 대한 기본적인 지원이되지 않음 3rd Party지원 or 유료 구현가능


uC/OS-II 개요

Kernel StructureTask, 스케줄링, 인터럽트, 시스템 초기화 등

Task ManagementTask 의 생성, 우선순위 변경 등

Time ManagementTask 의 Tick 카운터 관리 등

Intertask CommunicationISR, 공유자원 간의 내부적 통신(IPC) 등

Memory Management동적메모리 할당, 고정 메모리 블록 등

Porting


Kernel Structure

Critical Section

Tasks, Task State, Task Control Block

Ready List

Task Scheduling

Locking and Unlocking the Scheduler

Interrupt under uC/OS-II

Idle Task, Statistics Task, Clock Tick

uC/OS-II Initialization

Starting uC/OS-II


Kernel Structure - Critical Section

uC/OS-Ⅱ에서는 코드의 critical sections에 접근할 때 disable/enable interrupts 방법을 사용하여 보호

disable/enable interrupt를 위해 2개의 macros 지원

OS_ENTER_CRITICAL( )

OS_EXIT_CRITICAL( )

상기의 Macro는 processor specific하므로 OS_CPU.H 에서 포팅 필요


Kernel Structure - Critical Sections : example

x86에서의 인터럽트 Enable/Disable의 예

Method 1

#define OS_ENTER_CRITICAL( ) asm CLI

#define OS_EXIT_CRITICAL( ) asm STI

a total of 4 cycles

Method 2

#define OS_ENTER_CRITICAL( ) asm PUSHF；CLI

#define OS_EXIT_CRITICAL( ) asm POPF

OS_ENTER_CRITICAL : 12 clock cycles

OS_EXIT_CRITICAL : 8 clock cycles


Kernel Structure - Task States(1/3)

WAITING

DORMANT

READY RUNNING

ISR

OSMBoxPost()OSQPost()OSPostFront()OSSemPost()OSTaskRusume()OSTaskDlyResume()OSTimeTick()

OSMBoxPend()OSQPend()OSSemPend()OSTaskSuspend()OSTimeDly()OSTimeDlyHMSM()

OSTaskDel()

OSTaskDel()

OSTaskCreate()OSTaskCreateExt()

Preempted

OSStart()OSIntExit()

OS_TASK_SW()

Interrupt

OSIntExit()



DORMANTTask가 ROM 또는 RAM에 있는(살아 있지 않은 ?) 상태

스스로 or 다른 Task에 의해 Delete된 상태

READY수행되어야 할 Task들이 등록된 상태

mulitasking은 OSStart()에 의해 시작

OSStart()에 의해 높은 우선순위 Task가 실행되기위해 스케쥴링

RUNNING하나의 task 만이 RUN 상태



WAITINGTask가 delay되면 WAITING 상태

Timer가 expire 될 수도 있고, Ready 상태로 갈 수도 있다.

ISRRUNNING 상태의 Task는 인터럽트 가능

하나 이상의 Event에 대한 Task들을 실행 준비함

모든 task가 event나 time to expire(delay)를 대기


Kernel Structure - Task States : After OSInit()

0[0]0[1]0[2]000

0

[63]

0

[62]

0[61] 0

**

.

.

.

.

.

.

.

[3]

OSTCBStkptr

OSRCBStkBottom

OSTCBNextOSTCBPrev

OSTCBStkptr

OSRCBStkBottom

OSTCBNextOSTCBPrev

OSTCBPrioTbl[]

OS_TCB OS_TCB

OS_TaskStat() OS_TaskIdle()

Task Stack Task Stack

OSTCBList

00


Kernel Structure - OS_TCB Free List

OS_TCB OS_TCB OS_TCB

OSTCBFreeList 0

OS_MAX_TASKS


*OSTCBExtPtr*OSTCBStkBottom

OSTCBStkSizeOSTCBOpt

OSTCBId*OSTCBNext*OSTCBPrev

*OSTCBEventPtr

*OSTCBEventPtr*OSTCBMsg

OSTCBDlyOSTCBStatOSTCBPrio

OSTCBXOSTCBY

OSTCBBitXOSTCBBitY

*OSTCBStkPtrvoid

OS_STKINT32UINT16UINT16U

os_tcbos_tcb

OS_EVENT

OS_STK

voidOS_STK

INT8UINT8UINT8UINT8UINT8UINT8U

OS_EVENT

Kernel Structure - OS_TCB Data Structure(1/5)



OSTCBStkPtr이 Task의 마지막 top-of-stack을 표시함

Stack 크기는 각각 조절 가능

Structure entry의 처음에 위치함

OSTCBExtPtr확장된 TCB에 대한 사용자 정의된 곳의 Pointer

uC/OS-II의 코드 변경 없이 확장된 TCB 사용 가능

사용법 : OS_TASK_CREATE_EXT_EN = 1



OSTCBStkBottomStack의 bottom을 표시

00::0

Low Memory

High Memory

Free Stack Size

Stack Growth

Deepest Stack Growth

OSTCBStkBottom

Initial TOS

Current Location of Stack Pointer

Used Stack Space

OSTCBStkSize



OSTCBStkSizeOSTaskStkChk()에서 사용할 정보

OS_TASK_CREATE_EXT_EN=1일 경우만 사용가능

OSTCBOptOSTaskCreateExt()으로 전달될 Option 정보

OS_TASK_CREATE_EXT_EN=1일 경우만 사용가능



OSTCBNext, OSTCBPrevDouble link OS_TCBs

각 Task의 OSTCBDly 필드를 update할 때 사용할 chain임

Task가 생성, 삭제될 때 이 Linked List에 적용됨


Kernel Structure - Ready List(1/2)

각 Task는 실행되기 위에 OSRdyGrp and OSRdyTbl[] 에 등록됨

OSRdyTbl[]Table of tasks which are ready to run.

INT8U OSRdyTbl[OS_LOWEST_PRIO/8 + 1]

OSRdyGrpEach bit represents a group

INT8U OSRdyGrp

그룹당 8개의 task를 가지고 있고, OSRdyTbl[ ]의 각bit들은 task들에 대응

Ex. ) Bit i in OSRdyGrp is 1 when any bit in SRdyTbl[i] is 1.


Kernel Structure - Ready List(2/2)


Kernel Structure - Bit Map table

INT8U const OSMapTbl[]

/* Priority->Bit Mask lookup table */

INT8U const OSUnMapTbl[]

/* Priority->Index lookup table */

Contents of OSMapTbl[]index Bit Mask(Binary)

0 000000011 000000102 000001003 000010004 000100005 001000006 010000007 10000000


Kernel Structure - Scheduling

uC/OS_II 항상 가장 높은 우선 순위의 Task를실행

scheduler : 가장 높은 우선 순위의 Task를 선정 작업

OSSched(): Task-level scheduling

OSIntExit(): ISR-level scheduling


Kernel Structure - Locking and Unlocking

OSSchedLock()이상의 scheduling을 방지함

호출된 이후에는 현재 Task를 suspend 시킬 수 없음

Ex: OSMboxPend(), OSTimeDly()…

OSSchedLock()과 OSSchedUnLock() 은 항상 pair로 사용

OSLockNestingOSSchedLock() 이 불린 회수를 표시

OSLockNesting = 0 이면 scheduling이 가능한 상태임


Kernel Structure - Steps of OSSched()

Step1 : OSSched()가 ISR (i.e.,OSIntNesting > 0)이나 scheduling disabled (i.e., OSLockNesting > 0)상태인지 체크하여 맞다면, OSSched() 빠져나감

OSIntNesting is incremented in OSIntEnter().

OSLockNesting is incremented when your application called OSSchedLock() at least once.

Step2 : 아니면, Ready List 중 가장 높은 우선 순위의Task를 실행 준비함

Step3 : 가장 높은 우선 순위 Task가 현재의 것인지 체크

Step4 : 아니면, OS_TASK_SW() 를 호출하여 context switching 시작


Kernel Structure - Idle Task

μC/OS-Ⅱ는 항상 하나의 Task는 수행 중이어야 하므로 실제 일을 하지 않는 Task를 하나 수행함

OS_LOWEST_PRIO : 이 Idle Task의 우선순위는 가장낮음

OSIdleCtr : Idle Task가 수행되면 계속 이 값을 증가시키고 프로그램의 CPU 사용률 측정에 사용

void OSTaskIdle (void *pdata) {pdata = pdata; for (;;) {

OS_ENTER_CRITICAL();OSIdleCtr++;OS_EXIT_CRITICAL();

}}


Kernel Structure - Statistic Task

OSTaskStat( )OS_TASK_STAT_EN = 1로 설정하면 사용가능

매 초마다 값을 계산함

OSCPUUsagesigned 8-bit integer 값으로 실제 값

프로그램에서 사용한 CPU Time을 %로 표시

OSIdleCtrMax : 지금까지 중 최대 사용값 표시

OSStatInit( )위의 statistic task를 사용하기 위해서는 이 함수를초기에 호출하여 설정하여야 함

)1(100(%) axOSIdleCtrMOSIdleCtrOSCPUUsage −=


Kernel Structure - ISRs under µC/OS-Ⅱ

YourISR:Save all CPU register;

Call OSIntEnter() or, increment OSIntNesting directly;

Execute user code to service ISR;

Call OSIntExit();

Restore all CPU registers;

Execute a return from interrupt instruction;


Kernel Structure - Servicing an INT.

TASK TASK

TASK

Task ResponseInterrupt disabled

Interrupt Response

Vectoring

Saving Context

Notify kernel User ISR code Notify kernel

Restore Context

Return from interrupt

Interrupt RecoveryInterrupt Request

ISR signals a taskNew HPT

Interrupt RecoveryTask Response

No New HPT Or OSLockNesting>0

Return from interrupt

Notify kernel

Restore Context


Kernel Structure - OSIntEnter()

OS에게 인터럽트에 진입함을 알려주기 위하여OSIntEnter() 함수를 호출함

전역 변수인 OSIntNesting 를 증가하여interrupt nesting을 표현

void OSIntEnter (void){

OS_ENTER_CRITICAL();OSIntNesting++;OS_EXIT_CRITICAL();

}


Kernel Structure - OSIntExit()

ISR이 끝나면 OSIntExit() 를 호출하여 interrupt nesting counter값을 감소시킴

nesting counter = 0이면 인터럽트가 끝났으므로OS는 최상위 Task를 실행시키기 위해scheduling을 함

최상위 Task가 실행준비가 되면 인터럽트에서실행할 Task로 진입


Kernel Structure - OSIntCtxSw()

Why not using OS_TASK_SW()?

인터럽트 수행시 이미 CPU register 등을 저장하였으므로 일의 양을 줄일 수 있음

OSIntCtxSw() 는 단순히 processor의 stack pointer(SP) 만 조정하면 됨


Kernel Structure - The stack frame

High Memory

Processor Status Word

Interrupt Return Address

Saved Processor Registers

Return Address to caller of OSIntExit()

Processor Status Word

Return address to caller of OSIntCtxSw()

LOW MEMORY

1

2

3

45

SP Points Here!

SP must be adjusted to point here.

This new SP is saved into the preempted task’s OS_TCB.


Kernel Structure - Clock Tick

시스템의 심장인 Clock Tick은 특별한 주기Timer Interrupt로서 사용

전형적으로 10 ~ 200ms를 주기로 사용함(PC의 경우 default tick rate = 18.20648Hz)

A tick source:A hardware timer

AC power line(50/60HZ) signal

Ticker interrupts는 multitasking이 시작된 이후에 Enable 해야 함(crash 방지)


Kernel Structure - Delayed Tick

20ms

Tick Interrupt

Tick ISR

All HigherPriority Tasks

Delayed Task

19ms 17ms 27ms

높은 우선 순위의 Task나 ISR을 실행시키기 위해 1Tick Delay가 필요할 수 있음


Kernel Structure - Tick Code

void main(void){

.OSInit(); /*initialize uC/OS-II*/..

/* Application initializaztion code.... Create at least one task by calling OSTaskCreate() */..

Enable TICKER interrupts; /* DO NOT DO THIS HERE!! */..

OSStart(); /*starting Multitasking*/}


Task Management(1/2)

최대 64개의 TASK를 관리최상위, 최하위 우선순위의 TASK 4개씩 : 시스템용

각각의 Task는 Return Type과 Argument를 가지고있지만 Return값을 전달하지 않음

void yourTask(void *pdata){for(;;){

/* User Code */Osxxxx();

/* User Code */}

}

void yourTask(void *pdata){for(;;){

/* User Code */OSTaskDel(OS_PRIO_SELF);

}}

무한 반복형 Task 1회 수행형 Task


Task Management(2/2)

Task Creation

Task Deletion

Change a Task’s Priority

Suspend and Resume a Task

Obtain Information about a Task


Task Management - Task Creation

TASK들은 Multitasking의 시작 전이나 다른TASK에 의해 생성

스택도 같이 생성이 되며, 스택 영역은 C 컴파일의 malloc()과 같은 기능의 함수로 동적 할당 가능

ISR(Interrupt Service Routine)에서는 TASK를생성할 수 없음

Two functions for creating a task :OSTaskCreate()

OSTaskCreateExt()


Task Management - OSTaskCreate()

Format : OSTaskCreate(*task, *pdata, *ptos, prio)

task : A pointer to the task's code

pdata : A pointer to an argument that is passed to your task when it starts executing.

ptos : A pointer to the task's top of stack.

prio : The task's priority.

ReturnsOS_NO_ERR : if the function was successful.

OS_PRIO_EXIT : if the task priority already exist

OS_PRIO_INVALID : if the priority you specify is higher than the maximum allowed


Task Management - OSTaskCreateExt()

Format: OSTaskCreateExt(*task, *pdata, *ptos, prio, id, *pbos, stk_size, *pext, opt)

Additional Argumentsid : The task's ID (0..65535)

pbos : A pointer to the task's bottom of stack

stk_size : The size of the stack in number of elements

pext : A pointer of TCB extension

opt : Contains additional information (or options) about the behavior of the task

Returns : Same as OSTaskCreate()


Task Management - Task Stacks(1/2)

Task 함수의 외부에서 정의되어야 할 자료정적으로 정의 할 경우

static OS_STK MyTaskStack[stack_size];

OS_STK MyTaskStack[stack_size];

동적으로 정의 할 경우malloc()

OS_STK *OS_STK *pstkpstk;;pstkpstk = (OS_STK *)= (OS_STK *)mallocmalloc(stack_size);(stack_size);if if pstkpstk !=(OS_STK*)0){!=(OS_STK*)0){ /*Make sure /*Make sure mallocmalloc() has enough space*/() has enough space*/

Create the task;Create the task;}}


Task Management - Task Stacks(2/2)

Stack은 연속적인 메모리를 가짐

Fragmentation

Stack growsFrom low to high memory.

OS_STK_GROWTH is set to 0 in OS_CPU.H

From high to low memory.OS_STK_GROWTH is set to 1 in OS_CPU.H

33KbKb B(1Kb)B(1Kb) B(1Kb)B(1Kb)

C(1Kb)C(1Kb)

A(1Kb)A(1Kb) 11KbKb

11KbKb

OS_STK OS_STK TaskStackTaskStack[TASK_STACK_SIZE];[TASK_STACK_SIZE];OSTaskCreateOSTaskCreate(task, (task, pdatapdata, &, &TaskStackTaskStack[0], [0], prioprio););

OS_STK OS_STK TaskStackTaskStack[TASK_STACK_SIZE];[TASK_STACK_SIZE];OSTaskCreateOSTaskCreate(task, (task, pdatapdata, &, &TaskStackTaskStack[TASK_STACK_SIZE[TASK_STACK_SIZE--1], 1], prioprio););


Task Management - OSTaskStkChk()

Current Location of Stack Pointer

Deepest Stack Growth

OSTCBStkBottom

Initial TOS

OSTCBStkSize

Stack GrowthUsed Stack Space

HIGH MEMORY

LOW MEMORY

Free Stack Space

000. . .

0

특정 Task의 Stack 메모리 중 사용하지 않은 양을 측정할 수 있음


Task Management – Functions(1/2)

OSTaskDel() - Deleting a TaskTask를 삭제할 수 있는 함수

Task 스스로도 호출 가능

해당 Task는 DORMANT 상태로 진입

OSTaskDelReq()- Requesting to Delete a Task해당 Task가 스스로 삭제되도록 요청

현재 수행중인 Task가 삭제되기를 요청하면 삭제될 수 있음

OSTaskChangePrio() – Changing a Task’s Priority

Task 생성시에 우선 순위가 결정되어 있음

그러나 이 함수를 사용하여 변경가능

우선순위 역전 현상을 해결가능


Task Management - Functions (2/2)

OSTaskSuspend() – Suspending a TaskSuspend된 task는 OSTaskResume()에 의해 다시 동작 가능한 상태로 변경됨

스스로 혹은 다른 Task를 Suspend 할 수 있음

주의 사항 : event (e.g., a message, a semaphore)를 기다리고 있는 Task의 경우에는 신호 전달에 문제 발생 주의

OSTaskResume() – Resuming a TaskOSTaskResume()을 호출하면 다시 동작 가능한 상태로 될 수있음

OSTaskQuery() – Getting Info. about a TaskTasks 그 자체나 다른 Task에 대한 기타 정보를 획득(OS_CFG.H에 정의한 Task 정보를 바탕)

원하는 Task의 OS_TCB의 정보를 갖고 있음

Task가 수행되는 state와, 그 때 사용될 functions


Time Management

Clock time을 이용

시간과 관련된 함수를 제공

OSTimeDly()

OSTimeDlyHMSM()

OSTimeDlyResume()

OSTimeGet()

OSTimeSet()


Time Management - Delaying a Task

OSTimeDly()사용자가 지정하는 Clock time의 수만큼 Task 자신을 wait상태로 옮겨 Task의 실행을 지연시킴

현재 실행중인 Task의 실행을 멈추고, ready 상태에 있는 가장 높은 우선 순위의 Task를 실행

지정한 시간이 다 되거나 OSTimeDlyResume()에의해 ready 상태로 가면 다른 대기 중인 Task들과경합을 벌여 가장 높은 우선 순위일 때에만 실행됨

OSTimeDlyHMSM()OSTimeDly()와 같은 기능

H(시간), M(분), S(초)와 m(밀리초 = 10-3초)로 직접 사용자가 지정함


Time Management – Resume Delayed Task

OSTimeDlyResume()지연시킨 Task를 다시 풀고 ready 상태로 만듦

다른 Task가 지연된 Task를 wait 상태에서 ready 상태로 전환시킬 때 사용

이 경우 재실행된 Task는 대기중 시간이 끝난 것으로 처리


Time Management - System Time

Clock tick이 발생시마다 32 bit Counter 변수의 값을 증가

OSStart()의 호출이후 계속 증가(Tick rate이100Hz라면 497일이 되면 다시 초기화됨)

OSTimeGet()Counter의 값을 읽어오는 데에 사용

OSTimeSet()사용자가 지정한 값으로 Counter의 값을 설정

이 OSTime에 접근하는 동안에는 Interrupt를불능 상태로 만듦


Intertask Communication & Sync.(1/2)

공유 데이터를 보호하고 TASK간의 통신을 위한 여러 가지 방법들

여러 TASK들이 사용하고 있는 데이터들이 임의로 변경되지 않도록 함

한 TASK가 만들어낸 정보를 다른 TASK가 이용하기 위하여 전달할 수 있는 채널

synchronization과 coordination을 구현하기위한 방법 semaphore

IPC를 구현 하는 방법 mailbox, message queue

기타 : Mutex., Event Flags


Intertask Communication & Sync.(2/2)

Semaphore

Mailbox

Message Queue

Event Flags

Mutex


IPC & Sync. - Semaphore

semaphore를 사용하기 전에 이 자원에 대한생성이 필요

Semaphore 사용법(initial value 설정)Signal event

shared resource

n identical resources

5가지 semaphore serviceOSSemCreate()

OSSemPend(), OSSemPost()

OSSemAccept(), OSSemQuery()


IPC & Sync. – Relationships(tasks, ISRs)

Task

ISR

OR

N

N

Task

OSSempend()

OSSemAccept()

OSSemQuery()

OSSemCreate()

OSSemPost()

OsSemPost()

OSSemAccept()


IPC & Sync. - Creating a semaphore

OSSemCreate()

Steps :1. ECB의 free list로 부터 하나를 할당 받음

2. ECB 설정

3. ECB로 Pointer 값을 되돌려 줌

pointer는 semaphore를 다루는 함수에 사용됨 [OSSemPend(), OSSemPost(), OSSemAccept(), and OSSemQuery()]

더 이상의 ECB가 없다면, OSSemCreate()는NULL pointer를 돌려 줌


IPC & Sync. - Waiting on a semaphore

OSSemPend()

steps :

1. Type 과 semaphore 확인

2. If semaphore =< 0, interrupt nest 확인

3. Else semaphore를 기다리게 하기 위해 task를 Block 시킴

Error return :OS_ERR_EVENT_TYPE : type mismatch

OS_ERR_PEND_ISR : ISR cannot made to wait

OS_TIMEOUT : time up before get semaphore.


IPC & Sync. - Signaling a semaphore

OSSemPost()

steps : 1. Type 확인

2. 어떤 task가 waiting 하고 있는지 최 상위 우선순위의 것을 선택함

3. Waiting하는 Task가 없다면 semaphore를 증가시키고 return

ISR에 의해 이 함수가 호출되면 context switch이 되지 않고 마지막 OSIntExit()에서context switching 함


IPC & Sync.- Getting a semaphore w/o waiting

OSSemAccept()

Function steps : 1. Type과 semaphore를 확인

2. If count > 0 , count 감소

3. if not, return count

OSSemAccept()를 호출하는 함수는 returned value를 확인할 필요가 있음

Return value = 0 semaphore 가 가능하지않음


IPC & Sync. - status of a semaphore

OSSemQuery()

steps : 1. type 확인

2. ECB의 데이터를 복사

semaphore가 가지고 있는 ECB의 포인터를제공

OS_EVENT structure로부터 OS_SEM_DATA structure로 현재의 semaphore count값을 복사함


IPC & Sync. - Message MailBox(1/2)

Task가 독립적으로 움직이지만 이들 사이의데이터 교환을 위한 통로가 필요

MailBox : Task간에 직접 data(message)를주고 받는 데에 사용

하나의 message (mailbox is full)만 전달 가능

구성message를 포함한 데이터 구조체를 가리키는Pointer

대기 중인 TASK의 리스트

단순히 post와 pend 여부만을 검사하여binary semaphore처럼도 사용 가능


IPC & Sync. - Message MailBox(2/2)

Mailbox는 OS_MBOX_EN = 1로 하여야 사용가능

사용하기 전에 이 자원에 대한 생성이 필요

5가지의 Mailbox serviceOSMboxCreate()

OSMboxPost()

OSMboxPend()

OSMboxAccept()

OSMboxQuery()

기능과 사용법은 Semaphore와 동일


IPC & Sync. - Relationships

OSEventType*OSEventPtrOSEventTblOSEventGrp

ⅡMailbox

ECB

Message

Task

ISR

Task

OSMboxCreate()

OSMboxPost()

OSMboxPost()OSMboxAccept()

OSMboxPend()OSMboxAccept()OSMboxQuery()


IPC & Sync. - mailbox as binary semaphore(1/2)

non-empty mailbox를 생성

Wait : OSMboxPend();

Signal : OSMboxPost();

OS_EVENT *MboxSem;

void Task1(void *pdata){

INT8U err;for(;;){

OSMboxPend(MboxSem, 0, &err); /* Obtain resource */……OSMboxPost(Mbox , (void *)1); /* Release resource */

}}


IPC & Sync. - mailbox as binary semaphore(2/2)

Resource

Task1

Task1

Task2

……

message:

ECBPendPost

Pend

Post

PostPend


IPC & Sync. - mailbox as time delay(1/2)

empty mailbox 생성

Delay task : OSMboxPend();

Cancel delay : OSMboxPost();void Task1(void *pdata)

{

INT8U err;

for(;;){

/* Delay task */

OSMboxPend(MboxTimeDly, TIMEOUT, &err);

………

}

}

void Task2(void *pdata)

{

INT8U err;

for(;;){

/* cancel delay */

OSMboxPost(MboxTimeDly, (void *)1);

………

}

}


IPC & Sync. - mailbox as time delay(2/2)

message:NULL

ECB

Task1

Task2Post

Pend


IPC & Sync. - Message Queue

Message mailbox의 array와 같음

OS_Q_EN = 1로 하여야 사용 가능

사용되기 전에 생성되어야 함

FIFO와 LIFO queue 모두 사용 가능

Resource의 개수만큼 message 포함 가능

Counting semaphore로 사용 가능


Task

ISR

Message Queue Task

Message*Message*Message*Message*Message*Message*Message*

OSQPost()OSQPostFront()OSQFlush()

OSQPost()OSQPostFront()OSQFlush()

* OSQPend()OSQAccept()OSQQuery()

ISR

OSQPend()OSQAccept()OSQQuery()

Size = NOSQCreate()

IPC & Sync. - Message Queue Architecture


OSEventGrp

OSEventTbl[]

OSEventCntOSEventPtr

OS_Event

OSQPtrOSQStartOSQSizeOSQOutOSQIn

OSQEndOSQEntries

OS_Q

void* MsgTbl[]

OSQEntries

OSQSize

IPC & Sync. - Message Date Structure(1/4)


OSEventGrp

OSEventTbl[]


OSEventGrp

OSEventTbl[]


OSEventGrp

OSEventTbl[]



OSQEndOSQEntries


OSQEndOSQEntries


OSQEndOSQEntries

OSEventFreeList

OSQFreeList

NULLNULLOS Event Link List

OS Message Queue Link List



OSEventGrp

OSEventTbl[]


OSEventGrp

OSEventTbl[]


OSEventGrp

OSEventTbl[]



OSQEndOSQEntries


OSQEndOSQEntries


OSQEndOSQEntries

OSEventFreeListOSQFreeList

NULLNULL



.OSQStart.OSQEnd

.OSQOut

.OSQIn.OSQEntries

Pointer to message



Start

To get OSEventFreeList

To get OSQFreeList

Initialize the Message Queue Header

Linking OSEventFreeList to OSQFreeList which we got

Reset the OSEventFreeListand OSQFreeList

End

Return the pointer of Eventobject which we got

Has error, return NULL pointer

Yes

Yes

No

No

IPC & Sync. - Creating a message queue


Start

Correct Event Type

Need to fire event

If the queue table isn’t full

Insert a message in the message table

End

Return the successful signal

Return the unsuccessful signal

Post event(That means insert a event)

Do the system schedule

Yes

Yes

No

Yes

No

No

IPC & Sync. - Depositing a message queue


Start

End

Correct Event Type

If the queue table isn’t empty

Return the Null pointer

Return the message pointer

Get a message fromthe message table

Yes

Yes

No

No

IPC & Sync. - Getting a message w/o waiting


Start

End

Correct Event Type

If the queue table isn’t empty

Get a message fromthe message table

Return the message pointer

Return the Null pointer

Is this a task?

Set a Event trap to wait the queue insert message event

(with timeout)

Is it still waiting for that event?

Getting the message from that event message

Have we got the message event ?

Timeout !!Return the Null pointer

Yes

Yes

Yes

Yes

Yes

No

No

No

No

No

IPC & Sync. - Waiting for a message queue


Memory Management

일반 C언어 : malloc()과 free()로 자유롭게 메모리를할당

임베디드 실시간 시스템에서는 fragmentation 위험

보통 TASK 스택을 할당시 연속적인 블록을 사용하는알고리즘 채택

malloc()과 free()의 대안연속된 메모리 구역에 고정 크기의

메모리를 얻기 위한 방법

모든 메모리 블록은 같은 크기

메모리의 할당,회수는 일정 시간에 진행

하나 이상의 메모리 파티션이 존재가능

어플리케이션은 다른 크기의 메모리 블록을 얻을 수 있음

Start Address

Block

Memory partition


Memory Management - MCBs

typedef struct { /*MEMORY CONTROL BLOCK */

void *OSMemAddr; /*Pointer to beginning of memory partitio */

void * OSMemFreeList; /*Pointer to list of free memory blocks */

INT32U OSMemBlkSize; /*Size (in bytes) of each block of memory */

INT32U OSMemNBlks; /* Total number of blocks in this partition */

INT32U OSMemNFree; /* Number of memory blocks remaining in

this partition */

} OS_MEM;

MCB : Memory Control Blocks

데이터 구조체를 메모리 분할의 형식으로 사용


Memory Management - Function List(1/2)

OSMemCreate( )어플리케이션은 실행 전에 각 파티션을 생성해야함

메모리 파티션을 생성, 초기화 가능

OSMemGet( )어플리케이션은 생성된 메모리 파티션의 하나로부터 메모리 블록 획득

어플리케이션에서는 자신에게 필요한 메모리 양만사용


Memory Management - Function List(2/2)

OSMemPut( )어플리케이션이 메모리 블록을 사용하고 난후적절한 파티션으로 메모리를 돌려줄 때 사용

메모리 블록을 원래 속해있던 파티션으로 되돌려 주지 않으므로 사용 주의

OSMemQuery()메모리 파티션에 대한 정보를 얻음

비거나 사용 중인 메모리 블록을 파악 가능

정보 : OS_MEM_DATA로 불리는 데이터 구조체에 위치


ARM ArchitectureARM Architecture



ARM ArchitectureARM Architecture - Contents

ARM Architecture Overview

• ARM Programmer Model

• ARM Instruction Set

• Thumb Instruction Set

• ARM Assembly Programming

• ARM920T System Control Coprocessor

• ARM920T MMU

• ARM920T Cache, Write Buffer


ARM ArchitectureARM Architecture – About Company

1985. Acorn Computer Group develops the world’s first commercial RISC processor

1990. 12 ARM pins out of Acorn and Apple

1991. the first embeddable RISC core ARM6

1993. TI, Cirrus, Samsung license ARM, ARM7 core

1995. Thumb architecture, StrongARM

1996. ARM9TDMI family announced

1998. ARM10 family announced

2002. ARM11

The industry's leading provider of 32-bit embedded RISC microprocessors with almost 75% of the market


ARM ArchitectureARM Architecture - About ARM MPU

ARM (Advanced RISC Machine) ArchitectureIt’s RISC (Reduced Instruction Set Computer)

Large uniform register file

Load/store architecture

Simple addressing mode

Uniform and fixed-length instruction field

In addition,Shift + ALU data processing

Auto increment/decrement addressing

Load and store multiple

Conditional execution

CharacteristicSmall die size Low power

Thumb instruction High code density

High Performance, Lower Cost, Less Power


ARM ArchitectureARM Architecture - Embedded Products


ARM ArchitectureARM Architecture - Progression

T: Thumb extension

D: Debug extension

M: Hardware multiplier

I: EmbeddedICE extension

E: DSP Enhanced

J: Java extension

V6: Media extension

XScale

ARM7

StrongARM

V4

ARM7TDMI

V4T

ARM920TSecureCore

ARM9E

V5TE

ARM1020EARM926EJ

V5TEJ

V6


ARM ArchitectureARM Architecture - ARM9TDMI Core B.D.

Register Bank(31x32 + 6 PSR)

32 bit ALU

Shifter

MUL

DAReg

A B

us

B B

us

C B

us

DDReg

IAReg IINC

DINC

IA[31:0]

DA[31:0] DO[31:0] DI[31:0]

InstructionDecode

&ControlLogic

ID[31:0]

ScanControl

32bit (16 bit) RISC

ARM Architecture V4T

5 Stage Execution Pipelining

Harvard Architecture

ARM9TDM

EmbeddedICE

TAPController

ControlAddress

Data


ARM ArchitectureARM Architecture - ARM920T B.D.

ARM9TDMI

16K I$, 16K D$

MMU

Write Buffer

AMBA AHB Interface

CP Interface


ARM ArchitectureARM Architecture - Core Comparison

400xooNAo32K/32KXscale

206xxxNAo16K/16KStrongARM

266-325oooDualMMU+MPU

VariousARM1020EJ

325xooDualo32K/32KARM1020E

220-250oooDualoVariousARM926EJ

180xxooMPU4K/4KARM940

250xxooo16K/16KARM920

100xxooo8K UnifiedARM720T

133xxooxxARM7TDMI

ClockJazelleDSPThumbAHB Bus

MMUCache

(I/D)


ARM ArchitectureARM Architecture - Coprocessor(CP15)

Control standard memory and system facilitiesMMU and PU

Cache and Write Buffer

FCSE

Endianness and High vector address

Use only MCR, MRC coprocessor instructions in a privileged mode

1 1 1 1cond 1 1 1 L CRn Rd31 28 27 26 25 24 23 21 20 19 16 15 12 11 8

0 0 0 0 Op_2 00001037 6 5 4

Operation 1Load/Store CR0

Source/DestinationOperation 2

CP15Source/Destination


ARM ArchitectureARM Architecture - ARM920T CP15

Test configurationTest configuration15UnpredictableUnpredictable14

FCSE PIDFCSE PID13UnpredictableUnpredictable12UnpredictableUnpredictable11

2 registers for Instr./DataTLB lockdownTLB lockdown102 registers for Instr./DataCache lockdownCache lockdown9

TLB operationsUnpredictable8Cache operationsUnpredictable7

UnpredictableUnpredictable4

Fault addressFault address62 registers for Instr./DataFault statusFault status5

Domain access controlDomain access control3

Op-2 = 1Op_2 = 0

Action

Translation table baseControl

UnpredictableUnpredictable

WriteRead

Translation table base2Control1

Cache type0ID Code0

Reg


ARM Programmer Model - Overview

• Data Types

• Processor Modes

• Registers

• Exceptions

• Memory Systems


ARM Programmer Model - Data Types

Supported Data TypesByte : 8 bits

Halfword : 16 bits (aligned to 2-byte boundaries)

Word : 32 bits (aligned to 4-byte boundaries)

NotesUnsigned: 0 ~ 2N – 1

Signed: -2N-1 ~ +2N-1 – 1

All data operations are performed on word quantities

Load/Store transfer B, HW, W with zero-extending and sign-extending

ARM instruction are exactly 1 word

Thumb instruction are exactly 1 halfword


ARM Programmer Model - Modes

User and System mode share one bank of registers

Exception mode: their own registersFIQ mode has private R8 ~ R14

the other modes have private R13 ~ R14

HW EmulationundWhen an undefined instructionUndef

Vir. Mem, MProabtWhen data or instruction prefetch abortAbort

SWIsvcException mode for operating systemSupervisor

irqWhen a normal interruptIRQ

High-speed ch.fiqWhen a fast interruptFIQ

OS tasksysPrivileged mode for operating systemSystem

restrictionusrNormal program execution modeUser

CommentsIDDescriptionMode


ARM Programmer Model – Registers

R0R1R2R3R4R5R6R7R8R9R10R11R12R13R14

PC(R15)

User & System FIQ IRQ Supervisor Abort Undef R0R1R2R3R4R5R6R7

R8_fiqR9_fiqR10_fiqR11_fiqR12_fiq

CPSR

PC(R15)

CPSR

R0R1R2R3R4R5R6R7R8R9R10R11R12

PC(R15)

CPSR


PC(R15)

CPSR


PC(R15)

CPSR


R13_undR14_und

PC(R15)

CPSRSPSR_fiq

R13_abtR14_abt

SPSR_abt

R13_svcR14_svc

SPSR_svc

R13_irqR14_irq

SPSR_irq

R13_fiqR14_fiq

SPSR_fiq

Program Counter

Program Status Register


ARM Programmer Model - PSRs

ALU operation oVerflowedVALU operation caused Carry

CZero result from ALUZNegative result from ALUNCondition Code Flags

1: Thumb, 0: ARMT1: disables FIQF1: disables IRQI

Control bits

Undefined0b11011Abort0b10111

Supervisor0b10011IRQ0b10010FIQ0b10001

System0b11111User0b10000ModeM[4:0]

Mode bits

CPSR (Current PSR): Hold the current status information

SPSR (Saved PSR): Reserve the CPSR during exceptions

N Z C V I F T MReserved31 30 29 28 27 8 7 6 5 4 0

Control fieldExtension fieldStatus fieldFlag field


ARM Programmer Model - Exceptions

0xFFFF00140x00000014Reserved

0xFFFF001C0xFFFF0018

0xFFFF00100xFFFF000C0xFFFF0008

0xFFFF00040xFFFF0000High Vector

0x0000001CFIQ3FIQ0x00000018IRQ4IRQ

0x00000010Abort2Data Abort0x0000000C0x00000008

0x000000040x00000000

Vector

AbortSupervisor

UndefinedSupervisor

ModePriority

5Prefetch Abort6SWI

6Undefined Instruction

1ResetException Type


ARM Programmer Model – H/W Vectors

Branch to Handler0x00

0x04

0x08

0x0c

0x10

0x14

0x18

0x1c

Reset

Undefined Instruction

Software Interrupt

Prefetch Memory Abort

Data Memory Abort

Reserved

Normal Interrupt

Fast Interrupt

Branch to Handler

Branch to Handler

Branch to Handler

Branch to Handler

Branch to Handler

FIQ Handler

Interrupt Handler

Branch to Handler


ARM Programmer Model - LR & Return

Reserved

SUBS PC, R14, #4Next instruction + 4FIQSUBS PC, R14, #4Next instruction + 4IRQ

SUBS PC, R14, #8Aborted instruction + 8Data AbortSUBS PC, R14, #4

MOVS PC, R14MOVS PC, R14

ReturnR14 from ARM

Aborted instruction + 4Prefetch AbortSWI instruction + 4SWI

Undefined instruction + 4Undefined InstructionUnpredictableReset

Exception Type


ARM Programmer Model - Endian

Support Dual-Endian

Big Endian Processor : (like IBM, Motorola, SPARC)

High-order-byte-first, human-friendly type

Little Endian Processor: (like DEX VAX, Intel X86)

Low-order-byte-first, computer-friendly type

B0B1B2B3MSB LSB

B3B2B1B0N

N+1N+2N+3

Little Endian

Store 4Bytes Word to Memory at N

N+3N+2N+1N

Big Endian

B3B2B1B0


ARM Programmer Model - Alignment

Aligned AccessGood for performance

Byte: 4N, 4N+1, 4N+2, 4N+3

Half Word: 4N, 4N+2

Word: 4N

Unaligned AccessGood for memory usage

Half Word: 4N+1, 4N+3

Word: 4N+1, 4N+2, 4N+3

0

4N

Aligned Access

4N+44N+84N+C

1 2 3 0

4N4N+44N+84N+C

1 2 3

Unligned Access


ARM Programmer Model - Dual-Endian

B0B1B2B3MSB LSB

Reg

D0D1D2D3Data Bus

Latch

Shift Logicin Byte

Endianness

NN+1N+2N+3Memory

D1

D0

D2

D3

B1

B0

B2

B3

D1

D0

D2

D3

B1

B0

B2

B3

Load Byte Load HW

D1

D0

D2

D3

B1

B0

B2

B3

Load W

D1

D0

D2

D3

B1

B0

B2

B3

D1

D0

D2

D3

B1

B0

B2

B3

Load Byte Load HW

D1

D0

D2

D3

B1

B0

B2

B3

Load W

shift logic for big-endian operand

shift logic for little-endian operand


ARM Instruction - Set

• ARM Instruction Characteristics

• Data Processing Instructions

• Load and Store Instructions

• Branch Instructions

• SWP and SWI

• Coprocessor Instructions


ARM Instruction - Characteristics

RISC InstructionFixed length – 32-bit

Load/Store Architecture

Simple format and Simple addressing mode

5-stage pipelining

Conditional Execution

Shifted operand

InstructionFetch

Fetch

InstructionDecode

RegDecode

RegRead

Shift+

ALU

MemoryAccess

RegWrite

Decode Execute Memory Write


ARM Instruction - v4T Instructions

Data Processing/PSR Transfercond Shifter_operand0 0 I SOpcode Rn Rd

cond Rm0 0 0 S Rd Rn0 0 0 A Rs 1 0 0 1 Multiply

cond Rm0 0 0 S RdHi RdLo0 1 U A Rn 1 0 0 1 Multiply Long

cond Rm0 0 0 0 Rn Rd1 0 B 0 1 0 0 1 Data Swap0 0 0 0cond Rm0 0 0 01 0 0 1 0 0 0 1 Branch and

Exchange11 1 1 11 1 1 11 1 1cond Ad_mode0 0 0 L Rn RdP U I W 1 S H 1 HW Data

TransferAd_modecond 0 1 1 L Rn RdP U B W Single Data

TransferOffsetcond 1 0 1 Undefined1cond 1 0 0 L RnP U S W Block Data

TransferRegister Listcond 1 0 1 BranchL Signed_immed_24cond Offset1 1 0 L Rn CRdP U N W Co-processor

Data TransferCP#cond Op_21 1 1 CRn CRd0 Op_1 Co-processor

Data OperationCP# CRm0cond Op_21 1 1 CRn Rd0 Op_1 Co-processor

Register TransferCP# CRm1Lcond 1 1 1 1 SWI number Software

Interrupt

31 30 29 28 27 7 6 5 4 026 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 810 9 3 2 1


ARM Instruction - Condition Field

Cond Reserved31 28 27 0

Unpredictable(NV)1111AlwaysAL1110

Z==1 or N!=VSigned <=LE1101Z==0,N==VSigned >GT1100

N!=VSigned <LT1011N==VSigned >=GE1010

C=0 | Z=1Unsigned lower or sameLS1001C=1 & Z=0Unsigned higherHI1000

N = 0Plus/Positive or ZeroPL0101

O = 0No overflowVC0111O = 1OverflowVS0110

N = 1Minus/NegativeMI0100C = 0C = 1Z = 0Z = 1

Condition flag state

Carry clear / unsigned <Carry set / unsigned >=

Not EqualEqual

MeaningMnemonic

CC/LO0011CS/HS0010

NE0001EQ0000

Cond


ARM Instruction - Data Processing

Rd = NOT(shifter_operand)Move NotMVN1111Rd = Rn AND NOT(shifter_operand)Bit clearBIC1110Rd = shifter_operandMoveMOV1101Rd = Rn OR shifter_operandLogical ORORR1100Update flags after Rn + shifer_opernadCommomCMN1011Update flags after Rn - shifer_opernadCompareCMP1010Update flags after Rn EOR shifer_opernadTest EquivalenceTEQ1001Update flags after Rn AND shifer_opernadTestTST1000

Rd = Rn + shifter_operand + CarryAdd with carryADC0101

Rd = shifter_operand - Rn – NOT(Carry)Reverse Subract with carryRSC0111Rd = Rn – shifter_operand – NOT(Carry)Subract with carrySBC0110

Rd = Rn + shifter_operandAddADD0100Rd = shifter_operand - Rn Rd = Rn - shifter_operandRd = Rn EOR shifter_operandRd = Rn AND shifter_operand

Action

Reverse subtractSubtract

Logical Exclusive ORLogical AND

MeaningMnemonic

RSB0011SUB0010EOR0001AND0000

Opcode

cond Shifter_operand0 0 I SOpcode Rn Rd31 30 29 28 27 7 6 5 4 026 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 810 9 3 2 1


ARM Instruction - Load/Store

cond Offset_mode0 1 I L Rn Rd31 28 27 026 25 24 23 22 21 20 19 16 15 12 11

Source or DestinationBase Register

Load/Store

011

12-bit immediate

7 011

Rm0sh#shift6 5 4 3

Shift typeImmediate shift length

Offset register

1

0

P U B W

Write-back(Auto-index)Unsigned byte/Word

Up/DownPre-/Post-index


ARM Instruction - Load/Store Multiple

NN+1N+2

Full Ascending (FA) Stack

N+3

Empty Ascending (EA) Stack

Stack ImplementationAscending Stack

Full Descending (FD) Stack Empty Descending (ED) Stack

Descending Stack

SPSP

NN+1N+2N+3

NN+1N+2N+3

NN+1N+2N+3

SPSP


ARM Instruction - Branch

cond 1 0 1 Signed_immed_2431 28 27 026 25 24

L

1: LR PC+4, PC target_addr

23

Branch / Branch with Link Instruction (B, BL)

cond 0 0 0 Rm31 28 27 026 25 24

1230 0 1 0

22 21 20SBO SBO SBO 0 0 0

7 6 5 41

381112151619

Branch and eXchange Instruction (BX)


ARM Instruction - Status Register Access

cond 0 0 0 SBZ31 28 27 026 25 24

1

Destination

23MRS (Move PSR to Registers)

MSR (Move Register to PSR)

023 22

R 0 021 20

SBO1619

Rd1215

SPSR/CPSR

cond Operand0 1 I 0 field_mask SB031 28 27 026 25 24 23 22 21 20 19 16 15 12 11

f/s/x/c

0118-bit immediate

7

011RmSBZ

4 3Operand register

1

0

1 0 R 1

#rot8

Immediate align(ROR 2x#ror)


ARM Instruction - Exception-generating

cond31 28 27 024

Ignored by ARM processor

23Software Interrupt (SWI)

23SBO Immed_24

R14_svcR14_svc Address of SWI instruction + 4Address of SWI instruction + 4

SPSR_svcSPSR_svc CPSRCPSR

CPSR[4:0]CPSR[4:0] Supervisor modeSupervisor mode

CPSR[7:5]CPSR[7:5] I = 1, F = unchanged, T = 0I = 1, F = unchanged, T = 0

PCPC 0x000000080x00000008

To returnTo return MOVS PC, R14MOVS PC, R14


ARM Instruction - Coprocessor

cond Op_21 1 1 CRn CRd0 Op_1

Co-processor Data Operation

CP# CRm031 28 27 026 25 24

Operation 1

23Coprocessor Data Operation (CDP)

23 20 1619 1215

First operand CR

11 38 7 6 5 4

Second operand CRDestination CR

Coprocessor NumberOperation 2

CP#cond Offset_81 1 0 L Rn CRd31 28 27 026 25 24 23 22 21 20 19 16 15 12 11

Source or DestinationBase Register

Load/Store

78P U N W

Write-back(Auto-index)Data size (Coprocessor dependent)

Up/DownPre-/Post-index

Coprocessor Load/Store Operation


ARM Instruction - Thumb

16-bit Re-encoded Subset of the ARM Instruction Set

Use Advantages of 32-bit Architecture with Restriction

1 1 1 0 0 0 0 0 8-bit immediate0 0 1 10 1 0 0 0 Rd 0 Rd

0 0 1 8-bit immediate1 0 Rd

Always ConditionCode

Major op-code:Move/compare/add/subWith immediate value

Minor op-code:ADD

Destination andSource Register

Immediate value

ARM Code

Thumb Code

Example: ADD Rd, #immediate


ARM Instruction - Thumb State Registers

R0R1R2R3R4R5R6R7SPLR

PC

User & System FIQ IRQ Supervisor Abort Undef

R0R1R2R3R4R5R6R7

CPSR

PC

CPSR

R0R1R2R3R4R5R6R7

PC

CPSR

R0R1R2R3R4R5R6R7

PC

CPSR

R0R1R2R3R4R5R6R7

PC

CPSR

R0R1R2R3R4R5R6R7

SP_undLR_und

PC

CPSRSPSR_fiq

SP_abtLR_abt

SPSR_abt

SP_svcLR_svc

SPSR_svc

SP_irqLR_irq

SPSR_irq

SP_fiqLR_fiq

SPSR_fiq

Program Counter

Program Status Register


ARM Instruction - Mapping Registers

R0~R7

R8~R12

Stack Pointer(R13)

Link Register(R14)

Program Counter(R15)

CPSR

SPSR

ARM State

R0~R7

Access viaSpecial instruction

Stack Pointer(SP)

Link Register(LP)

Program Counter(PC)

CPSR

SPSR

Thumb State


MMU - Memory Hierarchy

Fast and Expensive

Registers

Cache

Main Memory

Secondary Storage (Disk)

Off-line Storage

Slow and Inexpensive

Performance Cost/bits

Locality PrincipleProgram access a relatively small portion of the address space at any instant of time.

Temporal LocalityPrograms tends to use recent information

Spatial LocalityMemory location referenced recently is more likely to be referenced than farther memory location


MMU - Memory Terminology

Block: minimum unit of data

Hit, MissHit Ratio: the fraction of memory access found in the upper level

Miss Ratio = 1 - (Hit Ratio)

Hit Time << Miss Penalty

Lower LevelMemoryUpper Level

MemoryTo Processor

From ProcessorBlk X

Blk Y


MMU - Memory Management

FunctionsDynamic memory allocation

Virtual memory implementation and Virtual address space

Virtual-to-Physical address translation

Memory protection and Task security

Physical Memory

Virtual Memory

Disk

MP

U

Physical AddressVirtual Address

MM

U

Virt

ual

Add

ress

Phys

ical

Add

ress


MMU - ARM920T MMU

1MB(section), 64KB(large pages), 4KB(small pages), 1KB(tiny pages)

Access permissions for sections

Subpage access permissions for large and small pages

16 domains implemented in hardware

64 entry I TLB and 64 entry D TLB

Hardware page table walks

RR replacement algorithm

Invalidate whole TLB or TLB entry

Independent lockdown of ITLB and DTLB


MMU - Paging Organization

Virtual and physical address space partitioned into blocks of equal size

Page transferring is expensive due to Disk Access

Virtual/Physical Address Space Example

Virtual Page Number

Virtual Address

Page Offset0111231

Physical Page Number

Physical Address

Page Offset0111223

Translation


MMU - Microprocessor Cache

Cache Improve Overall System Performance

Reducing read and write cycle time by using fast memory

Improving memory bus utilization

MPUMEMORY

Cache

CacheController

Cacheaddress miss

Mem

ory busaddress

Memory dataupdatedata

Data(hit)


MMU - ARM920T Memory System

IVA

ARM9TDMIAMBA

Interface

C13

DVA

IMMU

I$

IMVA

DMMU

D$

DMVA

PA TAGRAM

Writebuffer

ID

DD

IPA

DPAC13


MMU - Cached MMU Memory System

VAARM

CacheAnd

Write buffer

TLB

Accesscontrol

hardware

Cacheline fetchhardware

Translationtable workhardware

MainMemory

C,B Bits

APDomain

AbortPA


MMU - Cache and Write Buffer

Cache’s FeatureSeparate 16KB instruction and 16KB data caches

Virtually-addressed 64-way associative cache

8-word line with 1 valid bit and 2 dirty bit per line for halfline write-back

Write-through and write-back by C and B

Pseudo-random or round-robin replacement

Independently lockable

PA TAG RAM for TLB miss during write-back and interrupt latency

Efficient cleaning of caches

Write Buffer’s Feature16-word data buffer

4-address address buffer

Can be drained under software control


System Initialization



FunctionsFunctions

Setup Exception Handling

Clock & Power Initialization

Memory System Initialization

I/O Device Initialization

Run Environment Setup

Initialization Code

Initialization FlowInitialization Flow

Clock Configuration

Disable Watch Dog Timer

Disable Interrupt

Memory Bank Initialization

Setup Exception Handler

Exception Vector Initialization

Stack Initialization

Initialization RW/ZI Data Area

Jump to Main


Exception Vector Table

AREA Init, CODE, READONLY

ENTRY

b ResetHandler b HandlerUndef ;handler for Undefined modeb HandlerSWI ;handler for SWI interruptb HandlerPabort ;handler for PAbortb HandlerDabort ;handler for DAbortb . ;reservedb HandlerIRQ ;handler for IRQ interrupt b HandlerFIQ ;handler for FIQ interrupt

B HandlerUndef

B HandlerSWI

B ResetHandler

…0x0000000C

0x00000008

0x00000004

0x00000000 ResetHandler

HandlerUndefB HandlerPabort

HandlerSWI


Initialization for Reset(1/2)

ResetHandlerldr r0,=WTCON ;watch dog disable ldr r1,=0x0 str r1,[r0]

ldr r0,=INTMSKldr r1,=0xffffffff ;all interrupt disablestr r1,[r0]

;To reduce PLL lock time, adjust the LOCKTIME ldr r0,=LOCKTIMEldr r1,=0xffffffstr r1,[r0]

; Configure MPLLldr r0, =MPLLCONldr r1,=((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV)str r1,[r0]

0x53000000

Watch dog timer disable

Setting PLL Lock Time

0x00000000

All interrupts disable0xffffffff0x4a400008

0x00ffffff0x4c000000

t_lock_M = 4K/12M = 333 uS t_lock_U = 333 uS

Setting MPLL Fout0x0005c0420x4c000008

Mpll = (m*Fin)/(p*2^s), m = MDIV+8, p = PDIV+2, s = SDIV


Initialization for Reset(2/2)

;Watchdog timerWTCON EQU 0x53000000;Interrupt control registerINTMSK EQU 0x4a400008;Clock ControllerLOCKTIME EQU 0x4c000000MPLLCON EQU 0x4c000004; Fin = 12MHz, Fout = 50MHzM_MDIV EQU 0x5c M_PDIV EQU 0x4M_SDIV EQU 0x2

;Watchdog timerBWSCON EQU 0x48000000

SMRDATA DATA;BUSWIDTH=32DCD 0x22222220 ;BWSCON

……

DCD 0x20 ;MRSR7


Memory Bank Initialization

;Set memory control registersldr r0, =SMRDATAldr r1, =BWSCON ;BWSCON Addressadd r2, r0, #52 ;End address of SMRDATA

0 ldr r3, [r0], #4 str r3, [r1], #4 cmp r2, r0bne %B0

0x22222220

0x10

SMRDATA

0x20

Set memory control registers

0x222222200x48000000

BANKCON0BANKCON1

REFRESHBANKSIZE

MRSR6 0x100x20

BANK6/7 SIZE32M/32M

0x20 0x20MRSR7

Memory

latency: 2clks

SDRAMconfig.

Special Register


Stack Initializationbl InitStacks ;Initialize stacks…

InitStacksmrs r0, cpsrbic r0, r0, #MODEMASK; Undefined mode & Interrupt disableorr r1, r0, #UNDEFMODE|NOINT msr cpsr, r1 ; UndefModeldr sp, =UndefStack

orr r1, r0, #ABORTMODE|NOINT msr cpsr, r1 ; AbortModeldr sp, =AbortStack

;IRQMode;FIQMode

orr r1, r0, #SVCMODEmsr cpsr, r1 ;SVCModeldr sp, =SVCStack

mov pc, lr ; returnLTORG ; Literal Pool Origin

SVC mode Undef mode Abort mode IRQ mode FIQ mode SVC mode

R13_und= 0x33ff7400

R13_abt= 0x33ff7800

R13_irq= 0x33ff7c00

R13_fiq= 0x33ff8000

R13_svc= 0x33ff7000


Setup Handler

; Setup IRQ handlerldr r0, =HandleIRQ ldr r1, =IsrIRQ ; M[HandleIRQ] IsrIRQstr r1, [r0]; Setup FIQ handler; Setup Undefined Handler; Setup SWI handler; Setup DABORT handler; Setup PABORT handler

HandlerIRQ HANDLER HandleIRQ/*HandlerIRQ

sub sp, sp, #4 ;to store IsrIRQstmfd sp!, {r0} ;Save r0ldr r0, =HandleIRQldr r0,[r0] ; r0 IsrIRQstr r0, [sp,#4] ;store IsrIRQldmfd sp!, {r0,pc} ;jump to */

IsrIRQ sub sp, sp, #4 ;to store handlerstmfd sp!,{r8-r9} ;save r8-r9

ldr r9, =INTOFFSET ; which INT?ldr r9, [r9] ; r9 INT numberldr r8, =HandleEINT0 ; r8 HandleEINT0add r8, r8, r9, lsl #2 ; Handler addressldr r8,[r8] ; r8 Handlerstr r8,[sp,#8] ; store Handler addrldmfd sp!,{r8-r9,pc} ; jump to Handler

HandleResetHandleUndefHandleSWI

HandlePabortHandleDabort

HandleReserveIsrIRQHandleIRQ

HandleFIQHandleEINT0HandleEINT1

…Timer0ISRHandleTimer0

…

0x33FFFF000x33FFFF04

HandleRTC 0x33FFFFFC


RW/ZI Data Initialization

;Copy and paste RW data/zero initialized dataldr r0, =|Image$$RO$$Limit| ; RO limitldr r1, =|Image$$RW$$Base| ; RW limitldr r3, =|Image$$ZI$$Base| ; ZI base

cmp r0, r1 ; Check that they are differentbeq %F2 ; if RO_limit = RW_base goto 2

1 cmp r1, r3 ; Copy RW data upto ZI_limitldrcc r2, [r0], #4 ; if r1 < r3 strcc r2, [r1], #4 bcc %B1

2 ldr r1, =|Image$$ZI$$Limit| ; Top of zero init segmentmov r2, #0

3 cmp r3, r1 strcc r2, [r3], #4 ; Zero Initialize if r3<r1 bcc %B3

bl Main ;jump to Main

ZI

RW

RO

RO_BASE0x30000000

RW_BASE

ZI_BASE

RO_LIMIT

ZI_LIMIT

RW

RO

ZI

RW

RO

RO_BASE0x30000000

RW_BASE

ZI_BASE

RO_LIMIT

ZI_LIMIT

Zero-InitializedRegion

(1) RO_LIMIT = RW_BASE (2) RO_LIMIT != RW_BASE

ZI_LIMITZI_BASE

Zero-InitializedRegion

Load View


Porting uC/OS-II on ARM9



uC/OS-II Requirements

uC/OS-II Requirements해당 Processor의 C compiler가 존재하는가?

해당 Processor가 일정주기의 Tick을 생성할 수 있는가?

Interrupt가 C에서 허가/금지가 가능한가?

충분한 양의 데이터를 유지할 수 있는가?

해당 Processor가 Stack 관련 연산과 CPU Register를 Stack에 저장할 수 있는가?

ARM-9 satisfies all requirements.


uC/OS-II HW/SW Architecture.

uC/OS-II ArchitectureApplication Software

Processor-Independent Code

Application-Specific Code

Processor/Compiler Specific Code

uC/OS-II Config.Application

Specific Code

OS_CFG.HINCLUDES.H

uC/OS-II Config.Application

Specific Code

OS_CFG.HINCLUDES.H

Application SoftwareApplication Software

uC/OS-IIProcessor

Independent CodeOS_CORE.COS_MBOX.COS_MEM.C

OS_Q.COS_SEM.COS_TASK.COS_TIME.CuCOS_II.CuCOS_II.H

uC/OS-IIProcessor

Independent CodeOS_CORE.COS_MBOX.COS_MEM.C

OS_Q.COS_SEM.COS_TASK.COS_TIME.CuCOS_II.CuCOS_II.H

uC/OS-IIProcessor/Compiler Specific Code

OS_CPU.HOS_CPU_A.ASM

OS_CPU_C.C

uC/OS-IIProcessor/Compiler Specific Code

OS_CPU.HOS_CPU_A.ASM

OS_CPU_C.C

CPUCPU


RTOS Application Program Structure

주 실험 프로그램 : xx_main.c, ……

ARM Project 프로그램 : xx_main.apj (SDT compiler 기준)

전체 프로젝트 폴더

Startup, 기본 드라이버 코드 폴더

SDMK2410

드라이버를 기반으로 한 시스템 운영 API 코드 폴더

APIs

RTOS 코드와 Porting 코드 폴더

uCOS_II


Port Summary (Data Types, Macro)

Data Types

MacroOS_ENTER_CRITICAL()

OS_EXIT_CRITICAL()

OS_STK_GROWTH

Name Type

INT8U unsigned 1-byte

INT8S signed 1-byte


INT16S signed 2-byte


INT32S signed 4-byte

OS_STK Processor-specific

OS_CPU_SR Processor-specific


Port Summary (Function)

FunctionsOSStartHighRdy()

OSCtxSw()

OSIntCtxSw()

OSTickISR()

OSTaskStkInit()

User Hook FunctionOSInitHookBegin(), OSInitHookEnd()

OSTaskCreateHook(), OSTaskDelHook(), OSTaskSwHook(), OSTaskStatHook()

OSTCBInitHook(), OSTimeTickHook(), OSTaskIdleHook()


OS_CPU.H (Data Types)

Definition integer data types.

Processor마다 integer types의 크기가 다름.80186 (16bit CPU)

unsigned int = 16-bit unsigned data.

typedef unsigned int INT16U

ARM9 (32bit CPU)unsigned int = 32-bit unsigned data.

typedef unsigned int INT32U

OS_STK : 해당CPU의 Stack의 단위 크기 정의.ARM9

typedef unsigned int OS_STK


OS_CPU.H (Critical Section)

Critical Section Kernel은 특정 영역에서 Interrupt 발생을 금지할 수있어야 함.

OS_CRITICAL_ENTER

OS_CRITICAL_EXIT

mrs r0,CPSR; // PSR을 R0에읽음.stmfd sp!,{r0}; // PSR을스택에저장.orr r0,r0,#NOINT; // Disable IRQmsr CPSR_c,r0;

ldmfd sp!,{r0}; // 스택에저장했던 PSR을읽음.msr CPSR_c,r0; // Restore PSR


OS_CPU.H (Stack Growth)

OS_STK_GROWTH사용 Processor의 Stack의 방향 결정.

ARM9어느 방향으로든 가능하며, 컴파일러에 의존적.

SDT 및 ADS에서는 LDMFD/STMFD 명령을 사용.LDMFD(Post-Increment Load)

STMFD(Pre-Decrement Store)

따라서 High to low의 방향을 가짐.

#define OS_STK_GROWTH 1 // High to low


OS_CPU_C.C

Should write 10 simple C functions.OSTaskStkInit()

OSTaskCreateHook()

OSTaskDelHook()

OSTaskSwHook()

OSTaskIdleHook()

OSTaskStatHook()

OSTimeTickHook()

OSInitHookBegin(), OSInitHookEnd()

OSTCBInitHook

The only required function is OSTaskStkInit().

The other nine functions must be declared, but do not need to contain any code.


OS_CPU_C.C (OSTaskStkInit())

Task Context

R13(SP)는 따로 저장하기때문에 저장하지 않음.

Nested Interrupt를 위하여SPSR을 저장.

LDMFD/STMFD 명령에 적합하도록 생성.

R14R14 HighHigh

R12R12

R11R11

R10R10

R9R9

R8R8

R7R7

R6R6

R5R5

R4R4

R3R3

R2R2

R1R1

R0R0

CPSRCPSR

SPSRSPSR LowLow



OSTaskStkInit()목적 : Task의 스택을 Context Switching Out 된 상태인 것처럼 스택을 초기화.

Pseudo-code for OSTaskStkInit()

OS_STK OSTaskStkInit( void (*task)(void *pd), void *pdata, OS_STK *ptos, INT16U opt)

{Setup stack frame to contain desired initial values of all regs.Return new top-of-stack pointer to caller.

}



OSTaskStkInit() for ARM9

OS_STK *OS_STK *OSTaskStkInitOSTaskStkInit (void (*task)(void *pd), void *(void (*task)(void *pd), void *pdatapdata, OS_STK *, OS_STK *ptosptos, INT16U opt), INT16U opt){{

OS_STK *OS_STK *stkstk;;opt = opt;opt = opt; /* 'opt' is not used, prevent warning/* 'opt' is not used, prevent warning */*/stk stk = = ptosptos;; /* Load stack pointer/* Load stack pointer */*/*(*(stkstk) = (OS_STK)task;) = (OS_STK)task; /* Entry Point/* Entry Point */*/*(*(----stkstk) = (INT32U)0;) = (INT32U)0; /* /* lrlr */*/*(*(----stkstk) = (INT32U)0;) = (INT32U)0; /* r12/* r12 */*/*(*(----stkstk) = (INT32U)0;) = (INT32U)0; /* r11/* r11 */*/*(*(----stkstk) = (INT32U)0;) = (INT32U)0; /* r10/* r10 */*/*(*(----stkstk) = (INT32U)0;) = (INT32U)0; /* r9 *//* r9 */*(*(----stkstk) = (INT32U)0;) = (INT32U)0; /* r8 *//* r8 */*(*(----stkstk) = (INT32U)0;) = (INT32U)0; /* r7 *//* r7 */*(*(----stkstk) = (INT32U)0;) = (INT32U)0; /* r6 *//* r6 */*(*(----stkstk) = (INT32U)0;) = (INT32U)0; /* r5 *//* r5 */*(*(----stkstk) = (INT32U)0;) = (INT32U)0; /* r4 *//* r4 */*(*(----stkstk) = (INT32U)0;) = (INT32U)0; /* r3 *//* r3 */*(*(----stkstk) = (INT32U)0;) = (INT32U)0; /* r2 *//* r2 */*(*(----stkstk) = (INT32U)0;) = (INT32U)0; /* r1 *//* r1 */*(*(----stkstk) = (INT32U)pdata;) = (INT32U)pdata; /* r0 : argument *//* r0 : argument */*(*(----stkstk) = (INT32U)(SVCMODE|0x0);) = (INT32U)(SVCMODE|0x0); /* CPSR *//* CPSR */*(*(----stkstk) = (INT32U)(SVCMODE|0x0);) = (INT32U)(SVCMODE|0x0); /* SPSR *//* SPSR */

return (return (stkstk););}}


OS_CPU_C.C (OSxxxHook())

OSxxxHook() FunctionCalled by other internal function.

Hook functions and caller functions.

Function Name Called ByOSTaskCreateHook() OS_TCBInit().

OSTaskDelHook() OSTaskDel().OSTaskSwHook() OSCtxSw(), OSIntCtxSw().OSTaskStatHook() OSTaskStat().OSTimeTickHook() OSTimeTick().OSTCBInitHook() OS_TCBInit().OSTaskIdleHook() OS_TaskIdle().OSInitHookBegin() On Entering OSInit().OSInitHookEnd() On Leaving OSInit().


OS_CPU_A.ASM

어셈블러로만 작성될 수 있는 코드 유지.

다음 4가지 함수를 유지.OSStartHighRdy()

최우선 순위의 Task를 실행하는 함수.

OSCtxSw() 세마포어 Post같은 Task의 요청에 의한 Context Switching

함수.

OSIntCtxSw()Interrupt가 발생하여 Context Switching시 호출되는 함수.

OSTickISR()OS가 사용하는 Tick을 위한 ISR


OS_CPU_A.ASM (OSStartHighRdy())

OSStartHighRdy()목적 : 최우선 순위 Task를 실행하는 함수.

Pseudo-Code for OSStartHighRdy()

void void OSStartHighRdyOSStartHighRdy (void)(void){{

Call Call OSTaskSwHookOSTaskSwHook();();OSRunningOSRunning = TRUE;= TRUE;

// Get the stack pointer of the task to resume;// Get the stack pointer of the task to resume;StackPointerStackPointer = = OSTCBHighRdyOSTCBHighRdy-->>OSTCBStkPtrOSTCBStkPtr;;

Restore all CPU registers from the new taskRestore all CPU registers from the new task’’s stack;s stack;Return to new task.Return to new task.

}}


OS_CPU_A.ASM (OSStartHighRdy())

OSStartHighRdy() for ARM9

OSStartHighRdyOSStartHighRdyBL BL OSTaskSwHook OSTaskSwHook ; Call user defined task switch hook; Call user defined task switch hook

LDR r4,=LDR r4,=OSRunning OSRunning ; Indicate that multitasking has started; Indicate that multitasking has startedMOV r5,#1 ; MOV r5,#1 ; OSRunningOSRunning = 1= 1STRB r5,[r4]STRB r5,[r4]

LDR r4,=LDR r4,=OSTCBHighRdy OSTCBHighRdy ; Get highest priority task TCB address; Get highest priority task TCB addressLDR r4,[r4] ; r4 <= LDR r4,[r4] ; r4 <= OSTCBHighRdyOSTCBHighRdy-->>OSTCBStkPtrOSTCBStkPtrLDR sp,[r4] ; SP <= LDR sp,[r4] ; SP <= OSTCBHighRdyOSTCBHighRdy-->>OSTCBStkPtrOSTCBStkPtr

LDMFD sp!,{r4} ; pop new task's LDMFD sp!,{r4} ; pop new task's spsrspsrMSR SPSR_cxsf,r4MSR SPSR_cxsf,r4LDMFD sp!,{r4} ; pop new task's LDMFD sp!,{r4} ; pop new task's psrpsrMSR CPSR_cxsf,r4MSR CPSR_cxsf,r4LDMFD sp!,{r0LDMFD sp!,{r0--r12,lr,pc} ; pop new task's r0r12,lr,pc} ; pop new task's r0--r12,lr & pcr12,lr & pc


OS_CPU_A.ASM (OSCtxSw())

OSCtxSw()목적 : Task의 요청에 의한 Context Switching을 수행하는 함수.

Pseudo-Code for OSCtxSw() void void OSCtxSwOSCtxSw(void)(void){{

Save CPU registers.Save CPU registers.//Save the current task//Save the current task’’s SP into the current tasks SP into the current task’’s OS_TCBs OS_TCBOSTCBCurOSTCBCur-->>OSTCBStkPtrOSTCBStkPtr = SP;= SP;

OSTaskSwHookOSTaskSwHook();();

OSTCBCurOSTCBCur = = OSTCBHighRdyOSTCBHighRdy;;OSPrioCurOSPrioCur = = OSPrioHighRdyOSPrioHighRdy;;

// Get the stack pointer of the task to resume.// Get the stack pointer of the task to resume.SP = SP = OSTCBHighRdyOSTCBHighRdy-->>OSTCBStkPtrOSTCBStkPtr;;

Restore all CPU registers from the new taskRestore all CPU registers from the new task’’s stack.s stack.Return to new task.Return to new task.

}}


OS_CPU_A.ASM (OSCtxSw())

OSCtxSw() for ARM9OSCtxSw

STMFD sp!,{lr} ; PUSH PCSTMFD sp!,{r0-r12,lr} ; PUSH all CPU register and LRMRS r4,cpsrSTMFD sp!,{r4} ; PUSH CPSRMRS r4,spsrSTMFD sp!,{r4} ; PUSH SPSR

LDR r4,=OSPrioCur ; OSPrioCur = OSPrioHighRdyLDR r5,=OSPrioHighRdyLDRB r6,[r5]STRB r6,[r4]

LDR r4,=OSTCBCur ; Get current task TCB addressLDR r5,[r4]STR sp,[r5] ; Store sp in preempted tasks's TCB

BL OSTaskSwHook ; call Task Switch Hook

LDR r6,=OSTCBHighRdyLDR r6,[r6]LDR sp,[r6] ; get new task's stack pointer

STR r6,[r4] ; set new current task TCB addressLDMFD sp!,{r4} ; pop new task's spsrMSR SPSR_cxsf,r4LDMFD sp!,{r4} ; pop new task's psrMSR CPSR_cxsf,r4LDMFD sp!,{r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc1


OS_CPU_A.ASM (OSIntCtxSw())

Interrupt가 발생하여, Task Switching이 발생하는 경우.



Pseudo-Code for OSIntCtxSw()A lot of the code is identical to OSCtxSw() except

Need not save the CPU registers (already done by ISR)

Should adjust stack pointer.

void void OSIntCtxSwOSIntCtxSw(void)(void){{

Adjust the stack pointer to remove calls to Adjust the stack pointer to remove calls to OSIntExitOSIntExit(), (), OSIntCtxSwOSIntCtxSw();();//Save the current task//Save the current task’’s stack pointer in the current tasks stack pointer in the current task’’s OS_TCB.s OS_TCB.OSTCBCurOSTCBCur-->>OSTCBStkPtrOSTCBStkPtr = = StackPointerStackPointer;;

OSTaskSwHookOSTaskSwHook();();

OSTCBCurOSTCBCur = = OSTCBHighRdyOSTCBHighRdy;;OSPrioCurOSPrioCur = = OSPrioHighRdyOSPrioHighRdy;;

//Get the stack pointer of the task to resume//Get the stack pointer of the task to resumeStackPointerStackPointer = = OSTCBCurOSTCBCur-->>OSTCBStkPtrOSTCBStkPtr;;Restore all processor registers from the new taskRestore all processor registers from the new task’’s stack.s stack.Execute a return from interrupt instruction.Execute a return from interrupt instruction.

}}



OSIntCtxSw() for ARM9OSIntCtxSw()는 Flag만 세트.

ISR에서 위의 Flag를 체크하여 Context Switching 실행.

OSIntCtxSwLDR r0,=OSIntCtxSwFlag ; OSIntCtxSwFlag = TrueMOV r1,#1STR r1,[r0]MOV pc,lr

UCOS_IRQHandlerSTMFD sp!,{r0-r3,r12,lr} ; 아래의함수에서사용되는 Register 저장.

; APCS에따라, r0-r3만을저장함.BL OSIntEnter ; ISR에진입하였음을설정BL C_IRQHandler ; ISR HandlerBL OSIntExit ; ISR을빠져나오면서, Task Switching 처리

LDR r0,=OSIntCtxSwFlag ; Task Switching이일어나야하는가?LDR r1,[r0]CMP r1,#1BEQ _IntCtxSw ; Task Switching이필요하면 _IntCtxSw로.

LDMFD sp!,{r0-r3,r12,lr} ; 아니면, 그냥 Return.SUBS pc,lr,#4



_IntCtxSw_IntCtxSw

MOV r1,#0 ; OSIntCtxFlag = 0STR r1,[r0]

LDMFD sp!,{r0-r3,r12,lr} ; ISR이저장한 Stack 내용 POP.STMFD sp!,{r0-r3} ; 도중사용을위해 IRQ 스택에 r0-r3만저장.MOV r1,sp ; adjust SP_irq ADD sp,sp,#16SUB r2,lr,#4

MRS r3,spsr ; 현재 Task의 PSR에 NOINT로설정하여,ORR r0,r3,#NOINTMSR spsr_c,r0 ; 이를 SPSR에넣고,LDR r0,=.+8MOVS pc,r0 ; 원래Mode로진입함.

STMFD sp!,{r2} ; PUSH current task’s PCSTMFD sp!,{r4-r12,lr} ; PUSH current task's r4-r12,lrMOV r4,r1 ; r4 = SP_irqMOV r5,r3 ; r5 = SPSR_irq (PSR of current task)LDMFD r4!,{r0-r3} ; IRQ 스택에저장한 r0-r3 POP.STMFD sp!,{r0-r3} ; PUSH current task’s r0-r3.STMFD sp!,{r5} ; PUSH current task’s CPSR.MRS r4,spsrSTMFD sp!,{r4} ; PUSH current task’s SPSR.

LDR r4,=OSTCBCur ; Get current task TCB addressLDR r5,[r4] ; 현재 Task의스택포인터저장.STR sp,[r5] ; OSTCBCur->OSTCBStkPtr = SP



_IntCtxSw (continued)

새로운 Task로 스위칭. (OSCtxSw()와 동일)

BL BL OSTaskSwHook OSTaskSwHook ; call Task Switch Hook; call Task Switch Hook

LDR r4,=LDR r4,=OSPrioCur OSPrioCur ; ; OSPrioCurOSPrioCur = = OSPrioHighRdyOSPrioHighRdyLDR r5,=LDR r5,=OSPrioHighRdyOSPrioHighRdyLDRB r5,[r5]LDRB r5,[r5]STRB r5,[r4]STRB r5,[r4]

LDR r6,=LDR r6,=OSTCBHighRdy OSTCBHighRdy LDR r6,[r6] ; get new task's stack pointerLDR r6,[r6] ; get new task's stack pointerLDR sp,[r6] ; LDR sp,[r6] ; StackPointerStackPointer = = OSTCBCurOSTCBCur-->>OSTCBStkPtrOSTCBStkPtr;;

STR r6,[r4] ; STR r6,[r4] ; OSTCBCurOSTCBCur = = OSTCBHighRdyOSTCBHighRdy

LDMFD sp!,{r4} ; pop new task's LDMFD sp!,{r4} ; pop new task's spsrspsrMSR SPSR_cxsf,r4MSR SPSR_cxsf,r4LDMFD sp!,{r4} ; pop new task's LDMFD sp!,{r4} ; pop new task's psrpsrMSR CPSR_cxsf,r4MSR CPSR_cxsf,r4

LDMFD sp!,{r0LDMFD sp!,{r0--r12,lr,pc} ; pop new task's r0r12,lr,pc} ; pop new task's r0--r12,lr & pcr12,lr & pc


uCOS Multi-task Program(1/3)

void Main(void)

{

System_Init();

OSInit();

OSTaskCreate(TaskStart, (void *)0, (void *)&TaskStartStk[TASK_STK_SIZE - 1], 0);

OSStart();

}



void TaskStart (void *data)

{

data = data;

Timer0_Start();

OSTaskCreate(Task1, (void *)0, (void *)&TaskStk[1][TASK_STK_SIZE - 1], 2);

OSTaskCreate(Task2, (void *)0, (void *)&TaskStk[2][TASK_STK_SIZE - 1], 3);

while(1) {Uart_Printf(“a task");

}

OSTimeDlyHMSM(0, 0, 1, 0);

}



void Task1(void *data)

{

while(1) {

Led_Display(1);


Led_Display(2);


}

}

void Task2(void *data)

{

while(1) {

Uart_Printf("₩r₩nTEST ₩r₩n₩r₩n");


}

}


Application Program Test

1. UART Programming



UART

Universal Asynchronous Receiver and Transmitter3 개의 interrupt 혹은 DMA 기반의 UART

최고 115200bps 지원( 그 이상 지원을 위해 외부 클럭 필요)

Two 16 bytes FIFOs, infra-red(IR) Tx/Rx support


UART Operations

Data transmissionStart bit, 5~8 data bits, parity bit(option), 1 ~ 2 stop bits

Break condition: 0 state for 1 frame transmission time

Data receptionStart bit, 5~8 data bits, parity bit(option), 1 ~ 2 stop bits

Set error flags

Overrun error: when received data has overwritten

Parity error: unexpected parity condition

Frame error: No valid stop bit

Break condition

Receive time-out condition


UART Operations

Interrupt Request Generation

Baud-Rate GenerationBaud rate divisor UBRDIV = (int)(PCLK|UCLK/(bps*16))-1

PCLK: UART reference clock

Baud rate: 110, 1200, 2400, 9600, 14400, 19200, 38400, 57600, 76800, 115200

Ex) baud-rate: 115200 bps, PCLK = 40MHzUBRDIVn = (int)(40000000/(115200x16))-1 = (int)(21.7)-1 = 20

All errors

Transmit data becomes empty

receive data becomes fullNon-FIFO modeFIFO mode

Frame error, Parity error, break signalOverrun when RFIFO is full

Error interrupt

TFIFO reaches trigger levelTx interrupt

1. RFIFO reaches trigger level2. RFIFO does not reaches trigger

level and no data during 3 word timeRx interrupt

Type


UART Registers(1/4)

ULCON: UART Line Control Register (0x00)

UCON: UART Control Register (0x00)

5 030 Parity Mode

Infra-Red Mode0: Normal mode, 1: IR mode

Data bit size00: 5, 01: 6, 10: 7, 11: 8

Word Len2 1

SI67

Stop bit size0: 1, 1: 2

Parity Mode0xx: No parity,100: Odd, 101: Even, 110: parity forced as 1111: parity forced as 0

5 03RTO SB

For tramsmit/receive buffer register00: diable, 01: interrupt request or polling10: DMA0 request for UART0

DMA3 request for UART211: DMA1 request for UART1

R Mode2 1

LBREI67

Send break

T ModeRITTIT89

Loop back modeRx error state interrupt

Rx time out enableRx interrupt type0: pulse, 1: level

Tx interrupt type0: pulse, 1: level

CS10

Clock Selection 0: PCLK, 1: UCLK


UART Registers(2/4)

UFCON: UART FIFO Control Register (0x00)5 03RFTL

TFIFO Trigger Level00: empty, 01:4B, 10: 8B, 11: 12B

RFIFO Reset

UMCON: UART Modem Control Register (0x00)

FE2 1

TFRTFTL67

TFIFO Reset

5 030 0 0 AFC

Request to Send0: inactivate nRTS 1: activate nRTSWhen AFC is disabled

RTS167

Auto Flow Control0: disable1: enable

0 0 0

FIFO Enable

RFR04

RFIFO Trigger Level00:4B, 01: 8B, 10: 12B, 11: 16B

UBRDIV: UART Baud Rate division Register (0x0000)0

>015


UART Registers(3/4)

UTRSTAT: UART Tx/Rx Status Register (0x6)0

Transmit buffer empty for Non-FIFO

UERSTAT: UART Error Status Register (0x00)

RBR2 1

TE

Transmitter empty1: Transmit buffer & shifter register empty

Receive buffer data ready for Non-FIFO

TBE

0

Parity error

OE2 1

FE

Frame error

Overrun error

PE3

BD

Break Detect

UTXH: UART Transmit Buffer Register (0x00)URXH: UART Receive Buffer Register (0x00)

07


UART Registers(4/4)

UFSTAT: UART FIFO Status Register (0x00)5 03

Number of data in Rx FIFO

Rx FIFO Count2 167

RFFTFF89

Rx FIFO Full0: not full, 1: full

Tx FIFO Count

Number of data in Tx FIFO

Tx FIFO Full0: not full, 1: full


Application Program

주 실험 프로그램 : xx_main.c

ARM Project 프로그램 : xx_main.apj

(SDT compiler 기준)

전체 프로젝트 폴더

Startup : 2410init.s, 2410addr.a, Memcfg.a, Option.a

Ex. Driver : 2410addr.h, uart.c, uart.h, ioport.c, ioport.h

SDMK2410


Final Project

Keyboard Driver

LCD Driver

Barbel Shop Problem



Keyboard Experiment


Keyboard encoder (Block Diagram)

SPI Comm. Channel

Interface to host CPU.

Keyboard Scanner & State Control

Scans 8x14 matrix

Implements 3 modes

Power Management

Minimize power drain.

Drain 20uA in the stop mode.

System Monitor Input Signal

Used to maintain state control.

Programmable I/O

General purpose I/O

Can be used as a wake-up signal.


Keyboard encoder (Operation)

Keyboard Scanner

매 512us 마다, 1개 column lines(C0-C13)을 선택하여 R0-R7을 읽으며, 눌려진 키는 R0-R&에서 Low로 나타난다.모든 Column Lines에 대해 검사하는 것은 약 9.2ms가 걸린다.Debounce 및 Ghost key를 제거한 후, 해당 키 코드는 SPI Channel의 Transmit Buffer로 저장된다.

Keyboard Scanning

N-Key Rollover 방식 사용.눌려진 Key가 발견되기만 하면, 다른 키가 눌려진 상태가 있더라도 SPI Channel을 통하여 Host로 보내어짐.눌려진 Key가 release될 경우, 해당 break code가 SPI Channel을 통하여 Host로 보내어짐.


Keyboard encoder (State)

Three modes of keyboard and switch operation

Related to power States

Send All Keys

Normal state

Send Wake-up Keys Only

Entering when WUKO(Wake-Up Key Only) Signal is active.

Transmit only keys programmed to be wake-up keys.

Send No Keys

Entering on critically low level of battery voltage.


SPI Operation Procedure

Initialization.

Set a GPIO Control Reg. to function as SPI.

SPI0 : GPECON, GPGCON

SPI1 : GPGCON

Set Baud Rate Prescaler Reg. (SPREn)

Set SPICONn to configure properly the SPI module.

SPI Master and Slave must use the same parameters.

Parameters : CPOL(Clock Polarity), CPHA(Clock Phase)

SPI Read/Write Operation.

(1) Set nSS(GPIO) to low to activate the Slave.

(2) checks REDY(SPSTAn) and write data to SPTDATn.

(3) wait until REDY(SPSTAn) is set.

(4) Set nSS(GPIO) to high to deactivate the Slave and read the data from SPRDATn .


Interface to Keyboard.

Interface to key coder

Interrupt : EINT1

SPI Interface : SPI1

nSS : GPB[6]

Sequence

(1) Key Stroke.

(2) Interrupt to CPU. (using ATN-EINT1)

(3) Start Read/Write Operation.

S3C2410

EINT1

MOSI

MISO

SCLK

GPB[6]

SPI1

UR5HCSPI-SA

ATN

MOSI

MISO

SCLK

nSS


Key Codes

Key CodesRange from 1 to 0x73

Key Scan CodeScan Code = Column Number * 8 + Row Number + 1

Break Code = Scan Code | 0x80

Key CalculationColumn Number

[Scan Code / 3]

Row Number

Scan Code % 8 -1


Keyboard ISR Routine.

KBD_ISR() {

// SPI Read on TAGD bit diable.// Refer 22-3. S3C2410X01CLEAR_KBD_nSS(); // First, nSS to Low.while(!(rSPSTA1&0x1)); // Check ready staterSPTDAT1=0xFF; // Second, Dummay data to SPTDATnwhile(!(rSPSTA1&0x1)); // Check ready stateSET_KBD_nSS(); // Third, nSS to High.

data = rSPRDAT1; // Then, Read the data.

if ( data & 0x80 ) {// Ignore released key code.;

} else {key = GET_SCAN_CODE(data);if ( key & 0x8000 ) {

/* If Special Key ... */;

} else {PutKbdBuf( key );

}}

}


LCD Experiment


TFT LCD displays featuresSupports 1, 2, 4 or 8 bpp palettized color displays for TFT.

Supports 16, 24non-palettized true-color displays for color TFT.

Supports maximum 16M color TFT at 24-bit per pixel mode.

Support multiple screen size

640*480, 320*240, 160*160

Maximum virtual screen size(16 bpp mode) : 2048*1024

LCDSADDR1/2 : LCDBASEU, LCDBASEL

Before scrolling...

After scrolling...

LCDBASEU

LCDBASEL

OFFSIZE PAGEWIDTH

LINEVAL+1

View Port(LCD panel size)

OFFSIZE


LCD Controller

REGBANK17 programmable registers set256*16 palette memory

LCDCDMAtransfer the video data in frame memory to LCD drivercan be displayed on the screen without CPU intervention

VIDPRCSReceives the video data from LCDCDMASend the video data through the VD[23:0] data port to the LCD driver after changing data format

TIMEGENTiming and ratesGenerates VFRAME, VLINE, VCLK, VM(STN) / VSYNC, HSYNC, VCLK, VDEN(TFT)

System Bus

REGBANK TIMEGEN

LCDCDMA VIDRPCS VD[15:0]

LPC3600

VIDEOMUX

LPC3600 : LTS350A1-PD1 or LTS350Q1-PD2


EXTERNAL INTERFACE SIGNAL(1/2)

VFRAME / VSYNC Frame synchronous signal (STN)Vertical synchronous signal (TFT)

VLINE / HSYNCLine synchronous pulse signal (STN)Horizontal synchronous signal (TFT)

VCLKPixel colock signal (STN / TFT)

VD[23:0]LCD pixel data output ports (STN / TFT)

VM / VDENAC bias signal for the STN LCD driver (STN)Data enable signal (TFT)

LENDLine end signal (TFT)

LCD_PWRENLCD panel power enable control signal


EXTERNAL INTERFACE SIGNAL(2/2)


LCD PALETTE USAGE

Palette supports 5:6:6(R:G:B) and 5:5:5:1(R:G:B:I) format

#define PALETTE (0x4D000400)

Read/Write OperationVSTATUS of LCDCON5 register must be checked


LCD Palette Usage(TFT) 1/3

8bpp(bit per pixel)

Palette : 0x4D000050, 5:6:5=R:G:B

static const unsigned short DEMO256pal[]

={0xf800, 0x07e0, 0x001f, 0xffff, };

static const unsigned char DEMO256[]

={0x01, 0x01, 0x02, 0x02, 0x01, 0x01,};

256color * 16bit = 64K Color

8bit : 256 Color

16bpp



24 bpp

static const unsigned char DEMO256(16)[]

={0xf80000, 0x00f800, 0x0000f8, ,};

static const unsigned char DEMO256(24)[]

={0xff0000, 00ff00, 0000ff, ,};



for(i=starty; i<endy; i++) //y

{

for(j=0; j<240; j++)//x

{

frameBuffer8BitTft[(i)][(j)/4]=

( frameBuffer8BitTft[(i)][j/4]

& ~(0xff000000>>((j)%4)*8) ) |

( ((int)TEMP[j+(i%53)*240])<<((4-1-((j)%4))*8) );

}

}

0 000 0 0001 1 11111 11111 111 11 1111 1 11

1010 0 01111 00110 110110 101 1 0111 1 11

BIT CLEAR BIT MASK

AB

A

B

1 001 1 0100 0 00000 00000 000 00 0000 0 00

C

C

&

| 0000 0 00011 00110 110110 101 1 0111 1 11


Program Flow

MMU_Init()

MMU_EnableICache()

Port_Init()

Isr_Init()

Uart_Init(0,115200)

( (void (*)(void)) (function[i][0]) )()

Palette_Init()

Lcd_Port_Init()

Lcd_Init(MODE_TFT_8BIT)

Glib_Init(MODE_TFT_8BIT)

Glib_ClearScr(0, MODE_TFT_8BIT)

Glib_Rectangle(0,0,239,319,255)

Glib_Line(0,0,239,319,255)


Final Project 1

Job 1 : Display bumping ball to LCDJob 2 : Display text editor to LCDJob 3 : Display kernel statistics to console



Layout of LCD screen

Hello

This is text editor screen•Text editor

•Bumping Ball


Final Project 2

Solving Barber Shop Problem


Barber Shop Modeling

무엇을 모델링할 것인가?Door

CasherSofas

Barber Chairs

Barbers

Customers


Barber Shop Modeling

태스크로 정의되어야 하는 오브젝트는? Customers, barbers, casher…

리소스로 정의되어야 하는 오브젝트는? Barber shop, Sofas, barber chairs, money, and receipt…

태스크 오브젝트와 리소스 오브젝트의 관계는?

Customers barber shop

Customers sofas

Customers barbers

Barbers casher


Barber Shop Modeling( Job Slicing Example )

Customerenter the barber shopsit on one of the sofassit on a barber chairlet others sit on the sofalet a barber cut my hairstand up from the barber chairleave the barber chairpayexit shop

Barberchoose one who is the nextcut hair

Cashieraccept pay


Display Example

OutDoor : ABCDEFGHIJKLMNOPQRSTUVWXYZ

InDoor : ABCDEFGHIJKLMNOPQRSTUVWXYZ

Sofa : ABCDEFGHIJKLMNOPQRSTUVWXYZ

Barber Chair: ABCDEFGHIJKLMNOPQRSTUVWXYZ

Cashier : ABCDEFGHIJKLMNOPQRSTUVWXYZ

OutDoor : YZ

InDoor : STUVWX

Sofa : PQR

Barber Chair: MNO

Cashier : L

OutDoor : ABCDEFGHIJKLMNOPQRSTUVWXYZ

InDoor :

Sofa :

Barber Chair:

Cashier :


Appendix

Appendix01. ARM 개발 환경Appendix02. S3c2410Appendix03. SMDK2410Appendix04. BMP(bit map file format)Appendis05. WAVE PCM soundfile format



Appendix01. ARM 개발 환경

ADS(ARM DEVELOPER SUITE ) 1.2

Openice900


ADS Major Components

Code Generation ToolsARM and Thumb

ANSI C Compilers

Embedded C++ Compilers

Assemblers, Linker

C and C++ runtime libraries

CodeWarrior IDEProject manager

Integrated build facilities

Integrated editor

GUI tool configuration

DebuggersGUI (AXD)

Command-line

Debug TargetsARMulator, Instruction Set Simulator

Angel debug monitor

Multi-ICE JTAG

ARM Firmware SuiteAngel debug monitor

MicroHAL

ARM Applications Library

DocumentationOnline – hypertext based

Hardcopy

On-line help


ARM Firmware Suite (AFS)

What’s Firmware?Low level software that initializes a system’s hardware

Firmware Suite objectives and strategyProvide low level driver and support routines with standard API (uHAL)

Runs on bare metal or as part of a semi-hosted application

Introduce a more modular approachDeliberately restricted in scope/features

Processor specifics separated out

Well partitioned board specific code

Easily re-targeted to different platforms

Reusable, OS neutral

Included in ADSAngel debug monitor

MicroHAL

ApplicationRTOS

C Libs

Hardware platform

MicroHAL

Angel


ARM Application Library

What is the ARM Applications LibraryHighly optimized software suite of useful routinesHandcrafted by ARM architecture experts

Excellent examples of how to optimize for ARM

Royalty free inclusion in application software

Some of the functions in the Application LibraryDSP Transformations – DCT, FFT

DSP Filtering – FIR, IIR & LMS

Mathematics

…


OPENice32-A900 (JTAG Debug Tool)

Support a variety of ARM coresARM7TDMI,ARM720T,ARM9TDMI,ARM920T, ARM922T, ARM940T, ARM1020 including CDMA and Wireless Devices

Non-Intrusive

User Friendly GUI SMU setting

High speed Downloading (USB/Ethernet)-190Kbps

Flash Downloading & Debugging

Support S/W and H/W Breakpoint

Writing & Reading data to SFR

On-Board Programming

Support ARM SDT/ADS and Linux GDB

Convenient and rapid firmware upgrade


Development Environment

Debug Host

Target Board

JTAG Cable

Serial Port CableorUSB/Ethernet Cable

Serial Port Cable

OPENice32-A900


About Code Warrior for the ADS

Metrowerks CodeWarior IDE version 4.0

ARM-specific configuration panels that enable you to Configure the ARM development tools

Project Manager

armccC Compiler

armasmAssembler

armlinkLinker

armlibLibrarian

Image Code runsource

*.c

*.s

*.o

*.o

*.axf

*.b


Software Development Process

C소스파일

어셈블리소스파일

컴파일러 어셈블러

형식변환기

ROMWriter

시뮬레이터에뮬레이터매스크 공정

링커

라이브러리처리기

오브젝트파일

오브젝트파일

라이브러리

실행파일

ROM,프로세서

하드웨어에뮬레이션

소프트웨어에뮬레이션

HEX파일

다운로더

시스템메모리

EPROM,프로세서


Project

New ProjectExecutable Image, Object Library, Makefile Importer Wizard

Add Files to Project

Current Build TargetRelease

Debug

DebugRel


Build Target Settings

Target Settings

ARM C CompilerArchitecture or Processor

Byte order

Optimization Level

Preprocessor

ARM LinkerLinkType

RO base(0x030000000)

RW base

ARM from ELFOutput format


Appendix02. S3c2410

• Block Diagram and Features

• Memory Controller

• Timer

• UART

• Interrupt Controller

• I/O Ports


CellularSmartphones

GPS

Printer

S3C2410 RISCMicroprocessor

PDA / Organizers

Palm PC

Digital STB and NCse-Book

S3C2410 Applications


S3C2410 Block Diagram

ARM920T

JTAGARM9TDMI

Processor core(Internal Embedded ICE)

WriteBackPA Tag

RAMDataMMU

InstructionCACHE(16KB)

InstructionMMU

ExternalCoproc

Interface

AMBABusI/F

DataCACHE(16KB)

Bridge & DMA(4Ch)

AHB

BUS Memory CONT.

SRAM/NOR/SDRAM

BUS CONT.Arbitor/Decode

PowerManagement

Interrupt CONT.USB Host CONT.

ExtMaster

LCDDMA

LCDCONT.

I2C

GPIO

I2S

SPI 0, 1

ADC

UART 0, 1,2

SDI/MMC

USB Device

WatchdogTimer

BUS CONT.Arbitor/Decode

Timer/PWM0~3,4(internal)

RTC

Clock Generator(MPLL/UPLL)

NAND CONT.NAND Flash Boot

Loader

APB

BUS


S3C2410 Features(1/4)

Integrated System for hand-held devices and general embedded applications

ARM920T + IP (Intellectual Property)

System Manager8 banks each of which 128Mbyte 1Gbyte

6 memory banks for ROM, SRAM

2 memory banks for ROM, SRAM, SDRAM

Programmable size and access cycles

Clock & Power ManagerClock can be fed selectively to each block by software

Normal, Slow, Idle, Stop, SL_IDLE mode



Interrupt Controller55 Interrupt source

Timer with PWM (Pulse Width Modulation)4-ch 16-bit Timer with PWM, 1-ch 16-bit internal Timer

RTC (Real-Time Clock)Full clock feature, 32.768 KHz operation

General Purpose Input/Output Ports24 external interrupt ports

117 multiplexed input/output ports

UART3-channel UART with DMA-based/interrupt-based

DMA Controller 4-ch DMAC with burst transfer mode



A/D Converter8-ch multiplexed ADC

LCD ControllerSTN LCD support

TFT LCD support

1, 2, 4, 8 bpp palette color displays

16 bpp non-palette true-color displays

640x480, 320x240, 160x160

NAND Flash Boot LoaderSupports booting from NAND Flash memory

4KB internal buffer for booting

Supports storage memory for NAND Flash memory after booting



Watchdog Timer16-bit with interrupt request or system reset at time-out

IIC-BUS interface1-ch multi-master IIC-Bus

IIS-BUS interface1-ch IIS-bus for audio interface with DMA-based

USB 1.12-port host, 1-port device

SD Host interfaceSDIO Card, SD Memory Card Protocol version 1.0

Multimedia Card Protocol version 2.11

SPI interface2-ch Serial Peripheral Interface Protocol version 2.11 compatible


Memory Controller

0x0000_0000

SROM/SDRAM(nGCS7)

SROM/SDRAM(nGCS6)SROM

(nGCS5)SROM

(nGCS4)SROM

(nGCS3)SROM

(nGCS2)SROM

(nGCS1)Boot InternalSRAM(4KB)

0x4000_0000

0x3800_0000

0x3000_0000

0x2800_0000

0x2000_0000

0x1800_0000

0x1000_0000

0x0800_0000128MB

128MB

2/4/8/16/32/64/128MB

128MB

128MB

128MB

128MB

1GBHADDR[29:0]

2/4/8/16/32/64/128MB

0x4800_0000

Special FunctionRegister(APB)

Special FunctionRegister(AHB)

0x57FF_FFFF

0x5000_0000

SROM/SDRAM(nGCS7)

SROM/SDRAM(nGCS6)SROM

(nGCS5)SROM

(nGCS4)SROM

(nGCS3)SROM

(nGCS2)SROM

(nGCS1)SROM

(nGCS0)

OM[1:0]=01,10 OM[1:0]=00

Not using NAND flash for boot ROM

Using NAND flash for boot ROM


Clock & Power Management

12MHz


Timer

Timer Period CalculationTimer Clock [Hz] = PCLK/(Prescaler+1)/Division Factor

Min: 66M/256/16 = 16.1133KHz (62.0606 uS)

Max: 66M/1/2 = 33MHz (0.0303uS)

Timer Duration[sec] = (Data value+1) X Timer Clock Period

Max: 65536X62.0606uS = 4.0671 sec

Low Duration = (Data value +1 – Compare value) X Timer Clock Period

8-bitPrescaler TOUT

ControlLogic

TCMPB1/2

1/4

1/8

1/16

MU

XTCNTB

MU

X

PCLK Clockdivider

TCLK

Timer Clock

TCMP TCNT


Timer Operations

Basic Timer Operation

Interrupt request

TCNTBn=3TCMPBn=1Manual update=1Auto-reload=1

TCNTn 3 03 0

1 0TCMPn

TCNTBn=2TCMPBn=0Manual update=0Auto-reload=1

Start bit=1 Timer is started TCNTn=TCMPn Auto-reload

Interrupt request

Auto-reload=0

TCNTn=TCMPn

2 1 0 2 1

Timer is stopped

TOUTn


UART

Universal Asynchronous Receiver and Transmitter


Interrupt Controller

FeaturesFIQ or IRQ to ARM920T after arbitration

55 interrupt source (24 external, 31 internal)

Fixed or Rotate Priority

SRCPND

IRQ

MASK

MODE

PRIORITY

INTPND

INTOFFSET

FIQ


I/O Ports

Features117 multi-functional input/output pins

Port A (GPA): 23 output ports

Port B (GPB): 11 in/out ports

Port C (GPC), Port D (GPD), Port E (GPE): 16 in/out ports

Port F (GPF): 8 in/out ports

Port G (GPG): 16 in/out ports

Port H (GPH): 11 in/out port

If the multiplexed functions on a pin are not used…


Appendix03. SMDK2410


SMDK2410 Overview

Evaluate basic operations of SC32410 and develop codes

ComponentsEvaluation board and Accessories

Monitor program, Libraries, Example applications

FeaturesBoot ROM : AMD 8Mbit 1 EA HW size boot ROM: 1MB

Intel StrataFlash 16MBx3 SAMSUNG NAND flash 64M-byte 1EA (smart media card)

SDRAM: 32M Byte 2EA: 64MB

TFT LCD and Touch panel interface

3-ch UART, 2-port USB host

SD host(MMC) interface, Smart media card, Multi-ICE interface,

RTC X-tal input logic, IIC, ADC interface

SPI interface, IIS interface, EINT interface, IrDA interface

64 keyboard, Ethernet interface, PCMCIA interface, LED display


SMDK2410 (S3C2410 Evaluation Board)

EthernetSocket

PCMCIASocket

nGCS0 or nGCS1

ATX Power Input

Regulator(1.8V) PeripheralPower

ARM920TS3C2410X01

VDDMPLL

VDDRTC VDDCPU

VDDUPLL VDDIO

VDDADC

5V3.3V 3.3V 12V

UART2IrDA

MMCSocketReset

Switch

EINT nSwitches

USBHost

USBDevice

USBHost

AMD FLASH(Bank0 or Bank1)

STRATA FLASH(Bank1 or Bank0)

nGCS1 or nGCS0

SDRAM(Bank6)

nGCS6

RTC X-tal(32.7KHz)

Main X-tal(12MHz)

DATA/ADDR/Cont.

IIS

MIC SPKJack

Keyboard Cont.

UART0COM1

UART1COM2

MAX3232C MAX3232C

PowerLED

MainSwitch

Status LED

Ext.Headers

SmartMedia Card

LCDConnector

IIC

SPI Connector

ADC Connector

Touch panel

JTAG Port

DC/DC


Application Program Environment

SMDK2410 Board

Boot Program- vector handler- system init

Libraries

Application Program

SMDK2410 Board

BSP

Embedded OS

Application Program

Single Thread Application Multi Thread Application


Setup Environment

LPT1

USB host

USB host USB device

JTAGS3C2410X01

SMDK2410

OPENice32-A900

Host PC

USB cable

12V5V3.3V

ATX power

1.8V

RegulatorUART0

COM1RS232 cable


Address Space Design

0x00000000

4GB

256MB

256MB0x10000000

0x20000000

0xF00000000xFFFFFFFF

256MB

128MB

128MB0x00000000

128MB

128MB

128MB

128MB

128MB

128MB

0x08000000

0x10000000

0x30000000

0x38000000

128MB

0x48000000

1MB

0x5FFFFFFF

256MB

8MB

8MB

8MB

8MB

8MB

8MB

8MB

8MB

0x000000000x000FFFFF

0x30000000

0x320000000x31FFFFFF

0x33FFFFFF

AMD Flash

SDRAM

ARM Address Space

S3C2410 Address Space

SMDK2410 Address Space

32MB

0x08000000

0x0BFFFFFF

Intel Flash0x30000000

0x40000000

0x50000000

256MB

256MB

256MB

256MB

128MB0x50000000


Address Space Design

0x30000000

64MB

DownlodArea16MB

0x31000000

0x33FFFFFF

4KB

0x33FFFFFF

Video Data

SDRAM Address Partition SMDK2410 Initialize Routine

0x32000000

NonCachable

16MB

Cachable

0x33FF0000

64KB0x33FF8000

3KB

1KB

1KB

1KB

1KB

1KB

HandleReset4KB

4KB

4KB

4KB

4KB

4KB

4KB

Heap &RW Area

24KB

Stack Area8KB

HandleUndefHandleSWI

HandlePabortHandleDabort

HandleReserveHandleIRQHandleFIQ

HandleEINT0

HandleTIMER0

HandleRTC. . .

. . .

0x33FFFF000x33FFFF04

0x33FFFF1C0x33FFFF20

FIQ Stack

IRQ Stack

Abt Stack

Und Stack

SVC Stack

User Stack

0x33FF7C00

0x33FF7800

0x33FF7400

0x33FF7000

0x33FF6C00

0x33FF8000

TranslationTable0x33FF8000

0x33000000

NonCachable

16MB

NonCachable

16MB-64K

0x33FF4000

0x33FF4800

0x33FFC000256B


Appendix04. Bit Map


BMP

MS-Windows standard format black&white-, 16-color, 256-color, Truecolor의 영상을 표현한다.16-color and 256-color 영상은 run length encoding으로 압축이 가능하다.OS/2-BMP format 도 존재한다.


BMP File Format

File offset to Raster Data4 bytesDataOffset

unused (=0)4 bytesreserved

File size in bytes4 bytesFileSize

'BM'2 bytesSignature

Windows Structure: BITMAPFILEHEADER14 bytesHeader

DescriptionSizeName


BMP File Format (II)

DescriptionSizeName

Bits per Pixel1 = monochrome palette. NumColors = 14 = 4bit palletized. NumColors = 168 = 8bit palletized. NumColors = 25616 = 16bit RGB. NumColors = 65536 (?)24 = 24bit RGB. NumColors = 16M

2 bytesBitCount

Number of Planes (=1)2 bytesPlanes

Bitmap Height4 bytesHeight

Bitmap Width4 bytesWidth

Size of InfoHeader =404 bytesSize

Windows Structure: BITMAPINFOHEADER40 bytesInfoHeader


BMP File Format (III)

DescriptionSizeName

Type of Compression0 = BI_RGB no compression1 = BI_RLE8 8bit RLE encoding2 = BI_RLE4 4bit RLE encoding

4 bytesCompression

ColorsImportant

ColorsUsed

YpixelsPerM

XpixelsPerM

ImageSize

InfoHeader

Number of important colors0 = all4 bytes

Number of actually used colors4 bytes

vertical resolution: Pixels/meter4 bytes

horizontal resolution: Pixels/meter4 bytes

(compressed) Size of ImageIt is valid to set this =0 if Compression = 04 bytes


BMP File Format (IV)

present only if Info.BitsPerPixel <= 8colors should be ordered by importance4 * NumColors bytesColorTable

The pixel dataInfo.ImageSize bytesRaster Data

repeated NumColors times

unused (=0)1 bytereserved

Blue intensity1 byteBlue

Green intensity1 byteGreen

Red intensity1 byteRed

DescriptionSizeName


BMPRaster Data encoding

Depending on the image's BitCount and on the Compression flag there are 6 different encoding schemes. Pixels are stored bottom-up, left-to-right. Pixel lines are padded with zeros to end on a 32bit (4byte) boundary. For uncompressed formats every line will have the same number of bytes. Color indices are zero based, meaning a pixel color of 0 represents the first color table entry, a pixel color of 255 (if there are that many) represents the 256th entry. For images with more than 256 colors there is no color table.


BMPRaster Data encoding for 1bit / black & white images

BitCount = 1

Compression = 0

Every byte holds 8 pixels, its highest order bit representing the leftmost pixel of those.

There are 2 color table entries. Some readers will ignore them though, and assume that 0 is black and 1 is white. If you are storing black and white pictures you should stick to this, with any other 2 colors this is not an issue.

Remember padding with zeros up to a 32bit boundary (This can be up to 31 zeros/pixels!)


BMPRaster Data encoding for 4bit / 16 color images

BitCount = 4

Compression = 0

Every byte holds 2 pixels, its high order 4 bits representing the left of those.

There are 16 color table entries. These colors do not have to be the 16 MS-Windows standard colors.

Padding each line with zeros up to a 32bit boundary will result in up to 28 zeros = 7 'wasted pixels'.


BMPRaster Data encoding for 8bit / 256 color images

BitCount = 8

Compression = 0

Every byte holds 1 pixel. There are 256 color table entries.

Padding each line with zeros up to a 32bit boundary will result in up to 3 bytes of zeros = 3 'wasted pixels'.


BMPRaster Data encoding for 16bit / high color images

BitCount = 16

Compression = 0

Every 2bytes / 16bit holds 1 pixel.

The pixels are no color table pointers.

There are no color table entries.

Padding each line with zeros up to a 16bit boundary will result in up to 2 zero bytes.


BMPRaster Data encoding for 24bit / truecolor images

BitCount = 24

Compression = 0

Every 4bytes / 32bit holds 1 pixel.

The first holds its red, the second its green, and the third its blue intensity. The fourth byte is reserved and should be zero.

There are no color table entries.

The pixels are no color table pointers.

No zero padding necessary.


BMPRaster Data compression for 4bit / 16 color images (I)

BitCount = 4 Compression = 2

The pixel data is stored in 2bytes / 16bit chunks.The first of these specifies the number of consecutive pixels with the same pair of color. The second byte defines two color indices. The resulting pixel pattern will be interleaved high-order 4bits and low order 4 bits (ABABA...). If the first byte is zero, the second defines an escape code. The End-of-Bitmap is zero padded to end on a 32bit boundary. Due to the 16bit-ness of this structure this will always be either two zero bytes or none.


BMPRaster Data compression for 4bit / 16 color images (II)

The following c bytes will be read as single pixel colors just as in uncompressed files. up to 12 bits of zeros follow, to put the file/memory pointer on a 16bit boundary again.>=30

Delta. The following 2 bytes define an unsigned offset in x and y direction (y being up) The skipped pixels should get a color zero.20

End-of-Bitmap10

End-of-line00

n pixels are to be drawn. The 1st, 3rd, 5th, ... pixels' color is in c's high-order 4 bits, the even pixels' color is in c's low-order 4 bits. If both color indices are the same, it results in just n pixels of color c

any>0

Descriptionc (Byte 2)n (byte 1)


BMPRaster Data compression for 4bit / 16 color images (III)

Zero padding for 32bit boundary00 00

EndofBitmap00 01

1 E 1 E 1 E 1 E 109 1E

End-of-line00 00

Move 5 right and 1 up. (Windows docs say down, which is wrong)00 02 05 01

7 8 7 804 78

4 5 5 6 6 700 06 45 56 67 00

0 6 0 6 005 06

0 4 003 04

Expanded dataCompressed Data

Example for 4bit RLE


BMPRaster Data compression for 8bit / 256 color images (I)

BitCount = 8

Compression = 1

The pixel data is stored in 2bytes / 16bit chunks.

The first of these specifies the number of consecutive pixels with the same color.

The second byte defines their color index. If the first byte is zero, the second defines an escape code.

The End-of-Bitmap is zero padded to end on a 32bit boundary.

Due to the 16bit-ness of this structure this will always be either two zero bytes or none.


BMPRaster Data compression for 8bit / 256 color images (II)

The following c bytes will be read as single pixel colors just as in uncompressed files. A zero follows, if c is odd, putting the file/memory pointer on a 16bit boundary again.

>=30

Delta. The following 2 bytes define an unsigned offset in x and y direction (y being up) The skipped pixels should get a color zero.

20

EndOfBitmap10

End-of-line00

n pixels of color number cany>0

Descriptionc (Byte 2)n (byte 1)


BMPRaster Data compression for 8bit / 256 color images (III)

Zero padding for 32bit boundary00 00

End-of-bitmap00 01

1E 1E 1E 1E 1E 1E 1E 1E 1E09 1E

End-of-line00 00

Move 5 right and 1 up. (Windows docs say down, which is wrong)00 02 05 01

78 7802 78

45 56 6700 03 45 56 67 00

06 06 06 06 0605 06

04 04 0403 04

Expanded dataCompressed Data

Example for 8bit RLE


BMPPortability

Although BMPs were invented by Microsoft for its Windows platform, a lot of programs on other platforms are capable of reading and writing them.

Notice the Intel order in 2byte and 4-byte integer values (Least significant byte first).

The 16bit BMPs have been introduced to Windows after the others, still puzzling many applications.


Appendix05. WAVE PCM sound file format


WAV

The WAVE file format is a subset of Microsoft's RIFF specification for the storage of multimedia files.

A RIFF file starts out with a file header followed by a sequence of data chunks.

A WAVE file is often just a RIFF file with a single "WAVE" chunk which consists of two sub-chunks

"fmt " chunk specifying the data format

"data" chunk containing the actual sample data.

Call this form the "Canonical form".


File Format


Format Field (I)

ChunkID Contains the letters "RIFF" in ASCII form (0x52494646 big-endian form).

ChunkSize 36 + SubChunk2Size, or more precisely: 4 + (8 +SubChunk1Size) +

(8 + SubChunk2Size) This is the size of the rest of the chunk following this number. This is the size of the entire file in bytes minus 8 bytes for the two fields not included in this count: ChunkIDand ChunkSize.

Format Contains the letters "WAVE" (0x57415645 big-endian form).


Format Field (II)

The "WAVE" format consists of two subchunks: "fmt " and "data":

The "fmt " subchunk describes the sound data's format:

Subchunk1ID Contains the letters "fmt " (0x666d7420 big-endian form).

Subchunk1Size 16 for PCM. This is the size of the rest of the Subchunk which follows this number.

AudioFormat PCM = 1 (i.e. Linear quantization) Values other than 1 indicate some form of compression.

NumChannels Mono = 1, Stereo = 2, etc.

SampleRate

8000, 44100, etc.


Format Field (III)

ByteRate == SampleRate * NumChannels * BitsPerSample/8

BlockAlign == NumChannels * BitsPerSample/8 The number of bytes for one

sample including all channels.

BitsPerSample8 bits = 8, 16 bits = 16, etc.

ExtraParamSize if PCM, then doesn't exist

ExtraParams space for extra parameters


Format Field (IV)

The "data" subchunk contains the size of the data and the actual sound:

Subchunk2ID Contains the letters "data" (0x64617461 big-endian form).

Subchunk2Size == NumSamples * NumChannels * BitsPerSample/8 This is the number of bytes in the data. You can also think of this as the size of the read of the subchunk following this number.

Data The actual sound data.


Interpretation Example

Data :

52 49 46 46 24 08 00 00 57 41 56 45 66 6d 74 20 10 00 00 00 01 00 02 00 22 56 00 00 88 58 01 00 04 00 10 00 64 61 74 61 00 08 00 00 00 00 00 00 24 17 1e f3 3c 13 3c 14 16 f9 18 f9 34 e7 23 a6 3c f2 24 f2 11 ce1a 0d 4 f2 11 ce 1a 0d


참고 사항

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