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Digital Integrated Circuits © Prentice Hall 1995 Arithmetic Arithmetic Building Blocks Chapter 11 Rabaey
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Arithmetic Building Blocks Chapter 11 Rabaeyramirtha/EEC118/S10/arithmetic.pdf · - Bit-sliced datapath (adder , multiplier, shifter, comparator, etc.) Memory - RAM, ROM, Buffers,

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  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Arithmetic Building Blocks

    Chapter 11 Rabaey

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    AnnouncementsToday: wrap up sequential circuits, start discussing arithmetic circuits

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    A Generic Digital Processor

    MEM ORY

    DATAPATH

    CONTROL

    INPU

    T-O

    UT

    PUT

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Building Blocks for Digital Architectures

    Datapath (Arithmetic Unit)- Bit-sliced datapath (adder , multiplier,

    shifter, comparator, etc.)

    Memory- RAM, ROM, Buffers, Shift registers

    Control- Finite state machine (PLA, random logic.)- Counters

    Interconnect- Switches- Arbiters- Bus

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Bit-Sliced Design

    Bit 3

    Bit 2

    Bit 1

    Bit 0

    Reg

    ister

    Add

    er

    Shift

    er

    Mul

    tiple

    xer

    Control

    Dat

    a-In

    Dat

    a-O

    ut

    Tile identical processing elements

    Bit Slice

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Full Adder

    A B

    Cout

    Sum

    Cin Fulladder

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    The Binary Adder

    S A B Ci⊕ ⊕=

    A= BCi ABCi ABCi ABCi+ + +

    Co AB BCi ACi+ +=

    A B

    Cout

    Sum

    Cin Fulladder

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    The Ripple-Carry Adder

    A0 B0

    S0

    Co,0Ci,0

    A1 B1

    S1

    Co,1

    A2 B2

    S2

    Co,2

    A3 B3

    S3

    Co,3

    (= Ci,1)FA FA FA FA

    Worst case delay linear with the number of bits

    tadder N 1–( )tcarry tsum+≈

    td = O(N)

    Goal: Make the fastest possible carry path circuit

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Complimentary Static CMOS Full Adder

    VDDVDD

    VDD

    VDD

    A B

    Ci

    S

    Co

    X

    B

    A

    Ci A

    BBA

    Ci

    A B Ci

    Ci

    B

    A

    Ci

    A

    B

    BA

    28 Transistors

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    A Closer Look

    Drawbacks» Tall PMOS Stack

    – Slows down circuit» Co load is 2 diffusion and 6

    gate capacitances» Ci goes through the extra

    output inverter to Co– Could optimize with next

    stage» Sum generation has extra

    inverter on output– Not the critical path

    Positive» Ci closest to output node

    VDDVDD

    VDD

    VDD

    A B

    Ci

    S

    Co

    X

    B

    A

    Ci A

    BBA

    Ci

    A B Ci

    Ci

    B

    A

    Ci

    A

    B

    BA

    28 Transistors

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Inversion Property

    A B

    S

    CoCi FA

    A B

    S

    CoCi FA

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Minimize Critical Path by Reducing Inverting Stages

    A0 B0

    S0

    Co,0Ci,0

    A1 B1

    S1

    Co,1

    A2 B2

    S2

    Co,2 Co,3FA’ FA’ FA’ FA’

    A3 B3

    S3

    Odd CellEven Cell

    Exploit Inversion Property

    Note: need 2 different types of cells

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Applying Inversion PropertyVDD

    VDD

    VDD

    VDD

    A B

    Ci

    S

    Co

    X

    B

    A

    Ci A

    BBA

    Ci

    A B Ci

    Ci

    B

    A

    Ci

    A

    B

    BA

    28 Transistors

    Co VDDVDD

    VDD

    VDD

    A B

    Ci

    S

    Co

    X

    B

    A

    Ci A

    BBA

    Ci

    A B Ci

    Ci

    B

    A

    Ci

    A

    B

    BA

    CoTo Ci

    With the next stage, invert A and B. You will get as outputs S and C…so take away inverters on these outputs.

    Invert A and B inputs

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Express Sum and Carry as Function of P, G, D

    Define 3 new variable which ONLY depend on A, BGenerate (G) = ABPropagate (P) = A ⊕ BDelete = A B

    Can also derive expressions for S and Co based on D and P

    C0 = 0 if D = 1

    C0 = 1 if G = 1C0 = Ci if P = 1

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    A Better Structure: the Mirror Adder

    VDD

    CiA

    BBA

    B

    A

    A BKill

    Generate"1"-Propagate

    "0"-Propagate

    VDD

    Ci

    A B Ci

    Ci

    B

    A

    Ci

    A

    BBA

    VDD

    SCo

    24 transistors

    Delete

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    The Mirror Adder I•The NMOS and PMOS chains are completely symmetrical. This guarantees identical rising and falling transitions if the NMOS and PMOS devices are properly sized. A maximum of two series transistors can be observed in the carry-generation circuitry.

    •When laying out the cell, the most critical issue is the minimization of the capacitance at node Co. The reduction of the diffusion capacitances is particularly important.

    •The capacitance at node Co is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell .

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    The Mirror Adder II•The transistors connected to Ci are placed closest to the output.

    • Fastest for late arriving inputs, Ci tends to arrive late•Only the transistors in the carry stage have to be optimized for optimal speed. All transistors in the sum stage can be minimal size.

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Adder Architectures•In addition to optimizing each full adder cell and exploiting inversion property, we can also reorganize the add computation to speed things up

    •Basic idea is to overlap propagating the carry with computing the Propagate and Generate functions

    •Discuss three basic architectures• Carry-Bypass• Carry-Select• Carry-Lookahead

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Carry-Bypass Adder

    FA FA FA FA

    P0 G1 P0 G1 P2 G2 P3 G3

    Co,3Co,2Co,1Co,0Ci,0

    FA FA FA FA

    P0 G1 P0 G1 P2 G2 P3 G3

    Co,2Co,1Co,0Ci,0

    Co,3

    Mul

    tiple

    xer

    BP=PoP1P2P3

    Idea: If (P0 and P1 and P2 and P3 = 1)then Co3 = C0, else “kill” or “generate”.

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Carry-Bypass Adder (cont.)

    Setup

    CarryPropagation

    Sum

    Setup

    CarryPropagation

    Sum

    Setup

    CarryPropagation

    Sum

    Setup

    CarryPropagation

    Sum

    Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15

    Ci,0

    Note that this is done at the expense of a MUX in the carry delay path !!

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Carry Ripple vs. Carry Bypass

    N

    tp

    ripple adder

    bypass adder

    4..8

    Essentially greater than 4 bits is needed to overcome the overhead of the MUX

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Carry-Select Adder

    Setup

    "0" Carry Propagation

    "1" Carry Propagation

    Multiplexer

    Sum Generation

    Co,k-1 Co,k+3

    "0"

    "1"

    P,G

    Carry Vector

    Evaluate possibilities for both Ci = 1 and Ci = 0 and then select when

    Ci comes in.

    Results in about 30%extra transistors

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Carry Select Adder: Critical Path

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15

    S0-3 S4-7 S8-11 S12-15

    Co,15Co,11Co,7Co,3Ci,0

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Linear Carry Select

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15

    S0-3 S4-7 S8-11 S12-15

    Ci,0

    (1)

    (1)

    (5)(6) (7) (8)

    (9)

    (10)

    (5) (5) (5)(5)

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Carry-Select Adder Observations

    The inputs to the final multiplexer are steady long before the Mux select (Ci) arrives» Path is the same as is the number of bits

    Would be helpful to try and even out the delays so that the critical path is balanced between inputs and Muxselect.» Make logic simpler with the least significant bits by

    reducing the number of bits handled in the FA or half adder (HA). HA is FA without Ci (2 ins, 2 outs)

    » Add bits progressively as you move to the MSB

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Square Root Carry Select

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Bit 0-1 Bit 2-4 Bit 5-8 Bit 9-13

    S0-1 S2-4 S5-8 S9-13

    Ci,0

    (4) (5) (6) (7)

    (1)

    (1)

    (3) (4) (5) (6)

    Mux

    Sum

    S14-19

    (7)

    (8)

    Bit 14-19

    (9)

    (3)

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Adder Delays: Comparison

    0.0 20.0 40.0 60.0N

    0.0

    10.0

    20.0

    30.0

    40.0

    50.0

    tp

    ripple adder

    linear select

    square root select

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Carry Look Ahead: Basic Idea

    A0,B0 A1,B1 AN-1,BN-1...

    Ci,0 P0 Ci,1 P1Ci,N-1 PN-1

    ...

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Look-Ahead: TopologyVDD

    P3

    P2

    P1

    P0

    G3

    G2

    G1

    G0

    Ci,0Co,3

    • No more than N = 4 bits• Delay still increases linearly with number of bits

    • Capacitance, resistance too high for N > 4

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Binary Multiplication

    Z X·· Y× Zk2k

    k 0=

    M N 1–+

    ∑= =

    Xi2i

    i 0=

    M 1–

    ∑⎝ ⎠⎜ ⎟⎜ ⎟⎜ ⎟⎛ ⎞

    Yj2j

    j 0=

    N 1–

    ∑⎝ ⎠⎜ ⎟⎜ ⎟⎜ ⎟⎛ ⎞

    =

    XiYj2i j+

    j 0=

    N 1–

    ∑⎝ ⎠⎜ ⎟⎜ ⎟⎜ ⎟⎛ ⎞

    i 0=

    M 1–

    ∑=

    X Xi2i

    i 0=

    M 1–

    ∑=

    Y Yj2j

    j 0=

    N 1–

    ∑=

    with

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Binary Multiplication

    1 0 1 1

    1 0 1 0 1 0

    0 0 0 0 0 0

    1 0 1 0 1 0

    1 0 1 0 1 0

    1 0 1 0 1 0

    ×

    1 1 1 0 0 1 1 1 0

    +

    Partial Products

    AND operation

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    The Array Multiplier

    HA FA FA HA

    FA FA FA HA

    FA FA FA HA

    X0X1X2X3 Y1

    X0X1X2X3 Y2

    X0X1X2X3 Y3

    Z1

    Z2

    Z3Z4Z5Z6

    Z0

    Z7

    X0X1X2X3Y0

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    HA FA FA HA

    HAFAFAFA

    FAFA FA HA

    Critical Path 1

    Critical Path 2

    The MxN Array Multiplier: Critical Path

    Critical Path 1 & 2

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Adder Cells in Array Multiplier

    A

    B

    P

    Ci

    VDD A

    A A

    VDD

    Ci

    A

    P

    AB

    VDD

    VDD

    Ci

    Ci

    Co

    S

    Ci

    P

    P

    P

    P

    P

    Identical Delays for Carry and Sum

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Multiplier Floorplan

    SCSCSCSC

    SCSCSCSC

    SCSCSCSC

    SC

    SC

    SC

    SC

    Z0

    Z1

    Z2

    Z3Z4Z5Z6Z7

    X0X1X2X3

    Y1

    Y2

    Y3

    Y0

    Vector Merging Cell

    HA Multiplier Cell

    FA Multiplier Cell

    X and Y signals are broadcastedthrough the complete array.( )

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Array Multiplier Reflections

    Many equal critical paths» Very hard to optimize by transistor sizing

    We could pass the carry bits diagonally down instead of across» Output does not change» Need to add an extra stage to accommodate this

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Carry Save Multiplier

    HA HA HA HA

    FAFAFAHA

    FAHA FA FA

    FAHA FA HA

    Vector Merging Adder

    Could use carry look ahead structure

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    The Tree MultiplierNote that the partial products layout looks as follows:

    Note that we can rearrange and add the partial products differentlyReduce number of adder circuits and logic depthFA compresses 3b to 2b, HA has 2b in and 2b out

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Tree Multiplier

    Re arranging

    1st StageHalf Adders

    6 5 4 3 2 1 0

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Tree Multiplier

    Re arranging

    1st Stage

    2nd Stage

    6 5 4 3 2 1 0

    6 5 4 3 2 1 0

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Tree Multiplier

    Re arranging

    1st Stage

    2nd Stage Full Adders

    6 5 4 3 2 1 0

    6 5 4 3 2 1 0

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Tree Multiplier

    Re arranging

    1st Stage

    2nd Stage Full Adders 3rd Stage

    6 5 4 3 2 1 0

    6 5 4 3 2 1 0 6 5 4 3 2 1 0

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Tree Multiplier

    Re arranging

    1st Stage

    2nd Stage Full Adders 3rd Stage Half Adders

    6 5 4 3 2 1 0

    6 5 4 3 2 1 0 6 5 4 3 2 1 0

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Wallace-Tree MultiplierPartial X3Y2 X2Y2 X3Y1 X1Y2 X3Y0 X1Y1 X2Y0 X0Y1Products X3Y3 X2Y3 X1Y3 X0Y3 X2Y1 X0Y2 X1Y0 X0Y0

    HA HAFirst Stage

    2nd Stage

    Final Adder

    FA FA FA HA

    Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Multipliers: Summary

    Optimization goals different than Adder» Identify critical path» More system level optimization then

    individual cell optimization

  • Digital Integrated Circuits © Prentice Hall 1995Arithmetic

    Tree Multiplier

    Re arranging

    1st Stage

    2nd Stage 3rd Stage

    6 5 4 3 2 1 0

    6 5 4 3 2 1 0 6 5 4 3 2 1 0

    Arithmetic Building Blocks�Chapter 11 RabaeyAnnouncementsA Generic Digital ProcessorBit-Sliced DesignFull AdderThe Binary AdderThe Ripple-Carry AdderComplimentary Static CMOS Full AdderA Closer LookInversion PropertyMinimize Critical Path by Reducing Inverting StagesApplying Inversion PropertyExpress Sum and Carry as Function of P, G, DA Better Structure: the Mirror AdderThe Mirror Adder IThe Mirror Adder IIAdder ArchitecturesCarry-Bypass AdderCarry-Bypass Adder (cont.)Carry Ripple vs. Carry BypassCarry-Select AdderCarry Select Adder: Critical Path Linear Carry Select Carry-Select Adder ObservationsSquare Root Carry Select Adder Delays: Comparison Carry Look Ahead: Basic Idea Look-Ahead: TopologyBinary MultiplicationBinary MultiplicationThe Array MultiplierThe MxN Array Multiplier: Critical PathAdder Cells in Array MultiplierMultiplier FloorplanArray Multiplier ReflectionsCarry Save MultiplierThe Tree MultiplierTree MultiplierTree MultiplierTree MultiplierTree MultiplierTree MultiplierWallace-Tree MultiplierMultipliers: SummaryTree MultiplierAnnouncements