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Digital Integrated Circuits © Prentice Hall 1995 Arithmetic Arithmetic Building Blocks
50

Arithmetic Building Blocks · Arithmetic Building Blocks. ... Building Blocks for Digital Architectures Arithmetic unit ... Worst case delay linear with the number of bits

Aug 25, 2018

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  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Arithmetic BuildingBlocks

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    A Generic Digital Processor

    MEMORY

    DATAPATH

    CONTROL

    INPU

    T-O

    UT

    PUT

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Building Blocks for Digital Architectures

    Arithmetic unit- Bit-sliced datapath (adder , multiplier,

    shifter, comparator, etc.)

    Memory- RAM, ROM, Buffers, Shift registers

    Control- Finite state machine (PLA, random logic.)- Counters

    Interconnect- Switches- Arbiters- Bus

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Bit-Sliced Design

    Bit 3

    Bit 2

    Bit 1

    Bit 0

    Reg

    iste

    r

    Add

    er

    Shif

    ter

    Mul

    tiple

    xer

    Control

    Dat

    a-In

    Dat

    a-O

    ut

    Tile identical processing elements

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Full-Adder

    A B

    Cout

    Sum

    Cin Fulladder

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    The Binary Adder

    S A B Ci =

    A= BCi ABCi ABCi ABCi+ + +

    Co AB BCi ACi+ +=

    A B

    Cout

    Sum

    Cin Fulladder

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Express Sum and Carry as a function of P, G, D

    Define 3 new variable which ONLY depend on A, B

    Generate (G) = AB

    Propagate (P) = A BDelete = A B

    Can also derive expressions for S and Co based on D and P

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    The Ripple-Carry Adder

    A0 B0

    S0

    Co,0Ci,0

    A1 B1

    S1

    Co,1

    A2 B2

    S2

    Co,2

    A3 B3

    S3

    Co,3

    (= Ci,1)FA FA FA FA

    Worst case delay linear with the number of bits

    tadder N 1( )tcarry tsum+

    td = O(N)

    Goal: Make the fastest possible carry path circuit

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Complimentary Static CMOS Full Adder

    VDDVDD

    VDD

    VDD

    A B

    Ci

    S

    Co

    X

    B

    A

    Ci A

    BBA

    Ci

    A B Ci

    Ci

    B

    A

    Ci

    A

    B

    BA

    28 Transistors

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Inversion Property

    A B

    S

    CoCi FA

    A B

    S

    CoCi FA

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Minimize Critical Path by Reducing Inverting Stages

    A0 B0

    S0

    Co,0Ci,0

    A1 B1

    S1

    Co,1

    A2 B2

    S2

    Co,2 Co,3FA FA FA FA

    A3 B3

    S3

    Odd CellEven Cell

    Exploit Inversion Property

    Note: need 2 different types of cells

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    The better structure: the Mirror Adder

    VDD

    CiA

    BBA

    B

    A

    A BKill

    Generate"1"-Propagate

    "0"-Propagate

    VDD

    Ci

    A B Ci

    Ci

    B

    A

    Ci

    A

    BBA

    VDD

    SCo

    24 transistors

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    The Mirror Adder

    The NMOS and PMOS chains are completely symmetrical. This guaranteesidentical rising and falling transitions if the NMOS and PMOS devices areproperly sized. A maximum of two series transistors can be observed in the carry-generation circuitry.

    When laying out the cell, the most critical issue is the minimization of thecapacitance at node Co. The reduction of the diffusion capacitances is particularlyimportant.

    The capacitance at node Co is composed of four diffusion capacitances, twointernal gate capacitances, and six gate capacitances in the connecting adder cell .

    The transistors connected to Ci are placed closest to the output.

    Only the transistors in the carry stage have to be optimized for optimal speed. Alltransistors in the sum stage can be minimal size.

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Quasi-Clocked AdderVDD

    A

    B

    B

    AP

    VDD

    P

    P

    CiS

    P P

    VDD

    P

    P

    A

    P

    P

    Ci

    B B

    VDD

    CoCi

    Signal Setup Carry Generation Sum Generation

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    NMOS-Only Pass Transistor Logic

    AA

    B B

    CC

    Sum Sum

    ACC

    B

    CoutCout

    B

    AA

    A A

    Transistor count (CPL) : 28

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    NP-CMOS Adder

    VDD

    Ci0

    A0 B0 B0

    A0

    VDD

    B1

    A1

    VDD

    A1 B1

    Ci1

    Ci2

    Ci0

    Ci0

    B0

    A0B0

    S0

    A0

    VDD

    VDD

    VDD

    B1 Ci1

    B1

    A1A1

    VDD

    S1

    Ci1

    Carry Path

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    NP-CMOS Adder

    A0

    B0

    A1B1

    S0

    S1

    Co1

    Ci0

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Manchester Carry Chain

    P0

    Ci,0

    P1

    G0

    P2

    G1

    P3

    G2

    P4

    G3 G4

    VDD

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Sizing Manchester Carry Chain

    R1

    C1

    R2

    C2

    R3

    C3

    R4

    C4

    R5

    C5

    R6

    C6

    Out

    M0 M1 M2 M3 M4MC

    Discharge Transistor

    1 2 3 4 5 6

    tp 0.69 Ci Rjj 1=

    i

    i 1=

    N=

    1 1.5 2.0 2.5 3.0k

    5

    10

    15

    20

    25

    Spe

    ed

    1 1.5 2.0 2.5 3.0k

    0

    100

    200

    300

    400

    Are

    a

    Speed (normalized by 0.69RC) Area (in minimum size devices)

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Carry-Bypass Adder

    FA FA FA FA

    P0 G1 P0 G1 P2 G2 P3 G3

    Co,3Co,2Co,1Co,0Ci,0

    FA FA FA FA

    P0 G1 P0 G1 P2 G2 P3 G3

    Co,2Co,1Co,0Ci,0

    Co,3

    Mul

    tiple

    xer

    BP=PoP1P2P3

    Idea: If (P0 and P1 and P2 and P3 = 1)then Co3 = C0, else kill or generate.

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Manchester-Carry Implementation

    P0Ci,0

    P1

    G0

    P2

    G1

    P3

    G2

    BP

    G3

    BP

    Co,3

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Carry-Bypass Adder (cont.)

    Setup

    CarryPropagation

    Sum

    Setup

    CarryPropagation

    Sum

    Setup

    CarryPropagation

    Sum

    Setup

    CarryPropagation

    Sum

    Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15

    C i,0

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Carry Ripple versus Carry Bypass

    N

    tp

    ripple adder

    bypass adder

    4..8

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Carry-Select Adder

    Setup

    "0" Carry Propagation

    "1" Carry Propagation

    Multiplexer

    Sum Generation

    Co,k-1 Co,k+3

    "0"

    "1"

    P,G

    Carry Vector

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Carry Select Adder: Critical Path

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15

    S0-3 S4-7 S8-11 S12-15

    Co,15Co,11Co,7Co,3Ci,0

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Linear Carry Select

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15

    S0-3 S4-7 S8-11 S12-15

    Ci,0

    (1)

    (1)

    (5)(6) (7) (8)

    (9)

    (10)

    (5) (5) (5)(5)

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Square Root Carry Select

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Bit 0-1 Bit 2-4 Bit 5-8 Bit 9-13

    S0-1 S2-4 S5-8 S9-13

    Ci,0

    (4) (5) (6) (7)

    (1)

    (1)

    (3) (4) (5) (6)

    Mux

    Sum

    S14-19

    (7)

    (8)

    Bit 14-19

    (9)

    (3)

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Adder Delays - Comparison

    0.0 20.0 40.0 60.0N

    0.0

    10.0

    20.0

    30.0

    40.0

    50.0

    tp

    ripple adder

    linear select

    square root select

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    LookAhead - Basic Idea

    A0,B0 A1,B1 AN-1,BN-1...

    Ci,0 P0 Ci,1 P1Ci,N-1 PN-1

    ...

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Look-Ahead: TopologyVDD

    P3

    P2

    P1

    P0

    G3

    G2

    G1

    G0

    Ci,0

    Co,3

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Logarithmic Look-Ahead Adder

    A7

    F

    A6A5A4A3A2A1

    A0

    A0A1

    A2A3

    A4A5

    A6A7

    F

    tp log2(N)

    tp N

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Brent-Kung Adder

    (G0,P0)(G1,P1)

    (G2,P2)

    (G3,P3)

    (G4,P4)(G5,P5)

    (G6,P6)(G7,P7)

    Co,0

    Co,1Co,2

    Co,3

    Co,4

    Co,5

    Co,6

    Co,7

    tadd log2(N)

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    The Binary Multiplication

    Z X Y Zk 2k

    k 0=

    M N 1+

    = =

    Xi2i

    i 0=

    M 1

    Yj2j

    j 0=

    N 1

    =

    XiYj2i j+

    j 0=

    N 1

    i 0=

    M 1

    =

    X Xi2i

    i 0=

    M 1

    =

    Y Yj2j

    j 0=

    N 1

    =

    with

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    The Binary Multiplication

    1 0 1 1

    1 0 1 0 1 0

    0 0 0 0 0 0

    1 0 1 0 1 0

    1 0 1 0 1 0

    1 0 1 0 1 0

    1 1 1 0 0 1 1 1 0

    +

    Partial Products

    AND operation

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    The Array Multiplier

    HA FA FA HA

    FA FA FA HA

    FA FA FA HA

    X0X1X2X3 Y1

    X0X1X2X3 Y2

    X0X1X2X3 Y3

    Z1

    Z2

    Z3Z4Z5Z6

    Z0

    Z7

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    The MxN Array Multiplier Critical Path

    HA FA FA HA

    HAFAFAFA

    FAFA FA HA

    Critical Path 1

    Critical Path 2

    Critical Path 1 & 2

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Carry-Save Multiplier

    HA HA HA HA

    FAFAFAHA

    FAHA FA FA

    FAHA FA HA

    Vector Merging Adder

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Adder Cells in Array Multiplier

    A

    B

    P

    Ci

    VDDA

    A A

    VDD

    C i

    A

    P

    AB

    VDD

    VDD

    C i

    Ci

    Co

    S

    Ci

    P

    P

    P

    P

    P

    Identical Delays for Carry and Sum

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Multiplier Floorplan

    SCSCSCSC

    SCSCSCSC

    SCSCSCSC

    SC

    SC

    SC

    SC

    Z0

    Z1

    Z2

    Z3Z4Z5Z6Z7

    X0X1X2X3

    Y1

    Y2

    Y3

    Y0

    Vector Merging Cell

    HA Multiplier Cell

    FA Multiplier Cell

    X and Y signals are broadcastedthrough the complete array.( )

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Wallace-Tree Multiplier

    FA

    FA

    FA

    FA

    y0 y1 y2

    y3

    y4

    y5

    S

    Ci-1

    Ci-1

    Ci-1

    Ci

    Ci

    Ci

    FA

    y0 y1 y2

    FA

    y3 y4 y5

    FA

    FA

    CC S

    Ci-1

    Ci-1

    Ci-1

    Ci

    Ci

    Ci

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Multipliers Summary

    Optimization Goals Different Vs Binary Adder

    Once Again: Identify Critical Path

    Other possible techniques

    - Data encoding (Booth)- Pipelining

    FIRST GLIMPSE AT SYSTEM LEVEL OPTIMIZATION

    - Logarithmic versus Linear (Wallace Tree Mult)

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    The Binary Shifter

    Ai

    Ai-1

    Bi

    Bi-1

    Right Leftnop

    Bit-Slice i

    ...

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    The Barrel Shifter

    Sh3Sh2Sh1Sh0

    Sh3

    Sh2

    Sh1

    A3

    A2

    A1

    A0

    B3

    B2

    B1

    B0

    : Control Wire

    : Data Wire

    Area Dominated by Wiring

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    4x4 barrel shifter

    BufferSh3S h 2Sh 1Sh0

    A3

    A2

    A 1

    A 0

    Widthbarrel ~ 2 pm M

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Logarithmic ShifterSh1 Sh1 Sh2 Sh2 Sh4 Sh4

    A3

    A2

    A1

    A0

    B1

    B0

    B2

    B3

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    A 3

    A 2

    A 1

    A 0

    Out3

    Out2

    Out1

    Out0

    0-7 bit Logarithmic Shifter

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Design as a Trade-Off

    0 10 20N

    0.0

    20.0

    40.0

    60.0

    80.0

    t p (n

    sec)

    0 10 20N

    0.0

    0.2

    0.4

    Are

    a (m

    m2)

    look-ahead

    select

    bypassmanchester

    mirrorstatic

    manchester

    look-ahead

    select

    static

    mirrorbypass

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Layout Strategies for Bit-Sliced Datapaths

    Well

    ControlWires (M1)

    Well

    Wires (M1)

    GND VDD GND

    GND

    VDD

    GND

    Approach I

    Signal and power lines parallel

    Approach II

    Signal and power lines perpendicular

    Sign

    als W

    ires

    (M2)

    Sign

    als W

    ires

    (M2)

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Layout of Bit-sliced Datapaths

  • Digital Integrated Circuits Prentice Hall 1995Arithmetic

    Layout of Bit-sliced Datapaths(a) Datapath without feedthroughs

    and without pitch matching(area = 4.2 mm2).

    (b) Adding feedthroughs(area = 3.2 mm2)

    (c) Equalizing the cell height reducesthe area to 2.2 mm2.

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