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1 Document No.: Approved Product Specification Module name: C0200QILC-C Issue date: 2007/6/5 Version: 3.0 Note: 1. The information contained herein may be change without prior notice. It is therefore advisable to contact Chi MEI ELCorp before designed your product based on this specification. Customer Approved by Customer Approved by CMEL PD Division ENG Division QA Dept C0200QILC-C
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Approved Product Specification - Farnell element14 ... product specification was first issued C0200QILC-C 3 Document No.: 1. Purpose: This documentation defines general product specification

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Page 1: Approved Product Specification - Farnell element14 ... product specification was first issued C0200QILC-C 3 Document No.: 1. Purpose: This documentation defines general product specification

1

Document No.:

Approved Product Specification

Module name: C0200QILC-C

Issue date: 2007/6/5

Version: 3.0

Note: 1. The information contained herein may be change without prior notice. It is therefore advisable to contact

Chi MEI ELCorp before designed your product based on this specification.

Customer

Approved by Customer

Approved by CMEL PD Division ENG Division QA Dept

C0200QILC-C

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Reversion History

Version Date Page Description

Ver.3.0

2007,6,5

All

Approved product specification was first issued

C0200QILC-C

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Document No.:

1. Purpose:

This documentation defines general product specification for OLED module supplied by

CMEL. The information described in this technical specification is tentative. Please Contact

CMEL’s representative while your product is modified.

2. General Description:

� Driving Mode: Active Matrix.

� Color Mode: Full Color (262K color)

� Driver IC: HX5051, COG Assembly

� Polarizer type: Anti-reflective (3H)

� Interface: MPU i80-system 18-/16-/9-/8-bit bus interface

� Application: Cell phone etc..

3. Mechanical Data:

No. Items Specification Unit

1 Diagonal Size 2.0” Inch

2 Resolution 176 xRGBx220

3 Pixel Pitch 0.06×0.180 mm

4 Display Area 31.68×39.6 mm

5 Outline Area(Glass) 38×49 mm

6 Thickness 1.3(Typ) ; 1.5(Max) mm

7 Weight 6(Max) g

C0200QILC-C

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4. Absolute Maximum ratings:

Item Symbol Unit Value Note

Power supply voltage 1 VCC, IOVCC V -0.3 ~ + 4.6 Note(1),(2)

Power supply voltage 2 VCI - VSSA V -0.3 ~ + 4.6 Note(1),(3)

Power supply voltage 3 VLCD - VSSA V -0.3 ~ + 6.0 Note(1),(4)

Power supply voltage 4 VSSA -VCL V -0.3 ~ + 4.6 Note(1),(5)

Power supply voltage 5 VLCD - VCL V -0.3 ~ + 9.0 Note(1),(6)

Power supply voltage 6 VGH - VSSA V -0.3 ~ + 18.5 Note(1),(7)

Power supply voltage 7 VSSA - VGL V -0.3 ~ + 16.5 Note(1),(8)

Input voltage Vt V -0.3 ~ VCC + 0.3 Note(1)

Operating temperature Topr C -20 ~ + 60

Storage temperature Tstg C -40~ + 85

Notes: (1) VCC, VSSD must be maintained

(2) (High) VCC ≥ VSSD (Low), (High) IOVCC ≥ VSSD (Low).

(3) Make sure (High) VCI ≥ VSSA (Low).

(4) Make sure (High) VLCD ≥ VSSA (Low).

(5) Make sure (High) VSSA ≥VCL (Low)

(6) Make sure (High) VLCD ≥ VCL (Low).

(7) Make sure (High) VGH ≥ VSSA (Low).

(8) Make sure (High) VSSA ≥ VGL (Low).

5. Electrical Characteristic:

5.1 DC Characteristic

ItemItemItemItem SymbolSymbolSymbolSymbol UnitUnitUnitUnit Test Condition Min.Min.Min.Min. Typ. Max. Note

Input high

voltage VIH V

IOVCC=1.65~3.3V,

VCC= 3.1 ~ 3.3V

0.8*

IOVCC - - -

Input low

voltage VIL V

IOVCC=1.65~3.3V,

VCC= 3.1 ~ 3.3V - -

0.18*

IOVCC -

Output high

voltage(1)

( DB0-15 Pins)

VOH1 V IOH = -0.1 mA 0.9*

IOVCC - - -

Output low

voltage

( DB0-15 Pins)

VOL1 V

IOVCC=1.65~3.3V,

VCC= 3.1 ~ 3.3V

IOL = 0.1mA

- - 0.1*

IOVCC -

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I/O leakage

current ILi uA Vin = 0 ~ IOVCC -0.1 0.1

IOVCC =

2.8V

Current

consumption

during normal

operation

( VCC –

VSSD )

IOP uA

IOVCC=3.0V,

VCC=3.1V ,

VGAM1OUT=4.93V

VLCDC=5.5V (VC=3’b001,

0.92*VCI),

fOSC = 236KHz (160line) ,

Ta=25°C,

GRAM data = 0000h,

REV=”1”, SAP=”100”,

ON4-0=”0”, OP4-0=”0”,

MP52-00=”0”,

MN52-00=”0”,

CP12-00=”0” CN12-00=”0

- 80uA

(Vcc)

200uA

(VCC) -

Current

consumption

during standby

mode

( VCC –

VSSD )

IST IOVCC=3.0V,

VCC=3.1V , Ta=25°C -

1

(IOVCC,VCC)

10

(IOVCC,

VCC)

-

Output voltage

deviation - mV - - 5mV - -

Dispersion of

the Average

Output Voltage

V mA - -10mA - 10mV -

5.2 AC Characteristic

5.2.1

80-System Normal Write Mode (HWM = 0) / (IOVCC = 1.65 ~ 3.3V,

VCC=3.1~3.3V)

Item Symbol Unit Min. Typ. Max. Test Condition

Write tCYCW ns 200 - - Figure 5.1 Bus cycle time

Read tCYCR ns 500 - - Figure 5.1

Write low-level pulse width PWLW ns 50 - - Figure 5.1

Read low-level pulse width PWLR ns 200 - - Figure 5.1

Write high-level pulse width PWHW ns 100 - - Figure 5.1

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Read high-level pulse width PWHR ns 200 - - Figure 5.1

Write / Read rise / fall time tWRr , tWRf ns - - 25 Figure 5.1

Write ( RS to NCS, E_NWR ) 10 - - Figure 5.1

Setup time Read ( RS to NCS ,

RW_NRD )

tAS ns 10 - - Figure 5.1

Address hold time tAH ns 5 - Figure 5.1

Write data set up time tDSW ns 60 - Figure 5.1

Write data hold time tH ns 15 - Figure 5.1

Read data delay time tDDR ns - - 200 Figure 5.1

Read data hold time tDHR ns 5 - - Figure 5.1

5.2.2 80-System High-Speed Write Mode (HWM = 1) /(IOVCC = 1.65 ~ 3.3V,

VCC=3.1~3.3V)

Item Symbol Unit Min. Typ. Max. Test Condition

Write tCYCW ns 100 - - Figure 6.1 Bus cycle time

Read tCYCR ns 500 - - Figure 6.1

Write low-level pulse width PWLW ns 40 - - Figure 6.1

Read low-level pulse width PWLR ns 200 - - Figure 6.1

Write high-level pulse width PWHW ns 40 - - Figure 6.1

Read high-level pulse width PWHR ns 200 - - Figure 6.1

Write / Read rise / fall time tWRr , tWRf ns - - 25 Figure 6.1

Write ( RS to NCS, E_NWR ) 10 - - Figure 6.1

Setup time Read ( RS to NCS,

RW_NRD )

tAS ns 10 - - Figure 6.1

Address hold time tAH ns 5 - - Figure 6.1

Write data set up time tDSW ns 60 - - Figure 6.1

Write data hold time tH ns 15 - - Figure 6.1

Read data delay time tDDR ns - - 200 Figure 6.1

Read data hold time tDHR ns 5 - - Figure 6.1

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VIH

VIL

VIH

VIL

VIL

VIL

tAS

VIH

tAH

VIH

PWHW ,PWHR

VIH

PWLW ,PWLR

tCYCW ,tCYCR

tWRr tWRf

VIH

VIL

tDSW

VIH

VIL

tH

Write Data

Read Data

VOL

VOH

tDHR

VOL

VOH

tDDR

RS

NCS

E_NWR

RW_NRD

DB0 ~DB17

DB0 ~DB17

Figure 5. 1 i80-system Bus Timing

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5.2.3 Reset Timing Characteristics (VCC = 3.1 ~ 3.3 V, IOVCC = 1.65 ~ 3.3 V)

Item Symbol Unit Timing diagram Min. Typ. Max.

Reset low-level width tRES ms Figure 5.4 1 - -

Reset rise time trRES µs Figure5.4 - - 10

Figure 5. 4 Reset Timing

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6. Electro-Optical Characteristic:

Items Symbol Min Typ. Max Unit Remark

Operating Luminance L 130 180 230 Cd/m2 (1)(5)

Power Consumption Pon - 180 240 mW 30% pixels

on (1)

Response Time Tres - - 50 uS (2)

CIEx (White) Wx 0.25 0.30 0.35 - (5)

CIEy( White) Wy 0.27 0.32 0.37 - (5)

CIEx (Red) Rx 0.63 0.67 0.71 - (5)

CIEy( Red) Ry 0.29 0.33 0.37 - (5)

CIEx (Green) Gx 0.27 0.31 0.35 - (5)

CIEy( Green) Gy 0.58 0.62 0.66 - (5)

CIEx (Blue) Bx 0.11 0.15 0.19 - (5)

CIEy( Blue) By 0.15 0.19 0.23 - (5)

Viewing Angle VA 160 170 - Degree (3)

Contrast CR 2000:1 10000:1 - - (4)

Operation Lifetime LTop 10000 - - Hrs (1)(6)

Note:

1.Measuring surrounding: dark room

Surrounding temperature: 25oC

a.Driver Voltage: Vdd=3.1V, ARVDD=5.4V, ARVSS=-3.1V

b.Gamma register Setting:

R30 0x7FFF

R31 0x0777

R32 0x0060

R33 0x7FFF

R34 0x0777

R35 0x0060

R36 0x7FFF

R37 0x0777

R38 0x0000

c.Frame Rate: 115Hz (osc resistor=33k)

R04 0x0005

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d: Power voltage setting:

R01 0x4740

R02 0x0303

R03 0x0016

(VGH=6.5V VGL=-4.3 VGAMA1OUT=4.5v)

2.response time test condition

100%

90%

10%

Tr Tf

Time

3.Viewing angle test condition:

4.Contrast Luminance with all pixels white CR = Luminance with all pixels black

5.Optical tester: Topcon SR3

6. Full White with check board at 110Hz frame rate,1/96 duty. Operating Life Time is

defined when the luminance has decayed to less than 50% of the initial measured luminance

before life test.

ψ=270°

Vss(GND)

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7. System Diagram:

220

DB0~17

NCS, E_NWR,NRD, RS

18

176 pixels x RGB

S2 S176S175S1

G1

G220

G2

G219

OLED Pael

4

VGH/VGL

IM3, IM2, IM1

IM0/ID

4

Vci1out

VSSD,

VSSA

VSYNCHSYNCDOTCLKENABLE

4Vci Vcc,

IOVcc

HX5051-AGate Driver

Circuit

Source Driver Circuit

.

..

..

OSC Resister

SystemReset

...

.... ....

Power SupplyCircuit

Gate Drivercontrol signal

C0200QILC-C

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8. Pin Assignment:

PIN Symbol I/O Description Remarks

1 C11B I Connect a 1uF capacitor with C11A

2 C11A I Connect a 1uF capacitor with C11B

3 DDVDH I/O

When internal power generated by Step up circuit1;

The Amplitude of this Pin is about 2 X VCI1OUT.

When Step up circuit is off,

this Pin is as the external power supply Pin.

4 VCI1OUT I/O Connect a capacitor for stabilization

5 VGAM1OUT O A reference voltage for grayscale voltage.

6 VGAMS_R I Adjust internal red color gamma reference voltage

7 VGAMS_G I Adjust internal green color gamma reference voltage

8 VGAMS_B I Adjust internal blue color gamma reference voltage

9 IM3 I IM3=0 IM0=1 8-bit bus interface, i80-system

IM3=1 IM0=1 9-bit bus interface, i80-system

IM3=0 IM0=0 16-bit bus interface, i80-system 10 IM0 I

IM3=1 IM0=0 18-bit bus interface, i80-system

11 NCS I Chip Select Signal

12 NRESET I Reset pin. Must be reset after power is supplied.

13 RS I Register index/command select

14 E_NWR I Serves as a write signal and writes data at the rising edge

15 DB17 I

16 DB16 I

17 DB15 I

18 DB14 I

19 DB13 I

20 DB12 I

21 DB11 I

22 DB10 I

23 DB9 I

24 DB8 I

25 DB7 I

26 DB6 I

27 DB5 I

28 DB4 I

29 DB3 I

Operates liked an 18-bit bi-directional data bus.

18-bits bus I/F: DB17-0

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30 DB2 I

31 DB1 I

32 DB0 I

33 IOVCC I Power supply (2.7~3.3V)

34 OSC1 I/O

35 OSC2 I/O

Connect an external resistor for generating

internal clock by internal R-C oscillation.

Or an external clock signal is supplied through OSC1 with OSC2 open.

36 VDDD I

Internal Logic power supply.

(1). VDC Enable: VCC is Regulated to 1.9V By VDC Circuit

(2). VDC Disable: Logic Power is from this pin. Can be Shorted to VCC

37 VCC I For digital power supply ( 3.1V~3.3V)

38 GND I System ground

39 VCL I An internal power supply = (-1*VCI1OUT)

40 C12A I Connect a 1uF capacitor with C12B

41 C12B I Connect a 1uF capacitor with C12A

42 VGH I/O An internal power supply for the OLED's

common control signals. Adjusted by BT2-0

43 VGL I/O An internal power supply for the OLED's

common control signals. Adjusted by BT2-0

44 C22A I Connect a 1uF capacitor with C22B

45 C22B I Connect a 1uF capacitor with C22A

46 C21A I Connect a 1uF capacitor with C21B

47 C21B I Connect a 1uF capacitor with C21A

48 GND I System ground

49 AR_VDD I Power supply (5 ~ 7V)

50 AR_VSS I Power supply (-2 ~ -8V)

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9. External Dimension:

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10.Reliability Test:

No. Items Specification

1 High Temp. Storage 85°C, 240hrs

2 Low Temp. Storage -40°C, 240hrs

3 High Temp. Operation 60°C, 240hrs

4 Low Temp. Operation -20°C, 240hrs

5 High Temp / Humidity Storage 85°C, 85%RH, 240hrs

6 High Temp / Humidity Operation 60°C, 90%RH, 240hrs

7 Thermal shock

-40°C ~85°C (-40°C /30min; transit

/3min; 85°C /30min; transit /3min)

1cycle: 66min, 100 cycles

8 Peel strength 500g/cm (Speed~ 50mm/min)

9 Vibration

Frequency: 5~50HZ, 0.5G

Scan rate : 1 oct/min

Time : 2 hrs/axis

Test axis : X, Y, Z

10 Drop

Height: 76cm

Sequence : 1 angle、3 edges and 6

faces

Cycles: 1

11 ESD Air discharge model, ±8kV, 10 times

Evaluation Criteria

� No damage to glass or encapsulation

� No drastic change to display

� Pixel / Line defects : no increased

� Luminance: Within +/-50% of initial value

� Uniformity: (Max-Min) / Min <15%

� Current consumption: within +/-50% of initial value

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11.Package:

C0200QILC-C

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