Analog Baseband Blocks for Multistandard Wireless Transmitters

7/25/2019 Analog Baseband Blocks for Multistandard Wireless Transmitters

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UNIVERSIT DEGLI STUDI DI PAVIA

DIPARTIMENTO DI ELETTRONICA

DOTTORATO DI RICERCAIN INGEGNERIA ELETTRONICA, INFORMATICA ED ELETTRICAXVIII CICLO

ANALOGBASEBANDBLOCKSFORMULTISTANDARDWIRELESSTRANSMITTERS

Tutors:Chiar.mo Prof. Piero MalcovatiChiar.mo Prof. Guido Torelli

Co-Tutor:Chiar.mo Prof. Andrea Baschirotto

Coordinatore del Corso di Dottorato:

Chiar.mo Prof. Giuseppe Conciauro

Tesi di Dottoratodi Nicola Ghittori

Anno Accademico 20042005


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Ai miei nonni


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Contents

List of Acronyms 2

1 Introduction 4

1.1 Reconfigurable multistandard terminals . . . . . . . . . . . . . . . . . . . 4

1.2 This thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3 Outline of the thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Multistandard Transmitters for Wireless Applications 9

2.1 Wireless Local Area Networks . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 Orthogonal Frequency Division Multiplexing modulation . . . . . . . . . . 11

2.3 Universal Mobile Telecommunication System . . . . . . . . . . . . . . . . 13

2.4 Spread spectrum signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5 Transmitter architectures for reconfigurable terminals . . . . . . . . . . . . 15

3 Performance Evaluation 18

3.1 Transmitter model and performance evaluation . . . . . . . . . . . . . . . 18

3.2 WLAN digital modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.3 UMTS digital modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . 203.4 Baseband section of the direct conversion transmitter . . . . . . . . . . . . 27

3.5 Block specifications for WLAN 802.11a and UMTS . . . . . . . . . . . . . 27

4 Circuit Design 39

4.1 Choice of the digital-to-analog converter architecture . . . . . . . . . . . . 39

4.2 Pelgrom model of the random mismatch . . . . . . . . . . . . . . . . . . . 44

4.3 Effect of the current sources mismatch on the INL and DNL . . . . . . . . 47

4.4 INL and DNL yield . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.5 Effect of the current sources mismatch on the SNDR . . . . . . . . . . . . 52

4.6 Dimensioning of the unit cell . . . . . . . . . . . . . . . . . . . . . . . . . 54

4.7 Driving circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4.8 DAC-filter interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564.9 Analog reconstruction filter . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.10 Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5 Experimental Results 71

5.1 Layout strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

5.2 Measurement setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

5.3 Static characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.4 Dynamic characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87


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CONTENTS 1

6 High Frequency Baseband Section 896.1 High frequency baseband section . . . . . . . . . . . . . . . . . . . . . . . 89

6.2 Digital interpolator filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

6.3 Design of the 600-MHz digital-to-analog converter . . . . . . . . . . . . . 101

6.4 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

7 Crosstalk Effects in Mixed-Signal CMOS ICs 110

7.1 Fabrication technology issues . . . . . . . . . . . . . . . . . . . . . . . . . 111

7.2 Model of off-chip parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . 111

7.3 Test-chip description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

7.4 Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

7.5 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

7.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

8 Conlusions 128

A Appendix 130

A.1 Crest factor of a signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

A.2 Linearity of a transfer function . . . . . . . . . . . . . . . . . . . . . . . . 130

A.3 INL and DNL definition for a DAC . . . . . . . . . . . . . . . . . . . . . . 132

References 134

Acknowledgements 139


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List of Acronyms

16-QAM 16-quadrature amplitude modulation

64-QAM 64-quadrature amplitude modulation

BER bit error rate

BPSK binary phase-shift keying

CCK complementary code keying

CMFB common-mode feedback

DAC digital-to-analog converter

DBPSK differential binary phase-shift keying

DEM Dynamic element matching

DFT discrete Fourier transform

DNL differential non-linearity

DPCCH dedicated physical control channel

DPDCH dedicated physical data channel

DQPSK differential quadrature phase-shift keying

DR dynamic range

DS-CDMA direct-sequence code division multiple access

DSP digital signal processor

DSSS direct-sequence spread spectrum

EVM error vector magnitude

FDM frequency division multiplexing

FFT fast Fourier transform

FHSS frequency-hopping spread spectrum

FIR finite impulse response

FOM figure of merit

FS full-scale

GSM Global System for Mobile Communications


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3

HD3 third-order harmonic distortion

IC integrated circuit

IDFT inverse discrete Fourier transform

IFFT inverse fast Fourier transform

IIP2 input second-order intercept point

IIP3 input third-order intercept point

IIR infinite impulse response

IMD3 third-order intermodulation distortion

INL integral non-linearity

LINC linear amplification with non-linear components

OFDM Orthogonal Frequency Division Multiplexing

OIP3 output third-order intercept point

OSR oversampling ratio

PA power amplifier

PCB printed circuit board

PLL phase-locked loops

QPSK quadrature phase-shift keying

RF radio-frequency

RX receiver

SF spreading factor

SFDR spurious-free dynamic range

SNDR signal-to-noise-and-distortion ratio

SNR signal-to-noise ratio

THSS time-hopping spread spectrum

TX transmitter

UMTS Universal Mobile Telecommunication System

UNII Universal Networking Information Structure

VCO voltage controlled oscillator

VGA variable gain amplifier

WLAN Wireless Local Area Network

WMAN Wireless Metropolitan Area Network


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Chapter 1

Introduction

1.1 Reconfigurable multistandard terminals

The implementation of fully-integrated multistandard transceivers is nowadays driving the

telecommunication research worldwide, due to the evolution of the protocols and the grow-

ing importance of interoperability requirements among different standards. State-of-the-art

fully-integrated solutions in the scientific literature and on the market do not cover all of

the four most important telecommunication standards, namely Global System for Mobile

Communications (GSM), Universal Mobile Telecommunication System (UMTS), Blue-

tooth, and Wireless Local Area Networks (WLANs). In order to obtain a mobile terminal

offering to the user voice and data services in a seamless way, all the mentioned standards

must be considered together. As a matter of fact, GSM and UMTS are the dominant stan-

dards for voice and mixed voice/data mobile services, while WLANs based on the IEEE

802.11a/b/g protocols are the most important standards for high data rate wireless inter-

net access. Finally, Bluetooth enables short-range wireless connection between portable

devices at low data rates.

The project Enabling technologies for wireless reconfigurable terminals funded in the

framework of the Italian National Project FIRB [13] is a first step toward the above men-

tioned multistandard integrated transceiver. The aim of the project is the implementation of

fully-integrated solutions which support interoperability between different standards in an

efficient way.

An integrated multistandard transceiver competitive with discrete solutions based on

the combination of separate devices for the different standards needs a consistent reduction

in the silicon area and the power consumption. The maximum possible hardware sharing

among the transceivers for the different standards is therefore of crucial importance. If a

transceiver chain is reconfigurable between two different standards, they can not be em-

ployed together at the same time. Therefore, it is necessary to define which standards must

operate simultaneously. In the framework of the FIRB project, it is assumed that only twostandards among the supported ones can operate concurrently at a given time (e.g WLAN

with Bluetooth or GSM/UMTS with Bluetooth or GSM/UMTS with WLAN) and that no

handover is supported for Bluetooth.

In view of these consideration, the receiver and transmitter architectures, shown in Fig-

ure 1.1 and Figure 1.2 respectively, are proposed. These architectures reflect the following

basic ideas:

two parallel receiver (RX) chains based on the direct conversion architecture are imple-mented, one supporting all cellular standards (GSM/UMTS) and Bluetooth, while the

other supporting all WLAN standards and Bluetooth;


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Introduction 5

Phone BPFilter

LNAI/Q

DemodulatorVGALow-pass

FilterVGAADC

WLAN BPFilter

LNAI/Q

DemodulatorLow-pass

FilterVGAADC

Digitalprocessor

Antenna

Antenna

System on Chip RX

WLAN/Bluetooth RX

GSM/UMTS/Bluetooth RX

RF Analog Baseband Digital Baseband

Figure 1.1: Block diagram of the receiver architectures for GSM/

UMTS/

Bluetooth andWLAN/Bluetooth.

Digital Baseband WLANModulator DAC

Low-passFilter

I/QModulator

Digital Baseband PhoneModulator (LINC)

ModulatorPLL

LINCCombiner Balun

Differentialantenna

System on Chip TX

GSM/UMTS/Bluetooth TX

WLAN/Bluetooth TX

Antenna

PPA PA

PPA PA

PA

RF Analog Baseband Digital Baseband

Figure 1.2: Block diagram of the transmitter architectures for GSM/UMTS/Bluetooth and

WLAN/Bluetooth.

two parallel transmitter (TX) chains are implemented, one based on direct modulation forGSM, Bluetooth and, eventually, UMTS, while the other, based on the direct conversion

architecture, for all WLAN standards and Bluetooth;

the RX and TX chains covering the cellular standards can reconfigure themselves in ashort time (less than 200 s), thus allowing vertical handover between GSM and UMTS,

which do not need to operate concurrently;

vertical handover between cellular and WLAN standards, which can operate concur-rently, is based on the use of two different transceivers.

In particular, several different chips, which represent a preliminary step toward the fi-

nal device, are presently under fabrication: receiver and transmitter for GSM, UMTS, and

Bluetooth; receiver and transmitter for WLAN at 2.4 GHz and 5 GHz and Bluetooth, as

well as the digital processor for all standards. Moreover several basic building blocks of the

presented transceivers have been integrated and characterized in the framework of the FIRB

activity.


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6 Chapter 1

1.2 This thesis

The research activity reported in this thesis, carried out together with Andrea Vigna at the

Integrated Microsystem Laboratory of University of Pavia [4], in collaboration with the

Department of Innovation Engineering of University of Lecce [5], has been focused on

the realization of several baseband sections for reconfigurable transmitters using a direct

conversion architecture. In particular four different test-chips have been integrated:

Device #1: baseband section for the WLAN/UMTS standards consisting of digital-to-analog converter (DAC), output transimpedance stage and reconstruction filter, with a

total power consumption of 20 mW for WLAN and 16.8 mW for UMTS;

Device #2: baseband section for the WLAN/UMTS standards consisting of DAC, passiveoutput stage and reconstruction filter, which achieves the same performance of device #1,

but with a reduction in the power consumption, which is equal to 11 mW for WLAN and8.4 mW for UMTS;

Device #3: baseband section for the WLAN/Bluetooth standards consisting of DAC,passive output stage and reconstruction filter, with a power consumption of 8 mW for

WLAN and 5.4 mW for Bluetooth;

Device #4: high-frequency baseband section for the WLAN standard, which avoids theuse of an active reconstruction filter achieving a power consumption of 2.4 mW.

The experimental results obtained from the test-chip measurements show that all the devices

fulfill the specifications imposed by the different standards, even with the low 1.2-V supply

voltage adopted for the design. In particular the device #3 has been integrated together with

the radio-frequency (RF) section to implement the TX chain of Figure 1.2 for WLAN and

Bluetooth standards. The idea of reconfigurability for a multistandard terminal, the use of

a challenging supply voltage as low as 1.2 V and the low power consumption achieved for

all the implemented devices represent the main aspects of interest related to this research

activity. In this thesis the attention is focused on the couple of devices #2 and #4, which

present innovative solutions both at the architectural and at the design level.

The low power consumption has always been one of the key issue in the design of analog

and digital blocks for mobile applications. A proper choice of the architecture of the entire

system allows an optimization of this parameter. Moreover, the power consumption could

be strongly limited with a progressive reduction of the supply voltages used in wireless

applications, justified also by the diffusion of ultra-scaled-down technologies. However,

the low voltage trend implies also some drawbacks in the design of the analog blocks of

wireless systems, mainly because a low supply voltage strongly limits the output dynamic

range as well as the achievable linearity performance of such blocks. This makes difficult

the implementation of low voltage transceivers, since these devices usually require high

linearity performance and large output swing. As a matter of fact, considering the state-of-the-art literature [6], the use of a supply voltage such as 1.2 V or lower is actually unusual

in the realization of wireless transceivers, and the implementation of high-linearity analog

blocks when a low supply voltage is used can still be considered a challenge for designers.

Considering this scenario, the first part of this thesis presents a reconfigurable base-

band analog block realized by the cascade of a DAC and a reconstruction filter (device #2),

capable of operating in a multistandard wireless transmitter. The implemented block can

be digitally programmed to satisfy the specifications of WLAN IEEE 802.11a/b/g (with a

maximum baseband signal bandwidth of 10 MHz) and UMTS (with a maximum baseband

signal bandwidth of 2.34 MHz). The complete device is fabricated in a standard 0.13-m


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Introduction 7

CMOS technology and operates with a 1.2-V supply voltage. The choice of this low supplyvoltage, in conjunction with the co-design of the two functional blocks, allows a signifi-

cant power reduction as required for mobile applications, while fulfilling the resolution and

linearity targets.

The second part of the thesis presents a high-frequency solution suitable for a direct

conversion WLAN transmitter (device #4). The use of a DAC conversion frequency as high

as 600 MHz allows us to avoid the use of an active reconstruction filter, with a significant

reduction in power consumption. The device realizes the baseband digital-to-analog conver-

sion of WLAN signals with the highest efficiency if compared with state-of-the-art DACs,

as revealed by the highest value of figure of merit achieved for signals up to 10 MHz (the

band of WLAN 802.11a/b/g) and 14 MHz (the band of the upcoming WLAN 802.16).

The last part of the thesis deals with the study of crosstalk effects in mixed-signal inte-

grated circuits (ICs). This is a research activity carried out in the framework of the FIRB

project which aims at studying the injection of noise by the digital switching sections and its

propagation toward the analog parts. The final goal is to develop models for computer simu-

lation of the relevant effects, and to develop adequate guidelines for design and layout, with

the purpose of minimizing these effects. These aspects are of primary concern especially

when dealing with fully-integrated transceivers for wireless applications. In particular some

of the design and layout choices regarding the baseband sections described in this thesis

were done on the basis of the results obtained by this analysis.

1.3 Outline of the thesis

This thesis is organized as follows:

in Chapter 2 a brief description of the considered standards (WLAN and UMTS) is given,focusing in particular on the characteristics of the orthogonal frequency division multi-plexing modulation and of the spread spectrum techniques. An overview of direct con-

version transmitters for wireless applications is then presented.

in Chapter 3 the features of the Matlab model of the WLAN 802.11a/UMTS direct con-version transmitter is presented. The developed time-domain model allowed us to obtain

the specifications of the basic building blocks for device #2 and #4. In particular the

chapter presents the results regarding device #2, indicating the DAC input number of

bits, its conversion frequency and the type of the filter transfer function.

in Chapter 4 the design of device #2 is presented, describing the digital-to-analog con-verter, as well as the features of the interface between the DAC and the following re-

construction filter. Simulation results of the entire baseband section implemented at a

fully-transistor level are presented.

in Chapter 5 the experimental results regarding device #2 are presented, including staticand dynamic tests. Comparisons between the target specifications and measured perfor-

mance are given.

Chapter 6 deals with the high-frequency baseband section implemented in device #4.The required performance obtained with the Matlab model are first indicated. The design

of the 600-MHz block is described in detail and the obtained experimental results are

reported.

Chapter 7 describes the study performed on the crosstalk effects in mixed-signal ICs. Theexperimental results of two test-chips implemented for the validation of crosstalk models

are described.


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8 Chapter 1

in Chapter 8 the conclusions and the future developments of the activity are given.


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Chapter 2

Multistandard Transmitters for

Wireless Applications

This chapter presents the main characteristics of the two standards considered for the imple-

mentation of the baseband sections described in this thesis. The existing WLAN protocols

(802.11a/b/g) as well as the upcoming ones (802.11n and 802.16) are described in Sec-

tion 2.1, while the features of the Orthogonal Frequency Division Multiplexing (OFDM)

techniques, on which the WLAN 802.11a standard is based, are presented in Section 2.2.

The UMTS standard is presented in Section 2.3, while Section 2.4 is dedicated to the de-

scription of the spread spectrum techniques, used in the UMTS standard. Finally in Sec-

tion 2.5 the direct conversion architecture, chosen for the implementation of the reconfig-

urable transmitter, is briefly reviewed.

2.1 Wireless Local Area Networks

The purpose of the IEEE 802.11 standard [7], formalized in 1999, was to allow high data

rate wireless network connectivity between personal computers or workstations. The stan-

dard then evolved allowing the use of WLAN as high-speed internet access. The origi-

nal 802.11 standard provides a maximum data rate of 2 Mbps and uses frequency-hopping

spread spectrum (FHSS) or direct-sequence spread spectrum (DSSS) techniques to modu-

late the signal in the 2.4 GHz band. The growing demand of higher communication speed

led to the development of new standards, namely the 802.11a, 802.11b and 802.11g. More-

over the formalization of a next generation WLAN standard (802.16) has been performed

in the past years, while discussion of an upcoming 802.11n standard is still going on.

The IEEE 802.11a standard [8] achieves a high data rate (up to 54 Mbps) in the 5.4 GHzband. In particular the frequency range allocated in the United States is called Universal

Networking Information Structure (UNII) band and it is composed of three parts: theUNII-1 and UNII-2 (from 5.1 GHz to 5.35 GHz) are intended for indoor and outdoor

use, while the UNII-3 (from 5.725 GHz to 5.85 GHz) is for outdoor use exclusively.

Within each UNII band four non-overlapping WLAN radio channels with a bandwidth

of 20 MHz each are included. The data rate can vary from 6 Mbps to 54 Mbps. Each

channel uses the OFDM modulation and it is composed of 48 orthogonal subcarriers and

4 pilot tones used for the synchronization. Each subcarrier can be modulated by binary

phase-shift keying (BPSK), quadrature phase-shift keying (QPSK), 16-quadrature ampli-

tude modulation (16-QAM) or 64-quadrature amplitude modulation (64-QAM). The data

rates achievable with the different modulation schemes for the subcarriers are summa-


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10 Chapter 2

rized in Table 2.1. In Europe the WLAN standard in the 5 GHz band has been formalizedby the ETSI. The proposed standard, called HiperLAN2 [9], is similar to the 802.11a for

the use of the OFDM modulation and the achievable data rate of 54 Mbps. The major

difference is the allocated spectrum, which is from 5.15 GHz to 5.35 GHz for indoor use

and from 5.47 GHz to 5.725 GHz for outdoor applications.

Table 2.1: Achievable data rate for the IEEE 802.11a standard depending on the used modulation

scheme.

Data rate (Mbps) Modulation Coding rate (R)

6 BPSK 1/2

9 BPSK 3/4

12 QPSK 1/2

18 QPSK 3/4

24 16-QAM 1/2

36 16-QAM 3/4

48 64-QAM 2/3

54 64-QAM 3/4

The IEEE 802.11b standard [10] specifies two radio transmission solutions for wire-less communication in the band from 2.4 GHz to 2.4835 GHz, with a maximum data

rate of 2 Mbps. The first uses the FHSS technique, while the second uses DSSS tech-

nique. In the case of the DSSS solution, the radio channel of 14 MHz is modulated

with a diff

erential binary phase-shift keying (DBPSK) or diff

erential quadrature phase-shift keying (DQPSK) to provide a data rate of 1 Mbps and 2 Mbps respectively. This

solution was enhanced to a data rate of 11 Mbps with the use of complementary code

keying (CCK).

The IEEE 802.11g standard [11] improves the data rate in the 2.4 GHz band up to a valueof 54 Mbps and at the same time it is backward compatible with 802.11b. To do this, the

standard uses the same modulation techniques to achieve compatibility and data rate of

the 802.11b standard, while allowing also the OFDM modulation to obtain the 802.11a

data throughputs.

The IEEE 802.11n standard is an amendment to the original 802.11 standard started inJanuary 2004 and intended for local area wireless networks. The real data throughput

is estimated to reach a theoretical value of 540 Mbps (which may require an even larger

raw data rate at the physical layer) and should be up to 10 times faster than the 802.11a/g

and near 40 times faster than the 802.11b. The 802.11n is build upon previous 802.11standards by adding to the OFDM the use of multiple transmitter and receiver antennas

(multiple-input multiple-output antennas or MIMO) to allow for increased data through-

put through spatial multiplexing. The standardization process is expected to be completed

by April 2007.

The IEEE 802.16 standard [12], completed in October 2001, defines the air interfacespecifications for the Wireless Metropolitan Area Networks (WMANs). As currently de-

fined by the standard, a WMAN provides network access to buildings through exterior

antennas communicating with central radio base stations (BS). Therefore the WMAN

offers an alternative to cabled access networks, such as fiber optic links or digital sub-


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Multistandard Transmitters for Wireless Applications 11

f

singlesubcarrier

guardband

bandwidth saving

conventional FDM multicarrier modulation technique

OFDM multicarrier modulation technique

f

Figure 2.1: Conventional FDM subcarriers frequency allocation vs OFDM subcarriers fre-

quency allocation.

scriber line (DSL) links. IEEE 802.16 provides up to 50 km (31 miles) of linear service

area range and allows connectivity without a direct line of sight to the base station. The

user inside the building will connect to WMAN with conventional in-building networks,

such for example Ethernet or 802.11 Wireless LANs. Two ranges of frequencies are al-located to the 802.16 standard. The first one is from 10 GHz to 66 GHz, using a single

carrier modulation and a time division multiple access protocol (TDMA). On the other

hand, the band from 2 GHz to 11 GHz is addressed from the 802.16a standard and it

is driven by non-line-of-sight operation. The channel spacing ranges from 20 MHz to

28 MHz and the maximum data throughput is 134 Mbps.

2.2 Orthogonal Frequency Division Multiplexing modula-

tion

The principles of OFDM modulation are employed in data delivery systems over the phone

line (as in asynchronous digital subscriber line, ADSL), digital radio, television (like in ter-restrial digital video broadcast, DVB-T), and in wireless networking systems. The OFDM

techniques use a set of subcarriers that are orthogonal to each other, reaching a higher level

of spectral efficiency with respect to simple frequency division multiplexing (FDM) tech-

niques. As a matter of fact, the guard bands that are necessary to allow the individual

demodulation of the subcarriers in an FDM system are no longer used. In the case of the

OFDM systems the spectra of the subcarriers overlap one with each other, but as long as

their orthogonality is ensured, it is possible to recover the individual subcarrier signals.

Let us consider a group ofNcomplex symbols (Nis equal to 64 in the WLAN 802.11a

case), indicated asdn(with integern =N/2, ...,N/2 andn 0), taken from a constellation


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12 Chapter 2

of complex numbers (for example one of the PSK or QAM constellations used in the WLANmodulation scheme):

dn =an+ jbn. (2.1)

The complex symbols are used to modulate a set ofNorthogonal functions in a time interval

t [0, T]. The chosen orthogonal functions fn(t) correspond to sinusoids in the complexplane, as they are rotating points on the unit circle, describing an integer number of cycles

in the time interval [0, T]:

fn(t) = ej2n f0t, (2.2)

where f0 = 1/T. Note that as we are considering complex signals, the frequency can be

positive or negative, corresponding to clockwise or counterclockwise rotation. The chosen

set of functions are orthogonal as:

T

0

ej2n f0tej2m f0tdt= T, if m=n; (2.3)

T0

ej2n f0tej2m f0tdt= 0, ifm n. (2.4)

Considering the symboldn, the corresponding modulated function is:

yn(t)= dnej2n f0t =|dn| ej2n f0t+(dn), (2.5)

while the overall modulated signal can be written as:

s(t) =

N/2

n=N/2

yn(t)=

N/2

n=N/2

dnej2n f0t. (2.6)

The spectrum of the single modulated function yn(t) is a sinc function located around the

subcarrier frequencyn f0 and it is equal to zero in correspondence of the peaks of the other

subcarriers, so realizing the orthogonality (Figure 2.1). The value of the spectrum ofyn(t)

calculated in n f0 is therefore not influenced by the adjacent subcarriers and it allows the

value of the modulating complex symbol dn to be recovered. The overall spectrum of the

complex signal consists ofNsubcarriers spaced apart of f0. In the WLAN 802.11a case

f0 is equal to 0.3125 MHz and the spectrum of the complex baseband modulated signal is

included between10 MHz and 10 MHz.An OFDM system treats the source symbols dn(e.g., the PSK or QAM symbols) at the

transmitter as if they are in the frequency domain. These symbols are used as the inputs

to a modulator block that brings the signal into the time domain. This block takes in N

symbols at a time, where Nis the number of subcarriers in the system. Each input symbolacts like a complex weight for the corresponding sinusoidal basis function. Since the input

symbols are complex, the value of the symbol determines both the amplitude and phase of

the complex sinusoid for that subcarrier. The output of the block is the summation of all the

Ncomplex sinusoids.

The idea behind the analog implementation of the OFDM system can be extended to

the digital domain by using the discrete Fourier transform (DFT) and its counterpart, the

inverse discrete Fourier transform (IDFT). These mathematical operations are widely used

for transforming data between the time domain and the frequency domain. In practice,

OFDM systems are implemented using a combination of fast Fourier transform (FFT) and


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inverse fast Fourier transform (IFFT) blocks that are mathematically equivalent versions ofthe DFT and IDFT, respectively, but more efficient to implement.

If we consider the sampled version of the overall modulated function s(t):

s

t=

kT

N

=

N/2n=N/2

dnej2nk/N, (2.7)

with kgoing from 0 to N1, we can pass from the set ofNcomplex symbols dn to theNcomplex samples of the modulated signal using an IFFT block. Thus, the IFFT block

provides a simple way to modulate data onto Northogonal subcarriers. The block of N

output samples from the IFFT make up a single OFDM symbol. The length of the OFDM

symbol isT. After some additional processing, the time-domain signal that results from the

IFFT is split into a real and imaginary part and it is transmitted across the channel. At the

receiver, an FFT block is used to process the received signal and bring it into the frequencydomain. Ideally, the FFT output will be the original symbols that were sent to the IFFT at

the transmitter. When plotted in the complex plane, the FFT output samples will form the

original transmitted constellation.

2.3 Universal Mobile Telecommunication System

The third generation (3G) of global wireless systems provides voice and information ser-

vices with different data rates using the wide-band code-division multiple access (WCDMA)

protocol. The European version of the third generation telecommunication system, called

UMTS [13], can achieve a data rate of 384 Kbps for outdoor applications and of 2 Mbps for

indoor applications. The bit-stream carrying the user information is modulated by a pseudo-

random sequence (indicated as spreading code). Through the spreading process the signalbandwidth (ranging from 8 kHz to 384 kHz) is increased to the bandwidth of the spreading

code (3.84 MHz). At the receiver the despreading process uses the same code applied in the

transmitter to recover the original spectrum of the data signal, whose power spectral density

increases by an amount given by the spreading factor (SF). The spreading factor is defined

as the ratio between the rate of the spreading code and the one of the original signal.

The UMTS mobile terminal is a continuously transmitting and receiving frequency di-

vision duplexing (FDD) system. The transmission band is located between 1920 MHz and

1980 MHz, while the receiver band is located between 2110 MHz and 2170 MHz. The

minimum spacing between the TX and RX band is therefore 135 MHz, while the channel

spacing is 5 MHz.

2.4 Spread spectrum signals

The UMTS standard uses a coding process of the signal implying a modification of its

spectrum, which results to be spread in a wider bandwidth with respect with to the original

one. For this reason the resulting transmitted signal is called spread spectrum signal and

the protocol used is called spread spectrum multiple access protocol (SSMA). A spread

spectrum system must meet two criteria: the transmitted bandwidth is much wider than

the bandwidth of the information being sent; the spreading signal is independent of the

information bearing signal. According to the process which realizes the spreading of the

signal, the spread spectrum systems can be classified into three main groups:


18/143

14 Chapter 2

tCode

f x f

Bit rate chip rate

TX spreading

tCode

fx

Bit rate

RX despreading SF

Figure 2.2: Spreading and despreading process.

direct-sequence spread spectrum, in which the spreading is done by a multiplication ofthe data carrying signal with a code sequence of much larger bandwidth;

frequency-hopping spread spectrum, in which the spreading is accomplished by periodi-cally changing the carrier frequency according to a spreading code;

time-hopping spread spectrum (THSS), in which the signal is not transmitted in a con-tinuous way, but it is fragmented in bursts whose temporal position is decided by the

spreading code.

Another technique which implies a spreading of the signal spectrum is the chirp modulation,

usually reserved for military applications. In this technique the carrier frequency of the

transmitted signal varies continuously (usually linearly) over a wide frequency range. As

there is not a code univocally identifying each user, the chirp modulation is not a CDMA

technique, even if it is a spread spectrum technique as there is a spreading of the information

signal in a larger bandwidth.

The third generation systems, like UMTS, use the direct-sequence code division multi-

ple access (DS-CDMA), which is the one that offers the best advantages. In the DS-CDMA

technique the signal carrying the information is directly modulated by the code. The spread-

ing sequence (called also chip sequence) is associated to each user and it is orthogonal to

the spreading sequences of the other users. A representation of the coding process is shown

in Figure 2.2 in which the data signal is multiplied by a high frequency pseudo random

code. At the receiver the despreading of the signal is performed by the demodulator which

multiplies the signal by the same code used in the transmission modulator. In this way the

signal is restored in its original form.

The DS-CDMA, like the other spread spectrum techniques, has an inherent resistance

against interference and jamming. Suppose that a narrow-band interferer is present in thereceived signal, as indicated in Figure 2.3. Due to the high correlation between the wanted

signal (which was spread in the transmitter by the same sequence) and the locally generated

code for despreading, the signal level increases. At the same time the interference signal is

spread to a larger bandwidth and therefore the interference power in the receiver bandwidth

decreases.

The main advantage of the DS-CDMA is the high simplicity of the spreading process,

which results to be just a multiplication of the data signal with the spreading code. On the

other hand a crucial point is represented by the synchronization of the received signal and

the locally generated code for the despreading. Therefore obtaining initial synchronization


19/143


and keeping the code synchronized by a code tracking loop is mandatory in DS-CDMAsystem design.

2.5 Transmitter architectures for reconfigurable terminals

Transmitters performs three basic functions in a digital communication system: modulation,

frequency translation and amplification of the signal. Therefore the main parameters of

interest when dealing with a transmitter are modulation accuracy, spectral emission and

output power level. Among the others, two different transmitter architectures are interesting

for the possibility of a complete integration and reconfigurability between several standards:

direct conversion architecture and phase-locked loops (PLL) based architecture.

The direct conversion architecture, called also zero intermediate frequency (zero-IF),

performs the frequency translation of the transmitted signal in one step (Figure 2.4). Two

digital-to-analog converters convert the I and Q digital modulated signals coming from the

digital signal processor (DSP) into analog waveforms, which are smoothed by the following

low-pass reconstruction filters and amplified by means of a variable gain amplifier (VGA).

These baseband signals are then shifted to RF by two quadrature mixers, and summed up to

obtain the final waveform to be transmitted at the antenna, after the amplification provided

by the power amplifier (PA).

Since no intermediate frequency exists with respect to the RF final center frequency of

the signal, there is no need of an IF filter. For this reason, the direct conversion architecture is

the most interesting when dealing with highly-integrated multistandard solutions. A filtering

stage before the PA reduces the unwanted harmonics and noise from the up-conversion

process. However, if the bandpass filter before the PA is removed to achieve a high level ofintegration, a higher performance RF filter may be required after the PA. This requirement

in turns implies a larger insertion loss through the RF filter, thus reducing the efficiency of

the PA due to the reduction of the output power at the antenna for a given signal level at the

PA input. This signal level must therefore be increased, with a consequent increase in the

+ f

chip rate

tCode

fx

Bit rate

RX despreadingf

chip rate

interferer

interferer spread interferer

f

Figure 2.3: An interfering signal is spread by a code sequence resulting in a lower power

spectral density, while the wanted signal level is increased due to the high correlation of the

spreading code and the signal.


20/143

16 Chapter 2

I

Q

90

LO

+

RF S AW

VGA

VGA

PA

DAC

DAC

RF FILTE R

Figure 2.4: Model of the direct conversion transmitter.

arccos d/dt

20 bits

20 bits

d((t)-(t))/dt

d((t)+(t))/dt

+

+

f0

20 bits

f0

20 bits

LPFPD

N

LPFPD

N

quartz

PLL

PLL

PA

PA

+

S1(t)

S2(t)

20 bits

20 bits

3 bits

3 bits

RFsignal3 bitsfromDSP

Figure 2.5: Model of the direct modulation transmitter.

power consumption. The level of RF filtering is a compromise between power consumption

an achievable integration.

On the other hand, another drawback of a direct conversion architecture is represented

by the local oscillator (LO) pulling. The output of the I/Q modulator, of the power amplifier

and of the local oscillator run at the same frequency, which is the standard RF frequency. As

a consequence, the output of the local oscillator may be pulled by the large signal emitted

by the PA, so resulting in a modulation of the input mixer frequency. The solution is to

keep a high level of isolation between the PA and the voltage controlled oscillator (VCO),

which is however difficult to implement in a fully-integrated solution. Otherwise different

schemes, using two VCOs functioning at different frequencies with respect to the RF one,

can be used to overcome this problem.

Another architecture which has the advantage of reducing the requirements of the RF fil-

tering is the PLL based transmitter architecture (called also direct modulation architecture).

This transmitter can be combined with a digital section based on linear amplification with

non-linear components (LINC), as shown in Figure 2.5. The main processing of the signal

is performed in the digital domain, while the analog section is limited to some parts of thePLL and the power amplification stage. The input of the digital section consists of the mod-

ulated signal carrying the user information. Such a signal (that is generally modulated both

in phase and in amplitude) feeds a DSP section whose outputs are the instantaneous phases

of the two wideband (and constant envelope) LINC signal S1(t) and S2(t). Such informa-

tion, quantized in 2 words of 20 bits each, is then digitally processed and used to modulate

the carrier of two wideband PLLs, through their modulator. The two PLL outputs are

the constant envelope RF LINC signals S1(t) andS2(t) that may then be amplified through

the final power amplifiers. Their outputs are then on-chip recombined and transmitted to the

antenna.


21/143


In the framework of the FIRB project a direct conversion architecture has been chosenfor the WLAN/Bluetooth reconfigurable transmitter, while the direct modulation architec-

ture has been chosen for the GMS/UMTS/Bluetooth reconfigurable transmitter. On the other

hand, all the devices developed in our research activity are intended for direct conversion

architectures (no matter which standards are supported), and therefore they consist of the

cascade of a DAC and a filtering stage (which is active for device #1, #2, #3 and passive for

device #4).


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Chapter 3

Performance Evaluation

In this chapter the features of the Matlab model of the WLAN 802.11a/UMTS direct con-

version transmitter are presented. The developed time-domain model allowed us to obtain

the specifications of the basic building blocks for the devices presented in this thesis. Sec-

tion 3.1 describes the overall model and indicates the tests that have to be performed on the

transmitted signal to verify the compliance to the standard specifications. Sections 3.2 and

3.3 describe the simplified models for the WLAN 802.11a and UMTS digital modulators,

while Section 3.4 deals with the developed models for the analog baseband blocks. Finally

Section 3.5 presents the required performance for the baseband analog section implemented

in device #2. Even if the part of the model regarding the WLAN is limited to the 802.11a

standard, an overall system-level study developed in the framework of the FIRB activity

confirms the obtained specifications also for 802.11b and 802.11g standards.

3.1 Transmitter model and performance evaluation

A model of the direct conversion transmitter has been developed in the Matlab environment.

A time-domain model has been preferred to a frequency-domain one as it allows a more ac-

curate description of the non-idealities of the blocks, at the expense of more computational

time. Moreover a time-domain model allows to deal directly with the real signals that flow

through the blocks of the system, and hence to evaluate the parameters of interest, like the

signal-to-noise ratio (SNR).

The model consists of two parts. The first one describes a simplified version of the dig-

ital modulator for the WLAN 802.11a and UMTS standards. The second part includes the

models of the building blocks used in the analog baseband section of the direct conversion

transmitter. The DAC and the following reconstruction filter have been modeled taking into

account the most important design parameters and the main non-idealities.

As indicated by the standards, the quality of the transmitted signal is specified eval-

uating the error vector magnitude (EVM) at the antenna. An ideal receiver performs thedemodulation of the transmitted signal, obtaining a constellation of points in the complex

plane representing the received symbols. Each point of the constellation (indicated as Z) is

compared with the ideal one R (i.e. the one coming from an ideal transmitter), as shown in

Figure 3.1. The EVM (expressed as a percentage) can be calculated as follows:

EVM=

N1|ZR|2N

1|R|2 100%, (3.1)

where N is the number of received symbols. Considering for example the case of UMTS,

the EVM has to be less than 17.5% to ensure the achievement of the necessary bit error


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Performance Evaluation 19

I

Q R (ideal constellation point)

range of realconstellation points

Z (real constellation point)

Figure 3.1: Constellation points coming from an ideal transmitter and a real one.

rate (BER) at the receiver. The EVM can also be related to the signal-to-noise-and-distortion

ratio (SNDR) of the signal at the antenna, noting that it can be expressed as:

EVM=

Perror

Preference100%, (3.2)

where Preference is the mean power of the reference signal (i.e. the output of an ideal chain

in which the various blocks do not introduce distortion and noise) and Perror is the mean

power of the error signal (i.e. the difference between the reference signal and the real signal

processed by the transmitter chain). An EVM value of 17.5% implies an SNDR of 15 dB.

Table 3.1 summarizes the required EVM at the antenna for the two different standards.

The evaluation of the error signal as a difference between the signal processed by the real

transmitter and the one processed by an ideal transmitter accounts for all the sources of noise

and distortion. The noise can be quantization noise or thermal one, while the distortion is

caused by the non-linearity of the blocks or by the non-constant transfer function amplitude

in the band of the signal. In the model the distortion caused by the non-linear phase response

of the blocks is not taken into account. As a matter of fact, the phase component of the

blocks transfer function is always equal to zero and therefore the blocks do not introduce

delays.

The transmitter chain performance is evaluated not only with WLAN or UMTS appli-

cation signals but also with sinusoidal inputs. This gives the possibility to characterizethe quality of the baseband processing with parameters like spurious-free dynamic range

(SFDR), input third-order intercept point (IIP3) or output third-order intercept point (OIP3).

Moreover the power of the transmitted signal has to be sufficiently low out of band, as spec-

ified by the mask indicated in the standard, to avoid interference with adjacent channels.

This represents the second test performed on the transmitted signal.


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20 Chapter 3

3.2 WLAN digital modulator

A model of the WLAN 802.11a digital modulator has been realized in the Matlab environ-

ment. The model has been implemented on the basis of existing tools [14] and simplified to

allow more simulation flexibility and cosimulation with models of analog blocks.

The scheme of the WLAN digital modulator is reported in Figure 3.2. The input bit-

stream is modulated into a complex bit-stream using a modulation scheme chosen among

BPSK, QPSK, 16-QAM or 64-QAM according to the desired data rate. The resulting com-

plex symbols are grouped in packets of 64 (48 data symbols, 4 pilot symbols and 12 zero

symbols) in order to apply the IFFT algorithm. The length of the packet is further increased

to 80 by adding a cyclic extension, whose aim is to reduce the effect of the intersymbol

interference (ISI). The complex stream is then parallel-to-serial converted and finally split

into a real and an imaginary part sampled at 20 MHz and applied to the digital-to-analog

converters. Figure 3.3 shows the constellation of the complex symbols in the case of a 64-

QAM modulation scheme. Figure 3.4 shows the spectrum of two orthogonal subcarriers,

while the overall spectrum of the OFDM modulated signal is shown in Figure 3.5.

3.3 UMTS digital modulator

As in the WLAN case, a simplified model of the UMTS digital modulator has been realized

in the Matlab environment (Figure 3.6) on the basis of an existing commercial tool [15].

The section taken into account is the one which allows the multiplexing of up to six uplink

dedicated physical channels prior to the transmission.

A schematic representation of the modulator is given in Figure 3.7. The six dedicated

physical data channels (DPDCH1-6) are multiplexed together with the dedicated physical

control channel (DPCCH), which contains the control information for the data channels. In

order to split the seven channels, to each one is assigned a different orthogonal spreading

Table 3.1: EVM requirements for WLAN 802.11a and UMTS.

Standard and modulation scheme EVM upper limit SNDR

WLAN, BPSK 39.8% (with 9 Mbits/s) 8 dB

WLAN, QPSK 22.3% (with 18 Mbits/s) 13 dB

WLAN, 16QAM 11.2% (with 36 Mbits/s) 20 dB

WLAN, 64QAM 5.6% (with 54 Mbits/s) 25 dB

UMTS 17.5% 15 dB

BIT-STREAM

Serial to

parallel

MODULATOR

(BPSK, QPS K,

16QAM, 64QAM)

Pilot/Zero

insertion

IFFT

Cyclic

extension

G

Parallel to

serial

... ... ... ...

48 64 64

COMPLEX

BIT ST REAM

FDSP

= 20 MHz

Figure 3.2: Schematic representation of the WLAN digital modulator.


25/143


1.5 1 0.5 0 0.5 1 1.51.5

1

0.5

0

0.5

1

1.5

I component digital value

Qc

omponen

tdigita

lva

lue

zero and pilot symbols

Figure 3.3: Constellation of the complex symbols in the case of a 64-QAM modulation

scheme.

500 0 500 1000

60

50

40

30

20

10

0

10

20

Frequency (kHz)

Power

(dBr)

orthogonal subcarriers

Figure 3.4: Spectrum of two orthogonal subcarriers.


26/143

22 Chapter 3

10 5 0 5 1060

50

40

30

20

10

0

10

Frequency (MHz)

Power

(dBr)

pilot subcarriers

Figure 3.5: Spectrum of an OFDM modulated complex WLAN signal.

Figure 3.6: Screenshot of the developed Matlab code to model the UMTS digital modulator.

code. The spreading blocks convert each symbol into a series of chips and the frequency of

the resulting chip-stream is enhanced with respect to the frequency of the bit-stream by the

spreading factor (SF). When these channels are transmitted together, the orthogonality ofthese codes ensures that the receiver can extract the overlapping data streams from the re-

ceived message. The standard makes certain assumption on the spreading operation. When

there is more than one DPDCH present, the spreading factor for all the data channels must

be set equal to 4. Note that half of the DPDCHs, the first three in the system, are assigned

to the in-phase channel, while the other three DPDCHs are assigned to the quadrature chan-

nel. Within each I/Q group the only way of recognizing the data channel is through their

spreading codes and so different spreading codes are assigned to each of them. However

since the data in the I channel can be distinguished anyway from the data in the Q channel

(they are orthogonal), the same code can be used in both groups. Figure 3.8 and Figure 3.9


27/143


DPDCH1

DPDCH3

DPDCH5

DPDCH2

DPCCH

Re-Im to

ComplUPLINK

ScramblerCompl to

Re-Im

Root RaisedCosine Digital

Filter

Root RaisedCosine Digital

Filter

I BIT

STREAM

Q BIT

STREAM

G

G

G

G

G

BPSK symbol

mapper

BPSK symbol

mapper

BPSK symbol

mapper

BPSK symbol

mapper

BPSK symbol

mapper

OVSF

spreader

OVSF

spreader

OVSF

spreader

OVSF

spreader

OVSF

spreader

Figure 3.7: Schematic representation of the UMTS digital modulator.

0 1 2 3 4 5

1

0.8

0.6

0.4

0.2

0

0.2

0.4

0.6

0.8

1

Time (s)

Digita

lva

lue

Figure 3.8: DPDCH before the spreading. The data-period is 4 times the chip-period

(0.26s), so the spreading factor must be set equal to 4.

show an example of the bit-stream associated with one of the DPDCH before and after the

spreading process.

The spreading enhances the rate of the input symbols to 3.84 MHz (this value is called

chip-rate). A group of 2560 chips constitutes a slot, whose length is 2/3 ms. The allowable

values for the SF are 4, 8, 16, 32, 64, 128 and 256, which in turn determine the allowable

value of the data-rate at the input of the spreading blocks. Like the DPDCHs, the control

channel must be spread to 2560 chips per slot. Since the DPCCH includes just 10 bits per

slot, the spreading factor is always set to 256.

After the spreading each chip-stream is passed through a gain block. The amount of gain


28/143

24 Chapter 3

0 1 2 3 4 5

1

0.8

0.6

0.4

0.2

0

0.2

0.4

0.6

0.8

1

Time (s)

Digita

lva

lue

Figure 3.9: DPDCH after the spreading, with a spreading factor equal to 4. The spreading

code is equal to: (1,1,1,1). The chip-period is 0.26 s.

is specified by the standard and is set to 1 for all the DPDCHs and 0.6 for the DPCCH. The

DPCCH is then summed with the three channels that make up the Q group, while the three

channels forming the I group are summed separately. The resulting chip-streams obtained

after the summation are reported in Figure 3.10 and Figure 3.11 for the I branch and the Q

branch respectively. The two chip-streams are then combined together to obtain a complex

chip-stream. The possible values which can be assumed by the complex chip-stream can be

plotted in the complex plane, as done in Figure 3.12.

The chip-stream is then passed through a scrambling code, which is a slot-dependent

sequence of 2560 complex numbers. The effect of the scrambling on the constellation can

be seen in Figure 3.13. The scrambling implies a rotation of the transmitted complex bits.

The purpose of the uplink scrambling is to enable more user equipments (UEs) to use the

same RF channel. Each transmitting UE scrambles its data differently (but in such a way

that the bandwidth of the transmitted signal is not altered by the scrambling) so that the

receiving node can identify the UE sending the data. Since scrambling effectively separatesthe signals from various transmitters, different transmitters can spread data on the physical

channels with the same spreading codes as the other transmitters.

The scrambled chip-stream is then divided again into a real and an imaginary part. Note

that at this point the rate of the digital signal of the I and Q branch is equal to the chip-stream

(3.84 MHz) and the complex spectrum is included between1.92 MHz and 1.92 MHz. Thetwo streams must be filtered by a root raised cosine filter with roll-off equal to 0.22. This

implies that the bandwidth of the transmitted signal is enhanced to 1.92(1+0.22) MHz andthat the shaping filter must act also as an interpolation filter with an interpolation factor at

least equal to 2.


29/143


0 1 2 3 4 53

2

1

0

1

2

3

Time (s)

Digita

lva

lue

Figure 3.10: Chip-stream relative to the I component, after the application of the gain blocks

and the summation of DPDCH1, DPDCH3, DPDCH5.

0 1 2 3 4 54

3

2

1

0

1

2

3

4

Time (s)

Digita

lva

lue

Figure 3.11: Chip-stream relative to the Q component, after the application of the gain

blocks and the summation of DPDCH2, DPDCH4, DPDCH6, DPCCH.


30/143

26 Chapter 3

4 3 2 1 0 1 2 3 44

3

2

1

0

1

2

3

4


Qc

omponen

tdigita

lva

lue

Figure 3.12: Constellation of the complex chip-stream after the combination of the I and Q

components.

8 6 4 2 0 2 4 6 88

6

4

2

0

2

4

6

8


Q

componen

tdigita

lva

lue

Figure 3.13: Effect of the scrambling on the constellation of the complex chip-stream.


31/143


white noise

+IN

transferfunction

OUT

saturationlimits

3

3

2

21xaxaxa +

non-linearityeffects

+

Figure 3.14: Model of the filter block including non-idealities.

3.4 Baseband section of the direct conversion transmitter

The two analog blocks constituting the baseband section of the transmitter have been de-

scribed by time-domain Matlab models. The DAC has been characterized with its input

number of bits and conversion frequency as well as with appropriate noise and distortion

effects. An interpolation block between the DSP and the DAC has been considered in or-

der to enhance the signal sampling frequency to the value required by the DAC. Moreover

the DAC model takes into account different types of current-steering architectures (binary,

thermometric or segmented). As it will be explained in the next chapter, these are the most

used architectures for telecommunication applications.

The analog reconstruction filter model includes four sources of non-idealities: noise,

distortion, the implemented transfer function and a saturation limit. The resulting model is

shown in Figure 3.14. Noise is modeled as a random Gaussian signal summed at the block

input, while distortion is modeled in terms of input second-order intercept point (IIP2) and

IIP3, assuming the presence of a polynomial input-output relation of the type:

y= a1x + a2x2+ a3x

3. (3.3)

The saturation limit comes from the available supply voltage (1.2 V), assuming the use of

a fully-differential architecture. The linear part of the block is represented by a transfer

function. For an easier calculation of parameters like SNDR, the phase component of the

transfer function has been set equal to zero (this means no delay between the input and the

output signal).

3.5 Block specifications for WLAN 802.11a and UMTS

The developed Matlab model has allowed us to determine the specifications for each block

of the baseband section in order to satisfy the requirements of the two standards. In par-

ticular we deal with device #2 which can be embedded in a reconfigurable transmitter for

WLAN and UMTS. The main parameters of interest are: DAC input number of bitsN; DAC conversion frequencyFc; the type of transfer function that the reconstruction filter must provide; the signal amplitudes at the DAC output and at the filter output (and hence the presence

of an eventual filter gain);

the linearity of the filter in terms of IIP3 and IIP2.The specifications have been determined including in the model only one parameter at

a time, while all the rest of the transmitter was supposed ideal. In this way we can evalu-

ate the dependence of the SNDR on the parameter of interest, founding in particular where


32/143

28 Chapter 3

Transistorlevel design Block non idealities

(thermal noise,mismatch, ...)

YES

TRANSISTOR-LEVEL DESIGNSYSTEM-LEVEL STUDY

Standardrequirements met?

Standardrequirements met?

NO

YES

END

Main parameters specification: N,Fc, filter transfer function

Time-domain transmitter Matlab model

NO

Figure 3.15: Flow diagram of the adopted approach for the system-level study and the

analog blocks design.

its effect is minimized and does not influence the performance of the overall transmitter.

Moreover the spectrum of the signal at the output of the blocks is analyzed to verify that it

lies under the emission mask indicated by the standard. The model has also been used for

a verification of the effectiveness of the two blocks transistor-level design. The basebandsection non-idealities, such as the thermal noise or the transistor mismatch, have been char-

acterized on the basis of transistor-level simulations and included in the Matlab model to

verify the impact of each non-ideality on the transmitter performance. The flow diagram of

the adopted approach for the system-level study and the transistor-level design of the two

analog blocks is illustrated in Figure 3.15.

The first parameter to be found is the DAC input number of bits. The number of bits

Nused to quantize the digital signal coming from the DSP determines the resolution of the

signal at the DAC output and consequently its SNR. If we suppose that the DAC has the

lowest allowable conversion frequency (two times the signal bandwidth) and that the fol-

lowing reconstruction filter is ideal, the SNR in the signal bandwidth (equal to the Nyquist

frequency) is given only by the quantization noise. The signal effective number of bits is

therefore equal to the DAC input number of bits. The SNR value, expressed in dB, is equal

to:

SNR= 6.02N+ 1.76 , (3.4)where the quantity accounts for the different crest factor of a WLAN/UMTS signal and

a sinusoidal signal (as explained in A.1). In the worst case the value of is equal to about

9 dB for the WLAN signal and 7 dB for the UMTS signal. In Figure 3.16 the SNR as a

function of the DAC input number of bits is reported for both standards. The minimum

required SNR at the antenna is also indicated. A suitable choice is to fix the signal effective

number of bits to 8. This lets a margin of 15 dB for the non-idealities of the other blocks of

the transmitter.


33/143


2 4 6 8 10 12 140

10

20

30

40

50

60

70

80

Input nuber of bits

SNR(dB)

15 dB

WLAN SNR limit (64QAM)

UMTS SNR limit

WLAN SNR

UMTS SNR

Figure 3.16: SNR as a function of DAC input number of bits for WLAN and UMTS.

This level of in-band quantization noise can be obtained with different combinations

of DAC input number of bits and conversion frequency. Frequency planning affects also

the digital interpolator filter before the DAC and the analog reconstruction filter following

the DAC (Figure 3.17). A high conversion frequency increases the complexity of the first

block, a low conversion frequency makes difficult the design of the analog filter. In the

WLAN case, the system-level study shows that with a conversion frequencyFc of 100 MHz

(i.e. 5 times the DSP output rate) a finite impulse response (FIR) interpolator digital filter

can be used between the digital signal processor and the DAC to perform the upsample [16],

while an analog fourth-order Bessel low-pass filter with cut-offfrequency of 11 MHz can be

used to suppress the images of the signal around the integer multiples ofFc well below the

emission mask. Moreover a value ofFc equal to 100 MHz sets the oversampling ratio to 5,

giving about 1 bit of additional resolution in the signal bandwidth with respect to the DAC

original resolution. To take a robust design margin we however fixed the input number of

bits to 8.

In the case of UMTS the conversion frequency is set to 50 MHz, while the filtering trans-fer function remains a fourth-order Bessel low-pass, with a cut-offfrequency of 2.5 MHz.

The values obtained from the system-level study are confirmed by many works in liter-

ature [1719], where the typical values of the DAC conversion frequency are about one

hundred MHz, the DAC number of bits is between 8 and 11 and the filtering is done with

an order between 3 and 4.

The simulation results coming from the system-level study performed with the WLAN

time-domain model are reported as an example. Figure 3.18 shows the spectrum of the

WLAN signal at the output of an ideal interpolator filter increasing the signal sampling fre-

quency from 20 MHz to 100 MHz. The baseband spectrum, whose bandwidth is 10 MHz, is


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30 Chapter 3

DAC

ANALOG

OUTPUTanalog

filterdigital

interpolator filter

DIGITAL

INPUT

f

01011

|S| |S|

N

11001

FDSP 2FDSP3FDSP fFc

|S|

fFc

|S|

fFc

f

|S| |S|

FDSP 2FDSP3FDSP fFc

|S|

fFc

|S|

fFc

high DAC conversion frequency

low DAC conversion frequency

Figure 3.17: Impact of the DAC conversion frequency on the digital interpolator filter and

on the analog reconstruction filter implementation.

0 50 100 150 200 250 300400

350

300

250

200

150

100

50

0

50

Frequency (MHz)

Power

(dBr)

baseband signal

Figure 3.18: Spectrum of the ideal 100-MHz WLAN signal.

replicated around the multiples of the sampling frequency. Figure 3.19 shows the spectrum

of one of the two components of the WLAN signal at the output of the DAC. The presence

of the 8-bit quantization noise as well as the effect of the sinc attenuation are apparent

in the spectrum. Figure 3.20 shows the spectrum at the output of the analog reconstruction

filter, where the signal replicas are attenuated well below the standard emission mask.


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0 50 100 150 200 250 300120

100

80

60

40

20

0

20

Frequency (MHz)

Power

(dBr)

baseband signal

sinc attenuated replicas

Figure 3.19: Spectrum of the WLAN signal at the output of the 8-bit 100-MHz DAC.

0 50 100 150 200 250 300

200

150

100

50

0

Frequency (MHz)

Power

(dBr)

baseband signal

attenuated replicas

Figure 3.20: Spectrum of the WLAN signal at the output of the 4th-order low-pass Bessel

filter.


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32 Chapter 3

Considering only the quantization noise from zero to infinity, the effect of the Besselfilter is to enhance the SNR of the WLAN signal from 41 dB (the value at the DAC output)

to 47 dB (which are equivalent to 8 bits and 9 bits respectively, accounting for the WLAN

signal crest factor).

If the signal at the output of the block is compared with an ideal WLAN signal (i.e.

the one coming from a transmitter with no quantization and an ideal 10-MHz low-pass

filtering), the SNDR results in about 32 dB. As we are accounting all the sources of noise

and distortion (quantization noise, signal replicas and in-band amplitude distortion of the

signal provided by the DAC sinc filtering and the low-pass filtering) this value represents

the most pessimistic evaluation of the signal resolution. The in-band amplitude distortion is

the most significant component in the SNDR, as if we limit the SNDR evaluation from zero

to 10 MHz the obtained value remains unchanged with respect to the previous one. The

value of 32 dB is higher than the SNDR target for the 64-QAM modulation, equal to 25 dB.The effective number of bits in this case cannot be calculated on the basis of the equiv-

alent full-scale (FS) sinusoidal signal as done before. If we consider only the quantization,

the noise floor is the same for a WLAN input signal and for a sinusoidal input signal, so the

WLAN crest factor can be correctly used to obtain the WLAN signal effective number of

bits. If we account for the distortion components such as the signal replicas or the in-band

amplitude distortion, the use of the equivalent full-scale sinusoidal signal is no longer valid,

as the noise and distortion components relative to the WLAN signal are greater than the

noise and distortion components relative to the sinusoidal signal. The effective number of

bits calculated in this way represent however a worst-case estimation. With 32 dBm we

obtain a value of 6.6 bits. Figure 3.21 shows the overall noise and distortion components of

the error at the filter output. The effect of the quantization noise alone is also indicated.

In the case of an input sinusoidal signal the noise and distortion components are repre-

sented by the quantization noise and signal replicas. In the SNDR calculation the effect of

amplitude error caused by the filter transfer function is not taken into account (Figure 3.22).

In this case the SNDR at the filter output is equal to 55.6 dB (9 bits).

In the case of UMTS the low-pass filtering increases the SNR due to the quantization

noise from 43 dB to 53 dB (which are equivalent to 8 bits and 9.7 bits respectively, ac-

counting for the UMTS signal crest factor). The SNDR at the output of the filter calculated

considering all sources of noise and distortion is equal to 32 dB, equivalent to 6.2 bits. As

in the previous case, the dominant source of distortion is represented by the in-band signal

amplitude distortion due to the DAC sinc filtering and the low-pass filter transfer func-

tion. In the case of a sinusoidal signal, we obtain a total SNDR at the filter output of 60 dB

(9.7 bits).

The amplitudes of the signals at the output of the DAC and filter come from a system-

level partitioning of the overall transmitter gain. A suitable differential signal level at theDAC output is 700 mVpp, which corresponds to a WLAN signal power of8 dBm and anUMTS signal power of6 dBm, while at the filter output the differential signal amplitudeis equal to 1.8 Vpp, which corresponds to a WLAN signal power of 0 dBm and an UMTS

signal power of 2 dBm. Thus a filter gain of 8 dB is necessary.

The last parameter considered is the maximum allowable distortion introduced by the

filter, evaluated in terms of IIP3 and IIP2. Figure 3.23 and Figure 3.24 report the SNDR of

the WLAN/UMTS signal at the filter output as a function of the filter IIP3 and IIP2. The

signal amplitudes and the filter gain are the one indicated before. In order to minimize the

effect of the non-linearity on the transmitter, the filter must exhibit an IIP3 of at least 20 dBm


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0 50 100 150 200 250 300180

160

140

120

100

80

60

40

20

0

Frequency (MHz)

Power

(dBr)

quantization noise

sinc and filter amplitude distortion

signal replicas

Figure 3.21: Spectrum of the quantization noise and of the overall noise and distortion

components at the output of the filter (WLAN signal).

0 50 100 150 200 250 300200

180

160

140

120

100

80

60

40

20

0

Frequency (MHz)

Power

(dBr)

Figure 3.22: Spectrum of the quantization noise and distortion components at the output of

the filter in the case of a sinusoidal signal).


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34 Chapter 3

10 20 30 40 50 60 7010

15

20

25

30

35

IIP3 (dBm), IIP2 (dBm)

SNDR(dB)

SNDR vs IIP3

SNDR vs IIP2

Figure 3.23: SNDR of the WLAN signal at the filter output as a function of the filter IIP3

and IIP2.

and an IIP2 of at least 50 dBm. In the two cases the saturation value of 32 dB comes fromthe combined effect of quantization noise, signal replicas and in-band amplitude distortion.

The same analysis has been performed for a sinusoidal signal at the input of the DAC.

Figure 3.25 shows the SNDR as a function of the filter IIP3 for the WLAN case and the

UMTS case. The saturation values for high values of IIP3 correspond to the ones indicated

before.

As the test of the baseband block is usually performed not only with real application-

dependent signals, but also with sinusoidal input signals, it is important to relate the IIP3

required performance with other parameters as third-order harmonic distortion (HD3) or

third-order intermodulation distortion (IMD3).

The time-domain models used for the evaluation of the minimum value of IIP3 allows

us to find the relationship between the filter IIP3 and the output HD3 when a full-scale input

sinusoidal signal is applied at the input of the DAC. This is indicated in Figure 3.26 fora 3-MHz full-scale input tone in the WLAN case and a 600-kHz full-scale input tone in

UMTS case. In the graph the theoretical value of the HD3 as a function of the filter IIP3 is

also reported. The relationship between HD3 and IIP3 is [20]:

HD3= 2IIP32Psig,dBm + 2 Gfilter,dB+ 9 dB, (3.5)

where Psig,dBm is the power of the sinusoidal signal at the filter output expressed in dBm.

The required value of HD3 at the filter output for the two standards is therefore equal to

about 47 dB.


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10 20 30 40 50 60 705

10

15

20

25

30

35

IIP3 (dBm), IIP2 (dBm)

SNDR(dB)

SNDR vs IIP2

SNDR vs IIP3

Figure 3.24: SNDR of the UMTS signal at the filter output as a function of the filter IIP3

and IIP2.

10 20 30 40 50 60 7010

0

10

20

30

40

50

60

70

IIP3 (dBm)

SNDR(dB)

UMTS case (9.7 bits)

WLAN case (9 bits)

Figure 3.25: SNDR for a sinusoidal signal at the filter output as a function of the filter IIP3

for the WLAN case and the UMTS case.


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36 Chapter 3

0 10 20 30 40 50 60 700

10

20

30

40

50

60

70

80

IIP3 (dBm)

SFDR(dB)

third harmonic quantization noise limit

Figure 3.26: SFDR for a full-scale 3-MHz sinusoidal signal (WLAN case) and a full-scale

600-kHz sinusoidal signal (UMTS case) at the filter output vs the filter IIP3 (black line).

The theoretical HD3 vs the filter IIP3 is also reported (blue line).

The IMD3 at the output of the baseband block is related to the filter IIP3 by the following

relationship:

IMD3 = 2IIP32Psig,dBm + 2 Gfilter,dB, (3.6)where Psig,dBm is the power of each of the two tones at the filter output. Figure 3.27 shows

the IMD3 at the filter output when two6-dB full-scale sinusoidal signals are applied at theDAC input as a function of the filter IIP3. It is apparent that the required IMD3 at the block

output is equal to about 50 dB.

Table 3.2 and Table 3.3 summarize the main parameters and required performance for

the DAC and the filter as derived from the system-level study.


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10 20 30 40 50 60 700

10

20

30

40

50

60

70

80

90

IIP3 (dBm)

I

MD3(dB)

third order distortion quantization noise

Figure 3.27: IMD3 for two6-dB full-scale sinusoidal signals (1 MHz and 1.5 MHz in theWLAN case, 100 kHz and 200 kHz in the UMTS case) at the filter output vs the filter IIP3

(black line). The theoretical IMD3 vs the filter IIP3 is also reported (blue line).

Table 3.2: DAC specifications for WLAN and UMTS.

Parameter WLAN UMTS

DAC conversion frequency 100 MHz 50 MHz

Oversampling ratio 5 10Input number of bits 8

Differential signal full-scale amplitude 700 mVpp

Full-scale application signal power 8 dBm 6 dBmFull-scale sinusoidal signal power 1 dBm

Output quantization noise power (DC to Nyquist) 49 dBm 49 dBmOutput SNR (application full-scale signal) 41 dB (8 bits) 43 dBm (8 bits)

Output SNR (sinusoidal full-scale signal) 50 dB (8 bits) 50 dB (8 bits)


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38 Chapter 3

Table 3.3: Filter specifications for WLAN and UMTS.

Parameter WLAN UMTS

Transfer function Bessel 4th-order, low-pass

Cut-offfrequency 11 MHz 2.5 MHz

Gain 8 dB

Differential signal full-scale amplitude 1.8 Vpp

Full-scale application signal power 0 dBm 2 dBm

Full-scale sinusoidal signal power 9 dBm

Output SNR (application full-scale signal) 47 dB (9 bits) 53 dB (9.7 bits)

Output SNR (sinusoidal full-scale signal) 56 dB (9 bits) 60 dB (9.7 bits)

Required output SNR (application full-scale signal) 41 dB (8 bits) 43 dB (8 bits)

Design margin 6 dB (1 bit) 10 dB (1.7 bits)

Output SNDR (application full-scale signal) 32 dB (6.6 bits) 32 dB (6.2 bits)

Output SNDR (sinusoidal full-scale signal) 55.6 dB (9 bits) 60 dB (9.7 bits)

Required IIP3 20 dBm 20 dBm

Required in-band HD3 @ full-scale 47 dBm 47 dBm

Required IMD3 @6-dB full-scale 50 dBm 50 dBmRequired IIP2 50 dBm 50 dBm


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Chapter 4

Circuit Design

In this chapter the circuit design of the baseband blocks (device #2) for the WLAN/UMTS

multistandard wireless transmitter is presented. The attention is focused in particular on the

8-bit 100-MHz digital-to-analog converter. The choice of the most suitable architecture to

achieve the performance requirements is presented in Section 4.1. Considerations about the

high conversion frequency and the linearity requirements lead to the choice of a differential

current-steering fully-thermometric DAC.

The most important design issue is represented by the matching of the unit current

sources realizing the digital-to-analog conversion. Therefore the Pelgrom model for the

matching of transistors is reviewed in Section 4.2. The effect of the mismatch error on each

current source is taken into account in Section 4.3, indicating the relationship between the

DAC integral non-linearity (INL) and differential non-linearity (DNL) to the relative vari-

ance of the mismatch error. An upper bound for the relative variance is then found in order

to obtain INL and DNL yields of 99.9% (Section 4.4). The effect of the current sources

mismatch on the SNDR is then considered, observing that with the chosen relative variance

the degradation of the SNDR is negligible (Section 4.5). Using the Pelgrom model a lowerbound for the transistor area is found, once the overdrive voltage is fixed. The power con-

sumption budget fixes the value of the unit current, while the headroom constraint, deriving

from the 1.2-V supply voltage, limits the maximum allowable overdrive voltage. The width

and length of the unit current transistor can be found from the Pelgrom relation and the

expression of the transistor saturation current (Section 4.6).

The circuits used to drive the switches of the unit current sources are then described in

Section 4.7, as well as the stage which converts the output current into a voltage signal to be

filtered by the subsequent block (Section 4.8). Comparisons with other conventional output

stages lead to the conclusion that the adopted solution is the one that limits to a minimum

the power consumption, while achieving low static and dynamic distortion. The analog

reconstruction filter which follows the DAC is briefly described in Section 4.9.

Simulation results concerning static, dynamic and noise performance are then reported

in Section 4.10, confirming the effectiveness of the adopted design choices.

4.1 Choice of the digital-to-analog converter architecture

The difference among the variuos types of digital-to-analog converters is basically the output

analog quantity which corresponds to the input digital code. As a matter of fact, the digital

word can be converted into a voltage, a certain amount of charge or a current. Thus three

types of digital-to-analog converters can be distinguished: voltage-scaling DACs, charge-

scaling DACs or current-steering DACs. For all the types of DACs we assume that the input


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40 Chapter 4

digital binary code is is composed by NbitsbN1...b1b0, wherebN1 is the most significantbit (MSB),b0 is the least significant bit (LSB) and bi {0, 1} i. The decimal value of thecode is indicated askand its value is:

k=

N1i=0

2ibi. (4.1)

A voltage-scalingDAC usually employs a string of resistances, connected between the

supply voltage and the ground, to generate the analog voltage levels. For an N-bit DAC the

resistive string must have 2N1 unit resistances (whose value is equal toR) to obtain the 2Nquantized levels. The difference between the output values corresponding to two successive

codes is indicated as LSB and in this case it is equal to VDD/2N. Two resistances equal to

R/2 are usually added at the top and at the bottom of the string to give to the analog voltage

levels an 1/2 LSB offset. The input digital binary code can select the desired voltage level

among the available ones. As indicated in Figure 4.1, a switch tree selector can be used for

this purpose. The expression for the outpu

Analog Baseband Blocks for Multistandard Wireless Transmitters

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