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AN 888: PHY Lite for ParallelInterfaces Reference Design withDynamic Reconfiguration for Intel®Stratix® 10 Devices

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Contents

1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfigurationfor Intel® Stratix® 10 Devices....................................................................................31.1. Features...............................................................................................................31.2. Hardware and Software Requirements...................................................................... 41.3. Design System Architecture Overview...................................................................... 4

1.3.1. Functional Description................................................................................ 51.4. Dynamic Reconfiguration Overview.......................................................................... 7

1.4.1. Register Address Map.................................................................................81.4.2. Dynamic Reconfiguration API Functions........................................................ 8

1.5. PHY Lite Per-Bit Overview..................................................................................... 101.5.1. Per-Bit Deskew Concept............................................................................101.5.2. Read Deskew Algorithm............................................................................ 12

1.6. Compiling the Reference Design.............................................................................131.7. Hardware Testing.................................................................................................17

1.7.1. Setting Up the Development Kit................................................................. 171.7.2. Generating Executable and Linking Format (.elf) Programming File................. 171.7.3. Running the Hardware Reference Design..................................................... 201.7.4. Results................................................................................................... 21

1.8. Document Revision History for AN 888: PHY Lite for Parallel Interfaces ReferenceDesign with Dynamic Reconfiguration for Intel Stratix 10 Devices............................ 24

1.9. Appendix A: HiLo Loopback Card Pin Connections.....................................................261.10. Appendix B: Retrieving Lane and Pin Information................................................... 261.11. Appendix C: Decoding Parameter Table................................................................. 28

Contents

AN 888: PHY Lite for Parallel Interfaces Reference Design with DynamicReconfiguration for Intel® Stratix® 10 Devices

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1. PHY Lite for Parallel Interfaces Reference Design withDynamic Reconfiguration for Intel® Stratix® 10 Devices

The PHY Lite for Parallel Interfaces reference design demonstrates the usage of thedynamic reconfiguration feature using the PHY Lite for Parallel Interfaces Intel®Stratix® 10 FPGA IP core.

Two instances of PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP cores areplaced in different I/O tiles on a single FPGA. These PHY Lite instances are loopbackusing a custom HiLo loopback card on the Intel Stratix 10 GX FPGA development kit.One PHY Lite instance is configured as a transmitter (DUT_OUTPUT) and the other PHYLite instance is configured as a receiver (DUT_INPUT).

Figure 1. Block Diagram—PHY Lite for Parallel Interfaces Reference Design System forIntel Stratix 10 Devices

FPGAPHY Lite Instance 1

PHY Lite Instance 2

DUT_INPUT

HiLo Loopback Card

DUT_OUTPUT

82

group_0_data_outgroup_0_strobe_out

group_0_strobe_ingroup_0_data_in

Note: For the HiLo loopback card pin connections, refer to Appendix A: HiLo Loopback CardPin Connections. For more information about the HiLo loopback card, contact IntelSupport.

Related Information

Appendix A: HiLo Loopback Card Pin Connections on page 26

1.1. Features

• A Nios® II processor to perform dynamic calibration for the PHY Lite for ParallelInterfaces Intel Stratix 10 FPGA IP core.

• A set of application program interface (API) to configure delay chains for the PHYLite for Parallel Interfaces Intel Stratix 10 FPGA IP core.

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Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/orother countries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.

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1.2. Hardware and Software Requirements

To test the reference design, ensure that you have the appropriate hardware andsoftware.

Hardware

• Intel Stratix 10 GX FPGA Development Kit (Device OPN: 1SG280LU2F50E2VG)

• HiLo loopback card

• Intel FPGA Download Cable

Software

• Intel Quartus® Prime Pro Edition software version 19.1

• phylite_top.qar file

1.3. Design System Architecture Overview

This reference design consists of a calibration engine (phylite_nios.qsys) and PHYLite for Parallel Interfaces IP core instances (dut_INPUT.qsys anddut_OUTPUT.qsys) for data loopback and other functional blocks.

You can use this reference design as a starting point design and modify as required tosuit your design application.

1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel®Stratix® 10 Devices

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Figure 2. Block Diagram—PHY Lite for Parallel Interfaces Design System Architecture

Traffic Generator/Checker

Avalon Slave

Data_to_core

Rdata_valid

Avalo

n Mas

ter

Avalo

n Slav

e

DUT_INPUTDUT_OUTPUT Avalon Bus

Avalon Bus

ref_clk DQ DQSref_clk DQS DQ

ref_clk

DUT_MODULE

core_clk

Strobe_outOe_from_core

Strobe_enData_from_core

Rdata_validData_to_core

Rdata_en

‘b0

‘b0

8

2

Nios IIProcessor

DYN_CFGController

Avalon Master

Stro

be_o

utOe

_fro

m_c

ore

Stro

be_e

nDa

ta_f

rom

_cor

e

Rdat

a_en

Cfg_

done core_clk

Rdat

a_va

lidDa

ta_t

o_co

re

The reference design consists of:

• DUT_MODULE:

— DUT_INPUT

— DUT_OUTPUT

• Traffic generator/checker module

• DYN_CFG Controller

• Clocking Scheme

Related Information

PHY Lite for Parallel Interfaces Intel FPGA IP Core User Guide

1.3.1. Functional Description

1.3.1.1. DUT_MODULE

This module consists of DUT_OUTPUT and DUT_INPUT instances with dynamicreconfiguration enabled.

The DUT_OUTPUT instance acts as transmitter, which transfers data from DYN_CFGcontroller or the traffic generator module. During configuration mode, the DYN_CFGcontroller sends the test data to the DUT_OUTPUT instance. In normal operating


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mode, the DUT_OUTPUT instance takes data from the traffic generator and sends toDUT_INPUT instance. In contrast, the DUT_INPUT instance acts as receiver. The datatransmitted by the DUT_OUTPUT instance is looped back to the DUT_INPUT instance.

1.3.1.2. Traffic Generator/Checker Module

The traffic generator/checker module is responsible for transmitting data toDUT_OUTPUT and receiving data from DUT_INPUT during normal operating mode.

The transmitted data is random data generated by the Linear Feedback Shift Register(LFSR). The received data from DUT_INPUT should match with the transmitted datafor result comparison.

1.3.1.3. DYN_CFG Controller

The DYN_CFG controller module consists of a Nios II processor that acts as acentralized controller that handles the configuration of the PHY Lite for ParallelInterfaces IP core via Avalon® interface and handles control signals through parallelI/O modules.

The DYN_CFG controller module performs address translation to retrieve the physicaladdress of the strobe or data pin to be configured. This module has forward andreverse paths. In the forward path, this module transmits data to the DUT_OUTPUTmodule. In the reverse path, this module receives data from the DUT_INPUT module.

Dynamic reconfiguration code is written in the Nios II Software Build Tools for Eclipseand loaded into the instruction memory of the soft Nios II processor. The Nios IIprocessor executes this code to perform calibrations. During processing, the Nios IIprocessor writes to the register in the I/O subsystem manager (I/O SSM) to changethe DQS/DQ delay. Once the calibration is done and the data valid window is found,the Nios II processor sets cfg_done to 1 and the interface to the IP core switches tothe traffic generator. The traffic generator begins generating random data pattern andchecks against the loopback data that comes back from the IP core input.

1.3.1.4. Clocking Scheme

This design uses 133 MHz clock from the Si5338 programmable oscillator. The PHY Litefor Parallel Interfaces IP core clock transfers data between the FPGA core logic and theIP core. The interface frequency between two PHY Lite for Parallel Interfaces IP coreinstances is 532 MHz.


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Figure 3. Clocking Scheme for the PHY Lite for Parallel Interfaces Reference Design

Nios IIProcessor

Avalon Master

Traffic Generator/Checker

Avalon Slave

Data_to_coreRdata_valid

Avalo

n Mas

ter

Avalo

n Slav

e

DUT_INPUTDUT_OUTPUT

DYN_CFGController

Avalon Bus

ref_clk DQ DQSref_clk DQS DQ

ref_clk = 133 MHz

DUT_MODULE

core_clk

core_clk

core_clk = 133 MHz

Interface Frequency = 532 MHzAvalon Bus

1.4. Dynamic Reconfiguration Overview

Dynamic reconfiguration reconfigures the input and output delays in the PHY Lite forParallel Interfaces IP core.

This feature allows you to perform real-time configuration on the delay of DQS/Strobeor DQ/data signals. This feature helps to maximize the data valid window, allowing thedesign to achieve timing closure at high frequency. You can turn on Use dynamicreconfiguration in the parameter editor of the PHY Lite for Parallel Interfaces IntelStratix 10 FPGA IP core in Intel Quartus Prime Pro Edition software and thereconfiguration is performed via the Avalon-MM interface.


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1.4.1. Register Address Map

Figure 4. Intel Stratix 10 Register Address Map

Legend:CSR = Configuration status registerAVL = Avalon-MM interface register

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0CSRAVLCSRAVLCSRAVLCSRAVLCSRAVLCSRAVL

Read valid delay

Features

Pin output phase

Pin input delay

Strobe input delay

Strobe enable phase

Strobe enable delay

Bit Address Mapping

N/A

ID[3:0] cal_add 3'h0 lane_addr[7:0] 13'h180C

ID[3:0] cal_add 3'h0 lane_addr[7:0] 13'h1808ID[3:0] cal_add 3'h0 lane_addr[7:0] 13'H19a4

4'h03'h0 lane_addr[7:0] 13'H19a8

ID[3:0] cal_add 3'h0 lane_addr[7:0] 4'hC lgc_sel

4'h03'h0 lane_addr[7:0] 13'h1998

ID[3:0] cal_add 3'h0 lane_addr[7:0] 4'hC 2'h01

4'h0N/A N/A N/A N/A N/A N/A

ID[3:0] cal_add 3'h0 lane_addr[7:0] 4'hC lgc_sel

3'h0 lane_addr[7:0] Pin[4:0] 8'E8

3'h6

3'h7ID[3:0]

ID[3:0]

N/A

cal_add

cal_add

N/A N/A N/A N/A N/A N/AID[3:0] cal_add 3'h0 lane_addr[7:0] Pin[4:0] 8'D0

pin_off

ID[3:0] cal_add (1)

(5)

(2)(3)(4)

(5)

Notes to Figure 4 on page 8:

1. Pin[4:0]—Physical location of the pin in a lane. Refer to Appendix C: DecodingParameter Table for more information.

2. lane_addr[7:0]—Address of a given lane in an interface. The fitter sets thisaddress value. Refer to Appendix C: Decoding Parameter Table for moreinformation.

3. Once the lane and pin addresses of the target PHY Lite for Parallel Interfacesinterface is captured, the target pin can get reconfigured by Read/Write throughcalibration offset address, for example, cal_add = 3’b011.

4. ID[3:0]—Interface ID parameter. This parameter distinguishes between differentIP instances in an I/O column.

5. For the physical addresses of lgc_sel and pin_off, refer to the AddressRegister for Pin Input Delay Feature table in the PHY Lite for Parallel InterfacesIntel Stratix 10 FPGA IP Core Control Registers Addresses section of the PHY Litefor Parallel Interfaces Intel FPGA IP Core User Guide.

Related Information

• Appendix C: Decoding Parameter Table on page 28

• PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP Core Control RegistersAddresses

1.4.2. Dynamic Reconfiguration API Functions

Table 1. Dynamic Reconfiguration API Functions

API Function Access Type(R/W)

Argument Return Value Description

Read_Param_table R N/A Parametercontents

Retrieve parameter table contentsfrom the I/O SSM memory.

get_output_delay R • ID• NUM_GROUP• PIN• CSR

DELAY value Read from thePIN_OUTPUT_DELAY register forthe specified ID, group number,and pin number.Specified CSR to:

continued...


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• 0 to read from Avalon register.• 1 to read from CSR register.

get_data_input_delay

R • ID• NUM_GROUP• PIN

DELAY value Read from the PIN_INPUT_DELAYregister for the specified ID, groupnumber, and pin number.

get_strobe_input_delay

R • ID• NUM_GROUP

DELAY value Read from theSTROBE_INPUT_DELAY registerfor the specified ID and groupnumber.

get_strobe_enable_delay

R • ID• NUM_GROUP• CSR

DELAY value Read from the STROBE_EN_DELAYregister for the specified ID andgroup number.Specified CSR to:• 0 to read from Avalon register.• 1 to read from CSR register.

get_strobe_enable_phase


DELAY value Read from the READ_EN_PHASEregister for the specified ID andgroup number.Specified CSR to:• 0 to read from Avalon register.• 1 to read from CSR register.

get_read_valid_delay


DELAY value Read from theREAD_VALID_DELAY register forthe specified ID and groupnumber.Specified CSR to:• 0 to read from Avalon register.• 1 to read from CSR register.

set_output_delay W • ID• NUM_GROUP• PIN• DELAY value

N/A Write to PIN_OUTPUT_DELAYregister for the specified ID, groupnumber, and pin number.

set_data_input_delay

W • ID• NUM_GROUP• PIN• DELAY value

N/A Write to PIN_INPUT_DELAYregister for the specified ID, groupnumber, and pin number.

set_strobe_input_delay


N/A Write to STROBE_INPUT_DELAYregister for the specified ID andgroup number.

continued...


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set_strobe_enable_delay


N/A Write to STROBE_ENABLE_DELAYregister for the specified ID andgroup number.

set_strobe_enable_phase


N/A Write to STROBE_ENABLE_PHASEregister for the specified ID andgroup number.

set_read_valid_delay


N/A Write to READ_VALID_DELAYregister for the specified ID andgroup number.

Notes to Table 1 on page 8:

1. ID—Interface ID set during PHY Lite for Parallel Interfaces instantiation.

2. NUM_GROUP—The number of data/strobe groups in the interface.

3. PIN—Logical pin of the interface.

4. DELAY value—Refer to Control Registers Description section of the PHY Lite forParallel Interfaces Intel FPGA IP User Guide.

Related Information

PHY Lite for Parallel Interfaces Intel FPGA IP Core User Guide

1.5. PHY Lite Per-Bit Overview

The PHY Lite for Parallel Interfaces IP core has the per-bit calibration capability that isused to calibrate each DQ pin delay to achieve maximum performance.

When a large amount of DQ pins are used on high-speed transfer, it is very likely thatmost of the DQ have a narrower passing window. This limits the maximumperformance of the system, as well as having the possibility of data corruption.

1.5.1. Per-Bit Deskew Concept

In real-life cases, the time DQ signal reaches the receiving side varies, depending onboard skew, trace length mismatch, unit variation, and so on. All these factors mayresult a narrower DQ window than expected, as shown in the following figure:


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Figure 5. Passing Window Result Before Per-Bit DeskewThis figure shows data are skewed due to board trace different and other factors, resulting a smaller passingwindow.

DQ_0

DQ_1

DQS

DQ_0

DQ_1

DQS

TX Side RX SideWindow

To overcome this, the PHY Lite for Parallel Interfaces IP core has the capability tocalibrate each DQ/DQS pin separately. Successful per-bit calibration may improve thetotal DQS opening window. An example of the per-bit calibration (happening on the RXside) is shown in the following figures:

Figure 6. First DQ_0 Calibrated

DQ_0

DQ_1

DQS

DQ_0

DQ_1

DQS

TX Side RX Side

Figure 7. Second DQ_1 Calibrated

DQ_0

DQ_1

DQS

DQ_0

DQ_1

DQS

TX Side RX Side


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Figure 8. Comparison of Passing Window Result Before and After Per-Bit Deskew

DQ_0

DQ_1

DQS

DQ_0

DQ_1

DQS

TX Side RX Side

Old Window

New Window

1.5.2. Read Deskew Algorithm

The PHY Lite for Parallel Interfaces IP core does not come with any calibration engineor calibration algorithm.

The read deskew algorithm gives an idea how you can write any calibration algorithmto get an optimal margin of capturing data by center aligning DQS to all DQ. Thisalgorithm calibrates the following knobs on input PHY Lite for Parallel Interfaces side.

Table 2. Knob Step Size

Knob Unit Per Step

DQSen delay 1 external interface clock cycle.

DQSen phase 1/128th VCO clock cycle.

Input DQS 1/256th VCO clock cycle.

Input per-bit DQ 1/256th VCO clock cycle.

This algorithm consists of three steps:

1. DQSen Calibration

• Sweep through DQSen (delay + phase) settings from min to max

for (cur_delay = PIN_DQS_EN_DLY_DLY_VAL_MIN; cur_dly

• Sweep dqs_input_delay from high to low.

• Find passing window width and set DQS to center.

1.6. Compiling the Reference Design

Follow these steps to set up and run the simulation reference design.

1. Download the reference design files from Design Store and restore the designusing Intel Quartus Prime Pro Edition software. For more information about theguideline to download and install the reference design files, refer to GettingStarted with the Design Store in the related information.

2. Open the reference design file (phylite_top.qpf) after successfully installingthe design templates.

3. From the Intel Quartus Prime Pro Edition software, open the dut_INPUT.qsysand dut_OUTPUT.qsys files. Make sure that the PHY Lite for Parallel InterfacesIntel Stratix 10 FPGA IP has the same configuration, as shown in the followingfigures:

Figure 9. General Tab Configuration for DUT_INPUT Module


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Figure 10. Group 0 Tab Configuration for DUT_INPUT Module

Note: Intel recommends that you optimize the terminations (OCT) to achieve goodsignal integrity to help maximize the data margins obtained aftercalibration.


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Figure 11. General Tab Configuration for DUT_OUTPUT Module


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Figure 12. Group 0 Tab Configuration for DUT_OUTPUT Module

Note: Intel recommends that you optimize the terminations (OCT) to achieve goodsignal integrity to help maximize the data margins obtained aftercalibration.

4. From the Intel Quartus Prime Pro Edition software, click Processing ➤ StartCompilation to compile the reference design.

Related Information

Getting Started with the Design Store


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1.7. Hardware Testing

1.7.1. Setting Up the Development Kit

Follow these steps to set up the Intel Stratix 10 GX FPGA development kit beforerunning the reference design.

1. Set the Intel Stratix 10 GX FPGA development kit switches to default position.

2. Connect the HiLo loopback card on the HiLo memory interface.

3. Connect the Intel FPGA Download Cable to the Intel Stratix 10 GX FPGAdevelopment kit and your host machine.

Figure 13. Intel Stratix 10 GX FPGA Development Kit Board

HiLo Loopback Card

4. Click Tools ➤ Programmer to program the /phyllite_top.sof file into the Intel Stratix 10 GX FPGA development kit.

Related Information

Intel Stratix 10 GX FPGA Development Kit User Guide

1.7.2. Generating Executable and Linking Format (.elf) Programming File

Follow the steps below to generate an executable and linking format (.elf)programming file. These steps are necessary if you would like to modify thephylite_dynamic_reconfiguration.c,phylite_dynamic_reconfiguration.h and hello_world.c files.

1. In the Intel Quartus Prime Pro Edition software version 19.1, select Tools ➤ NiosII Software Build Tools for Eclipse.


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Figure 14. Nios II Software Build Tools for Eclipse

2. Create a new workspace when the Select a workspace window prompt appears.


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Figure 15. Create New Workspace

3. Select File ➤ New ➤ Nios II Application and BSP from Template in the NiosII - Eclipse window.

Figure 16. Nios II Application and BSP from Template

4. In the SOPC Information File name parameter, browse to the location ofphylite_nios.sopcinfo file in your host machine. Click OK to select the fileand Eclipse automatically loads all CPU settings.

The phylite_nios.sopcinfo is created when generatingphylite_nios.qsys.

5. In the Project name parameter, specify your desired project name.

6. Choose Hello World as the project template.

7. Click Finish to generate the project. The Intel Quartus Prime Pro Edition softwarecreates a new directory named software in the specified project location.


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Figure 17. Nios II Application and BSP from Template Settings

8. Replace the following files from /software referencedesign with the files located in your new software directory.

• hello_world.c

• phylite_dynamic_reconfiguration.c

• phylite_dynamic_reconfiguration.h

9. In the Nios II - Eclipse window, press F5 to refresh the window and reload thenew files into the project.

10. Click Project ➤ Build Project.

11. Make sure the .elf file is generated in the new /software// directory.

1.7.3. Running the Hardware Reference Design

Follow the steps below to run dynamic calibration and start the data transfer for thehardware reference design.

Remove all other connected devices in the programming device list during JTAGconnection setup in your operating system.

1. Open two Nios II Command Shell prompts on your host machine:

a. For Windows operating system:


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i. In the Intel Quartus Prime Pro Edition software installation directory inyour host machine and double click on Nios II Command Shell.bat tolaunch the command prompt window (command prompt A).

b. For Linux operating system:

i. Go to \linux64\nios2eddirectory and run nios2_command_shell.sh to launch the commandprompt window (command prompt A).

c. Repeat this step to launch the second command shell (command prompt B).

Command prompt A is to display the dynamic calibration result. Command promptB is used to run Nios II commands.

2. In command prompt A, use the following command to run the Nios II terminalapplication for result printouts.

nios2-terminal

3. In command prompt B, go to the project top directory.

cd

4. In command prompt B, download the executable (.elf) fileinto the FPGA and start the dynamic calibration process with the followingcommand:

nios2-download -r -g software//.elf

ornios2-download -r -g software/phylite_top/s10_devkit.elf

You may observe the passing dynamic calibration result displayed in commandprompt A.

5. When the Nios II instruction memory is cleaned and calibration is done, run thefollowing command in command prompt B to reset the system, start the randomdata transfer and capture internal signals.

quartus_stp -t issp.tcl top.qpf 1 1

Note: Sent and received data are displayed in command prompt B after runningthe command.

1.7.4. Results

The hardware reference design provides:

• Dynamic calibration result

• Random data transfer result

1.7.4.1. Dynamic Calibration Result

The figures below show the per-bit calibration result log on command prompt A.


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Figure 18. Calibration Result Log (Part 1 of 2)

Initialized values

Step 1: Calibrating DQS_EN

Step 2: Calibrating DQ

Step 3: Calibrating DQS


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Figure 19. Calibration Result Log (Part 2 of 2)

Send/Receive Data

Delay values after calibration

1.7.4.2. Random Data Transfer Result

Start the random data transfer by using this command in command prompt B:

quartus_stp -t issp.tcl 1 1

The figure below shows the result log on command prompt A. The log data displaysthe following information:

• The number of words being transferred.

• The expected data value.

• The received data value.

• The passing/failing status of the test.


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Figure 20. Random Data Transfer Log

Expected Data vs Received Data

Sent 255 data packets

Status of Test

1.8. Document Revision History for AN 888: PHY Lite for ParallelInterfaces Reference Design with Dynamic Reconfiguration forIntel Stratix 10 Devices

DocumentVersion

Changes

2020.09.11 Updated the following figures:

continued...


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DocumentVersion

Changes

• General Tab Configuration for DUT_INPUT Module• Group 0 Tab Configuration for DUT_INPUT Module• General Tab Configuration for DUT_OUTPUT Module• Group 0 Tab Configuration for DUT_OUTPUT Module

2019.05.24 Initial release.


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1.9. Appendix A: HiLo Loopback Card Pin Connections

Figure 21. HiLo Loopback Card Pin Connections (For Reference Only)

Legend:NC = No connection

Loopback Connection

(bidirectional)

Intel Stratix 10 Pin

LocationPin Name DQ_Group DQ_Group Pin Name

Intel Stratix 10 Pin

LocationB27 MEM_DQA[0] DQ0 DQ16 MEM_DQA[16] U29G27 MEM_DQA[1] DQ1 DQ17 MEM_DQA[17] T30C27 MEM_DQA[2] DQ2 DQ18 MEM_DQA[18] T29C26 MEM_DQA[3] DQ3 DQ19 MEM_DQA[19] V26B25 MEM_DQA[4] DQ4 DQ20 MEM_DQA[20] U30D26 MEM_DQA[5] DQ5 DQ21 MEM_DQA[21] V25D26 MEM_DQA[6] DQ6 DQ22 MEM_DQA[22] U28D27 MEM_DQA[7] DQ7 DQ23 MEM_DQA[23] U27E26 MEM_DQSA_P[0] DQS_P0 DQS_P2 MEM_DQSA_P[2] V28F26 MEM_DQSA_N[0] DQS_N0 DQS_N2 MEM_DQSA_N[2] V27E27 MEM_DMA[0] DM0 DM2 MEM_DMA[2] V30H27 MEM_DQA[8] DQ8 CKE0 MEM_ADDR_CMD[20] L40H26 MEM_DQA[9] DQ9 CKE1 MEM_ADDR_CMD[21] K40J25 MEM_DQA[10] DQ10 CSn0 MEM_ADDR_CMD[22] G38H25 MEM_DQA[11] DQ11 CSn1 MEM_ADDR_CMD[23] H38L27 MEM_DQA[12] DQ12 RESETn MEM_ADDR_CMD[27] E40L26 MEM_DQA[13] DQ13 Wen MEM_ADDR_CMD[28] D40G25 MEM_DQA[14] DQ14 MEM_ADDR_CMD[31] H40K27 MEM_DQA[15] DQ15 NC NCJ26 MEM_DQSA_P[1] DQS_P1 ODT0 MEM_ADDR_CMD[24] G40D26 MEM_DQSA_N[1] DQS_N1 ODT1 MEM_ADDR_CMD[25] F40M27 MEM_DMA[1] DM1 NC NCT25 MEM_DQA[24] DQ24 DQ56 MEM_DQB[24] A37N27 MEM_DQA[25] DQ25 DQ57 MEM_DQB[25] B38L25 MEM_DQA[26] DQ26 DQ58 MEM_DQB[26] C38U25 MEM_DQA[27] DQ27 DQ59 MEM_DQB[27] A38N26 MEM_DQA[28] DQ28 DQ60 MEM_DQB[28] C37R26 MEM_DQA[29] DQ29 DQ61 MEM_DQB[29] B37P26 MEM_DQA[30] DQ30N25 MEM_DQA[31] DQ31 NC NCT26 MEM_DQSA_P[3] DQS_P3 DQS_P7 MEM_DQSB_P[3] A36R27 MEM_DQSA_N[3] DQS_N3 DQS_N7 MEM_DQSB_N[3] A35P25 MEM_DMA[3] DM3 DM7 MEM_DMA[7] C36K34 MEM_DQB[0] DQ32 DM8 MEM_DQ_ADDR_CMD[0] T31K33 MEM_DQB[1] DQ33 DQ64 MEM_DQ_ADDR_CMD[1] R34N33 MEM_DQB[2] DQ34 DQ65 MEM_DQ_ADDR_CMD[2] R31M33 MEM_DQB[3] DQ35 DQ66 MEM_DQ_ADDR_CMD[3] U33J34 MEM_DQB[4] DQ36 DQ67 MEM_DQ_ADDR_CMD[4] U34N32 MEM_DQB[5] DQ37 DQ68 MEM_DQ_ADDR_CMD[5] T34N31 MEM_DQB[6] DQ38 DQ69 MEM_DQ_ADDR_CMD[6] U32M34 MEM_DQB[7] DQ39 DQ71 MEM_DQ_ADDR_CMD[8] P33L32 MEM_DQSB_P[0] DQS_P4 DQS_P8 MEM_DQS_ADDR_CMD_P R32L31 MEM_DQSB_N[0] DQS_N4 DQS_N8 MEM_DQS_ADDR_CMD_N T32K32 MEM_DMA[4] DM4 DQ70 MEM_DQ_ADDR_CMD[7] V32E34 MEM_DQB[8] DQ40 A12 MEM_ADDR_CMD[12] P35F34 MEM_DQB[9] DQ41 A15 MEM_ADDR_CMD[15] N36H35 MEM_DQB[10] DQ42 BA0 MEM_ADDR_CMD[16] L36J35 MEM_DQB[11] DQ43 NC NCG35 MEM_DQB[12] DQ44 NC NCH36 MEM_DQB[13] DQ45 CASn MEM_ADDR_CMD[19] L35F35 MEM_DQB[14] DQ46 RASn MEM_ADDR_CMD[26] P36H33 MEM_DQB[15] DQ47 BA1 MEM_ADDR_CMD[17] T35G33 MEM_DQSB_P[1] DQS_P5 A13 MEM_ADDR_CMD[13] K36G34 MEM_DQSB_N[1] DQS_N5 A14 MEM_ADDR_CMD[14] K37J33 MEM_DMA[5] DM5 BA2 MEM_ADDR_CMD[18] R36D34 MEM_DQB[16] DQ48 A2 MEM_ADDR_CMD[2] M37E38 MEM_DQB[17] DQ49 A9 MEM_ADDR_CMD[9] R37D38 MEM_DQB[18] DQ50 A8 MEM_ADDR_CMD[8] P37E37 MEM_DQB[19] DQ51 A3 MEM_ADDR_CMD[3] M38D35 MEM_DQB[20] DQ52 A6 MEM_ADDR_CMD[6] K39D39 MEM_DQB[21] DQ53 A11 MEM_ADDR_CMD[11] P38E39 MEM_DQB[22] DQ54 A10 MEM_ADDR_CMD[10] N37H37 MEM_DQB[23] DQ55 A1 MEM_ADDR_CMD[1] L37E36 MEM_DQSB_P[2] DQS_P6 A4 MEM_ADDR_CMD[4] J39F36 MEM_DQSB_N[2] DQS_N6 A5 MEM_ADDR_CMD[5] J38F37 MEM_DMA[6] DM6 A7 MEM_ADDR_CMD[7] L39

NC NC NCNC

NCNC

NC

NC

1.10. Appendix B: Retrieving Lane and Pin Information

Information about each IP instance is stored in the I/O SSM named as parametertable.


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You can access the parameter table via Avalon interface at the base address offset0x5000000. The global parameter table lists all interfaces in the I/O column. Oncethe lane and pin addresses of the target PHY Lite for Parallel Interfaces interface iscaptured, the target pin can get reconfigured by Read/Write through calibrationaddress offset of 0x3000000. The base address offset, parameter table size offset,and interface offset are fixed, as defined in an algorithm shown in the following figure:

Figure 22. Flow Chart of Reading Parameter Table

Start

End

No

Yes

Initialize addr =base_address

Read parameter tablesize

Read values

addr < size

Store in memory

Increment addr by 4

The code block below is written in Nios II processor to read out the parameter table asshown in Figure 23 on page 28.

#define BASE_ADDR 0x5000000#define PT_SIZE_PTR 0x0000014#define ADDR_OFFSET 0x0000024void Read_Param_table(){ int delay = -1; int addr_offset = -1; unsigned int size = 0;


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unsigned int value = 0; int i;

addr_offset = IORD32(BASE_ADDR+ADDR_OFFSET);printf("Reading Addr Offset from Param Table: %08x\n\n",addr_offset);size = IORD32(BASE_ADDR+PT_SIZE_PTR);printf("Param Table size is %08x:\n", size);printf("\nParam Table:\n");for (addr=0x0; addr < size+1; addr += 4) {value = IORD32(BASE_ADDR+addr);printf("%d\t%03x\t0x%08x\n",addr,value); }

1.11. Appendix C: Decoding Parameter Table

Figure 23. Parameter Table Example for Intel Stratix 10 Devices

Avalon Address Data0000000200000001000000010000000C001312D0000000AC00000000000000000000001E

0000000000000000000000000000000000014840000000010000000A006C00700000005353E553E453F653F953FA53F853F753FB53F153F300014840000000010000000A009400980000005B5BE55BE4

500007C500008050000845000088500008C500009050000945000098

500000050000045000008500000C500001050000145000018500001C500002050000245000028500002C500003050000345000058500005C500006050000645000068500006C500007050000745000078

5BF75BFA5BF25BF35BF95BFB5BF15BFB00000000

500009C50000A050000A450000A850000AC

830000848200005C

PHY Lite for ParallelInterfaces IP CoreInterface IDs

(1)

(2)

(3)

(4)(5)(6)(7)

(8)

(4)(5)(6)(7)

(8)

Legend:PHY Lite for Parallel Interface 1PHY Lite for Parallel Interface 2


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Notes to Figure 23 on page 28:

1. To access the parameter table = 27’h5000000

2. To determine the size of the parameter table, generate an address. For example:

addr = 27’h5000000 + 24’h14value at addr = 0xAC

The size of parameter table is AC, which means that information about the PHYLite for Parallel Interfaces IP cores are spread from address 27’h5000000 to27’h50000AC.

3. To determine the address offset of the PHY Lite for Parallel Interfaces IP cores inthe parameter table.

• There are two PHY Lite for Parallel Interfaces IP cores in the parameter tableat address offset. For example:

27’h5000024 = 8200005C27’h5000028 = 83000084

where 0x5C address offset points to PHY Lite for Parallel Interfaces IP core 1and 0x84 address offset points to PHY Lite for Parallel Interfaces IP core 2.

• 2 and 3 (marked in yellow box) are the PHY Lite for Parallel Interfaces IP coreinterface IDs.

4. To determine the number of groups in the PHY Lite for Parallel Interfaces IP coreinterfaces:

27’h5000060 = 00000001

The underlined number indicates that there is only one group.

5. To determine the group information (for example, the number of lanes and pins ina PHY Lite for Parallel Interfaces IP core interface):

27’h5000064 = 0000000A

where num_lanes[7:6],num_pins[5:0] means lanes = 1 and pins = 10.

6. To determine the lane and pin address offsets:

27’h5000068 = 006C0070

where lane_off[31:16],pin_off[15:0] means lane off = 0x6C and pin off = 0x70.

7. To determine the lane address:

27’h500006C = 00000053

where the lane address is 0x53.

8. To determine the pin address at 27’h5000070 to 27’h5000080:

27’h5000070 = 53E553E4

where

• DQS_P = Pin 4; DQS_N = Pin 5

• DQ[0] = Pin 9; DQ[1] = Pin 6

• DQ[2] = Pin 8; DQ[3] = Pin A

• DQ[4] = Pin B; DQ[5] = Pin 7

• DQ[6] = Pin 3; DQ[7] = Pin 1


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Note: {lane_addr[7:0],0xE,pin[3:0]} for strobe and{lane_addr[7:0],0xF,pin[3:0]} for data.


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AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel Stratix 10 DevicesContents1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices1.1. Features1.2. Hardware and Software Requirements1.3. Design System Architecture Overview1.3.1. Functional Description1.3.1.1. DUT_MODULE1.3.1.2. Traffic Generator/Checker Module1.3.1.3. DYN_CFG Controller1.3.1.4. Clocking Scheme

1.4. Dynamic Reconfiguration Overview1.4.1. Register Address Map1.4.2. Dynamic Reconfiguration API Functions

1.5. PHY Lite Per-Bit Overview1.5.1. Per-Bit Deskew Concept1.5.2. Read Deskew Algorithm

1.6. Compiling the Reference Design1.7. Hardware Testing1.7.1. Setting Up the Development Kit1.7.2. Generating Executable and Linking Format (.elf) Programming File1.7.3. Running the Hardware Reference Design1.7.4. Results1.7.4.1. Dynamic Calibration Result1.7.4.2. Random Data Transfer Result

1.8. Document Revision History for AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel Stratix 10 Devices1.9. Appendix A: HiLo Loopback Card Pin Connections1.10. Appendix B: Retrieving Lane and Pin Information1.11. Appendix C: Decoding Parameter Table

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