An 8-Bit 200-MSample-s Pipelined ADC With Mixed-mode Front-End S-H Circuit

This document is downloaded from DR-NTU, Nanyang Technological

University Library, Singapore.

Title An 8-bit 200-MSample/s pipelined ADC with mixed-modefront-end S/H circuit.

Author(s) Jiang, Shan.; Do, Manh Anh.; Yeo, Kiat Seng.; Lim, WeiMeng.

Citation

Jiang, S., Do, M. A., Yeo, K. S., & Lim, W. M. (2008). An8-bit 200-MSample/s Pipelined ADC With Mixed-ModeFront-End S/H Circuit. IEEE Transactions on Circuits andSystems—I. 55(6), 1430-1440.

Date 2008

URL http://hdl.handle.net/10220/6256

Rights

© 2008 IEEE. Personal use of this material is permitted.However, permission to reprint/republish this material foradvertising or promotional purposes or for creating newcollective works for resale or redistribution to servers orlists, or to reuse any copyrighted component of this workin other works must be obtained from the IEEE. Thismaterial is presented to ensure timely dissemination ofscholarly and technical work. Copyright and all rightstherein are retained by authors or by other copyrightholders. All persons copying this information areexpected to adhere to the terms and constraints invokedby each author's copyright. In most cases, these worksmay not be reposted without the explicit permission of thecopyright holder. http://www.ieee.org/portal/site Thismaterial is presented to ensure timely dissemination ofscholarly and technical work. Copyright and all rightstherein are retained by authors or by other copyrightholders. All persons copying this information areexpected to adhere to the terms and constraints invokedby each author's copyright. In most cases, these worksmay not be reposted without the explicit permission of thecopyright holder.

1430 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO. 6, JULY 2008

An 8-bit 200-MSample/s Pipelined ADC WithMixed-Mode Front-End S/H Circuit

Shan Jiang, Manh Anh Do, Senior Member, IEEE, Kiat Seng Yeo, and Wei Meng Lim

Abstract—This paper describes an 8-bit pipelined analog-to-dig-ital converter (ADC) using a mixed-mode sample-and-hold (S/H)circuit at the front-end. The mixed-mode sampling techniquereduces signal swings in pipelined ADCs while maintaining thesignal-to-noise ratio. The reduction of signal swings relaxes theoperational amplifier (opamp) gain, slew rate, bandwidth, andcapacitor-matching requirements in pipelined ADCs. Due to themixed-mode S/H technique, the single-stage opamps and smallcapacitor sizes can be used in this pipelined ADC, leading to ahigh speed and low-power consumption. Fabricated in a 0.18- mCMOS process, the 8-bit pipelined ADC consumes 22 mW with1.8-V supply voltage. When sampling at 200 MSample/s, theprototype ADC achieves 54-dB spurious free dynamic range and45-dB signal-to-noise and distortion ratio. The measured integralnonlinearity and differential nonlinearity are 0.34 LSB and 0.3LSB, respectively.

Index Terms—Analog-to-digital converters (ADCs), digital re-ceiver, high-speed, operational amplifier (opamp), pipelined ADCs,sample-and-hold (S/H).

I. INTRODUCTION

T HE fast growing demands on high-data-rate applicationssuch as multimedia service are driving the bandwidth of

wired and wireless communication standards upwards. For ex-ample, the data rate of the next generation of the IEEE 802.11standard is expected to reach 540 Mb/s, and the signal band-width is expected to extend to 40 MHz [1].

Analog-to-digital converters (ADCs) are key components indigital communication receivers. For wideband applicationssuch as 1000BASE-T and IEEE 802.11, an ADC resolutionof 8 or 9 bits is sufficient to meet the system signal-to-noiseratio (SNR) requirement [2]–[5]. However, a sampling rate ofhundreds of Msample/s is required to support the increasingsignal bandwidth and to relax the anti-alias filter design. Inaddition, the power consumption of ADCs has to be minimizedfor the portable operation powered by battery.

The pipelined ADC architecture is a popular candidate forwideband receivers due to its high speed and power efficiency[6]–[9]. Most of the pipelined ADCs are implemented in

Manuscript received March 8, 2007; revised August 1, 2007. First publishedFebruary 2, 2008; last published July 10, 2008 (projected). This paper was rec-ommended by Associate Editor T. B. Tarim.

S. Jiang was with the Center for Integrated Circuits and Systems, School ofElectrical and Electronic Engineering, Nanyang Technologies University, Sin-gapore 639798. He is now with Avago Technologies, Singapore 768923 (e-mail:[email protected]).

M. A. Do, K. S. Yeo, and W. M. Lim are with the Center for Integrated Cir-cuits and Systems, School of Electrical and Electronic Engineering, NanyangTechnologies University, Singapore 639798.

Digital Object Identifier 10.1109/TCSI.2008.916613

switched-capacitor (SC) circuits [10][11][12][13]. The perfor-mance of an SC implemented pipelined ADC is determinedby the operational amplifier (opamp) and the capacitor size.The opamp must have high dc gain, high slew rate, and widebandwidth to meet the accuracy and speed requirements. Theopamp performance also has effects on the linearity of thesample-and-hold (S/H) circuit and pipeline stages and thus,consequently, on the overall ADC dynamic performance. Thecapacitor size is another impact factor that limits the pipelinedADC performance. In a medium-resolution pipelined ADC, thecapacitor size is limited by matching instead of thermal noise.A large capacitor size translates to higher power consumptionand lower speed.

In order to achieve a desirable SNR, a large-signal swing isrequired in pipelined ADCs. However, a large-signal swing hassignificant effects on the SC circuit performance. It increasesthe opamp gain and capacitor matching requirements, leadingto high power consumption and slow conversion speed. A large-signal swing also deteriorates the pipelined ADC’s dynamic per-formance. As the device size and supply voltage decrease, theeffects of signal swing on opamp gain and linearity become sig-nificant. A detailed analysis of these effects is described in thenext section. Thus, although single-stage cascode opamps arefast and consume less power, they are not commonly used inpipelined ADCs due to the poor gain and linearity performanceat the large-signal swing [10], [12].

This paper presents a pipelined ADC with a mixed-modeS/H circuit at the front-end that reduces the signal swing. Themixed-mode sampling technique mitigates the opamp andcapacitor-matching requirements both in the S/H circuit andpipeline stages. The relaxation on performance requirementsenables the use of a single-stage cascode opamp and smallcapacitor size in a pipelined ADC without degrading the systemperformance. A single-stage opamp and small capacitor enablelow power and high speed operation. The decrease of the signalswing also improves the whole ADC linearity.

II. IMPACT OF SIGNAL SWING ON S/H AND PIPELINED STAGES

Most pipelined ADCs include an S/H circuit at the front-endto minimize the conversion errors at high frequencies and toimprove the overall system performance. The performance ofthe S/H circuit dominates the overall ADC dynamic character-istics and plays a major role in determining the spurious freedynamic range (SFDR) and the signal-to-noise and distortionratio (SNDR) of the system [14].

The effects of signal swing on the performance of the S/Hcircuit can be illustrated by the simplified schematic of a con-ventional SC S/H circuit shown in Fig. 1 [15]. If the mismatch

1549-8328/$25.00 © 2008 IEEE

Authorized licensed use limited to: Nanyang Technological University. Downloaded on February 25,2010 at 22:05:39 EST from IEEE Xplore. Restrictions apply.

JIANG et al.: 8-b 200-MSample/s PIPELINED ADC WITH MIXED-MODE FRONT-END S/H CIRCUIT 1431

Fig. 1. Conventional S/H circuit.

between and is , as shown in Fig. 1, the S/H outputcan be expressed as

(1)

where is the opamp dc gain,denotes the feedback factor in the holding mode, and isthe input capacitance of the opamp. Equation (2) below showsthat the S/H output has a error of

due to the finite opamp gain and capacitor mismatch. Thiserror is signal-dependent and aggravates as the input signalincreases.

If this S/H circuit is used in an -bit ADC, for a full-scalestep input, the error due to the finite opamp dc gain and capac-itor mismatch must be less than half of the least significant bit(LSB) in order to avoid introducing any error to the followingpipelined stages. Thus, the opamp gain and capacitor matchingrequirements have to satisfy the following condition:

(2)

Although an S/H gain error can be tolerated in some applica-tions, the gain error drift must be minimized, which requires ahigh-opamp dc gain across temperature and process corners.

In addition, the opamp dc gain also depends on signal swing.This dependence is derived in the Appendix and can be ex-pressed as

(3)

where is the opamp dc gain when the output is zero.is the overdrive voltage of the opamp input tran-

sistor. Because the opamp dc gain varies with signal swing, thegain requirement in (2) should be the gain when a largest outputswing is applied. At this condition, the required zero outputopamp dc gain is usually much larger than that given by (2).

The variation of the opamp gain during its operation in turnintroduces nonlinearity in the S/H output. Including the opampgain variation, the output of the S/H circuit in Fig. 1 is derivedin the Appendix as

(4)

Equation (4) indicates the dependence of the S/H nonlinearityon the input signal. The above analysis does not take into ac-count the nonlinearity due to the device transconductanceand output impedance variations with the output swing.

Fig. 2. Opamp gain variation with output swing.

Fig. 3. MDAC in a 1.5-bit stage.

These two factors also contribute a large amount of nonlinearitywith the device size and supply voltage decreases [16], [17]. Anopamp gain variation with the output swing is shown in Fig. 2.

The speed of an S/H circuit is determined by the settlingtime of the opamp that can be categorized into the nonlinearslewing time and the quasilinear settling time. The requirementof opamp unity-gain bandwidth in an -bit S/H circuit ig-noring the slew time is given by

(5)

where is the ADC sampling frequency and is the feedbackfactor. The opamp unity-gain bandwidth is directly related tothe capacitive load. The larger the load capacitance, the higherthe power is required to achieve a given bandwidth.

In practice, the opamp bandwidth needs to be larger thanthe value given by (5) to take into account the slewing timeand nonoverlapping clock phases. For speed consideration, theslewing time should be minimized, which requires a high opampslew rate. The opamp with a high slew rate settles to the finalvalue in the linear settling phase. Therefore, even if the opampis not fully settled at the end of the hold mode, there is only alinear error, and an improvement of the dynamic performancecan be expected. Since the slew rate of the opamp is determinedby the output swing, the capacitive load, and the sampling fre-quency, a reduced output swing and smaller capacitive load canimprove the S/H speed and accuracy.



Fig. 4. Detailed diagram of the proposed 8-bit pipelined ADC.

The first stage of the pipeline also has the most stringent per-formance requirement. It has been proved that, for a pipelinedADC with medium resolution, the resolution of 1.5 bits perstage will give the optimized implementation [19]. The simpli-fied schematic of the multiplexing DAC (MDAC) in a 1.5-bitstage is shown in Fig. 3. In an -bit ADC, for the output errorto be less than half LSB of the remaining resolution, the opampgain and capacitor matching requirement is

(6)

and the opamp bandwidth requirement is

(7)

Similar to the S/H circuit, the signal swing also has significanteffects on the performance of the first stage as shown in (6) and(7).

III. PROPOSED ADC ARCHITECTURE

The above discussions show that the signal swing has a sig-nificant influence on the whole ADC performance. In order toreduce the signal swing, we propose a pipelined ADC with amixed-mode S/H circuit at the front-end as shown in Fig. 4.The mixed-mode S/H circuit decreases the input signal swingand has 1-bit digital output [18]. Following the S/H circuit aresix modified 1.5-bit stages. The S/H reduces the input signalswing and maintains it within the range of .Hence, the input of the 1.5-bit stage is limited within the samerange. Therefore, all of the pipelined stage outputs do not needa full-scale swing, and the opamp and capacitor matching re-quirement are relaxed. The last stage is implemented in a 2-bitflash ADC. The digital output of the pipeline stages and the 1-bitoutput from the S/H circuit are sent to the digital error correc-tion logic to remove the comparator offset errors and generatethe 8-bit digital output. Since the prototype ADC is going to betested on-wafer, a decimation circuit decimates the output databy eight and the 8-bit output data are serialized by the serial-ization circuit, becoming 1-bit output so that we do not needeight high-speed probes to tap the data out. The biasing blocksupplies the biasing currents to the S/H and pipeline stages. Thenonoverlapping clocks are generated by the clock generator.

Fig. 5. Mixed-mode S/H circuit.

IV. CIRCUIT IMPLEMENTATION

A. Mixed-Mode S/H Circuit

The schematic of the mixed-mode S/H circuit is shown inFig. 5. Although shown in single-end configuration, the S/H cir-cuit is implemented in the fully differential configuration in ourcircuit. One comparator is added to the conventional S/H circuit.The S/H operation is controlled by two nonoverlapping clockphases, namely sampling phase and holding phase .is a copy of but with an earlier falling edge. During the sam-pling phase, switches controlled by and are on, and thesampling capacitor is charged to with the aid of thevirtual ground formed by the opamp in the unity-gain configura-tion. presents the offset voltage of opamp. Meanwhile, thefeedback capacitor is charged to . The sampling phaseends at the falling edge of . At the same clock edge, thecomparator quantizes the input signal and generates the dig-ital output . Subsequently, turns off the input switchesand the bottom plate of is connected to either or

, determined by the value of . The S/H circuit isin the holding mode and the opamp offset is eliminated by theauto-zero technique [23]. As a result, the transfer function of themixed-mode S/H circuit is given as

(8)



Fig. 6. Transfer curve of the mixed-mode S/H circuit.

where

forfor

(9)

(10)

The sampled data are represented both in analog and digitalforms. The transfer curve of this mixed-mode S/H circuit is il-lustrated in Fig. 6. Also shown is the 1-bit digital output sentto the digital error correction logic. The dashed line shows thetransfer curve of the conversional S/H circuit in Fig. 1. As ex-pected, the output swing of the proposed S/H circuit is reducedand does not exceed the range to as longas the comparator offset error is smaller than . The ef-fective gain of the proposed S/H circuit equals 1, which is thesame as in [15]. The reduced analog signal swing does not de-grade the SNR or stress the following pipelined stage since nowthe information is stored both in analog and digital forms andthe full scale range is maintained.

Although the full-scale input is unchanged, the effective inputsignal to the opamp is reduced by , as can be seen in (8).Therefore, the maximum error introduced by finite opamp dcgain and capacitor mismatch isin the mixed-mode S/H circuit. If this S/H circuit is used in an

-bit ADC, for the error to be less than LSB/2, the opamp gainand capacitor matching requirements become

(11)

which is 6 dB lower than the requirement for the conventionalS/H circuit as expressed in (2). The mixed-mode S/H circuit alsoreduces the opamp bandwidth requirement which is now givenby

(12)

Although this configuration increases the gain error when theinput is in the vicinity of zero, as shown in Fig. 6, this error is stillwithin the range of LSB/2 of the full scale. Due to the reducedsignal swing, the capacitors and have a very small valueof 200 fF. In addition, since the output swing is reduced, the

Fig. 7. Two signal paths in the sampling mode.

opamp dc gain is more stable, and therefore an improvement ofthe S/H circuit linearity is expected.

Although a dedicated front-end S/H circuit can be removedand the sampling function is performed in the first stage of apipelined ADC, the input capacitance of the pipelined ADCin such an implementation is significantly increased due to themultibit first-stage configuration [20], [21]. A large input ca-pacitance stresses the driving circuit of the ADC, such as a vari-able gain amplifier (VGA) in digital receiver applications. Insome solutions, the full-scale input range of the ADC is reducedand so is the achievable dynamic range [22]. The time con-stant matching is another concern in a pipelined ADC withouta front-end S/H circuit. Although the aperture errors due to thetime constant mismatch can be treated as comparator offset er-rors and removed by the digital error correction logic, due tothe high gain of the multibit first stage, it is easy for the apertureerrors to saturate the S/H circuit output swing. This sets a limiton the highest working frequency of the pipelined ADC withouta front-end S/H circuit. Therefore, a dedicated front-end S/H isnecessary in these considerations.

Due to the additional comparator, in the sampling mode,there are two signal paths in the mixed-mode S/H circuit.One is formed by the sampling switch, the sampling capacitor

, and the opamp. The other goes through the comparator.Because of the time-constant difference between these twopaths, there exists an aperture error which is increased withthe input frequency. However, it is possible to minimize thiserror by matching the two signal paths in terms of topology andtime constant [24]. Fig. 7 shows the two signal paths during thesampling period. Instead of connecting the comparator directlyto the input signal, it is connected to the output of the samplingswitch. Thus, the two paths see the same delay caused by thesampling switch. In addition, the opamp and the comparatorboth use the falling edge of to sample and quantize theinput signal.

In actual implementation, it is difficult to match these twosignal paths particularly at high frequency due to parasitic com-ponents and second-order effects. However, based on the char-acteristic of pipelined ADCs, the aperture error due to time con-stant mismatch can be treated as comparator offset error andeliminated by the digital error correction logic. Although thiserror can be tolerated in a pipelined ADC, the errors causedby opamp offset and comparator offset will increase the outputswing, occupy a large offset correction range, and degrade theefficiency of the mixed-mode sampling technique. Therefore, in



Fig. 8. Modified 1.5-bit stage.

this design, the auto-zero technique is used for the opamp in thesampling mode to eliminate its offset error. This is realized byconnecting the opamp in the unity-gain configuration during thesampling mode. The comparator does not employ the auto-zeroconfiguration because of the speed consideration. Otherwise,the comparator has to quantize the input signal during the holdmode, which leads to a higher opamp speed requirement or com-plicates the timing scheme that uses a shorter sampling phase toincrease the time slot for amplifying. In addition, the low gain ofthe S/H circuit (equals to 1) also minimize the aperture error. Inthe worst case simulation, the aperture error is less than 20 mVwhen a 99-MHz input is sampled at 200 MS/s in the presenceof 7-mV comparator offset error.

B. Modified 1.5-bit Pipeline Stage

In the mixed-mode S/H circuit, the sampling capacitoris connected to either or during the holdingmode. Although two additional reference voltages and

can be used to implement conventional 1.5-bit pipelinestages, the implementation of additional reference voltagecircuits will increase the overall circuit complexity, powerconsumption, and die size. Therefore, in this design, all of thepipelined stages will use the same reference employedin the mixed-mode S/H circuit.

The pipelined stages 2–6 in this ADC are implemented inthe modified 1.5-bit stage as illustrated in Fig. 8. It has sim-ilar configuration as that of the mixed-mode S/H circuit. Be-cause the half reference is used, the capacitor is twice thesize of , as shown in Fig. 8. In the sampling phase , theinput signal is sampled by capacitor . At the end of , thetwo comparators, which have threshold voltages at and

, respectively, quantize the input signal and generate thedigital output 00, 01, or 10. During the amplifying phase ,

is connected to , 0, or according to the com-parator outputs. The feedback capacitor is reset at the sam-pling phase and connected around the opamp during the am-plifying phases. The auto-zero implementation eliminates theopamp offset error. The transfer function of the modified 1.5-bitstage is the same as the conventional 1.5-bit stage, which is

(13)

where is the feedback factor.denotes the opamp parasitic input capacitance. has the valueof 1, 0, or 1.

The transfer curve of the modified 1.5-bit stage ignoringthe opamp finite gain and capacitor mismatch is shown inFig. 9. Since the mixed-mode S/H circuit limits its outputwithin to , the output of the 1.5-bit stagewill not exceed theoretically. To guarantee that all ofthe pipeline stages work in half signal swing, the maximumcomparator offset error in the modified 1.5-bit stage should besmaller than .

With the output swing reduced, the opamp gain and capac-itor matching requirements in pipelined stages are also relaxedfor the same reasons discussed on the mixed-mode S/H circuit.For the first 1.5-bit stage with 1-bit effective resolution, the re-maining resolution for the following stages is bits. Theopamp gain and capacitor matching requirements are reduced to

(14)

which is 6 dB lower than the requirement for the conventional1.5-bit stage as expressed in (6).

Assume the opamp parasitic input capacitance size is half ofand the feedback factor of the modified 1.5-bit stage is

. The feedback factor of themodified 1.5-bit stage is smaller than that of conventional 1.5-bit



Fig. 9. Tcurve of the modified 1.5-bit stage.

stage, which is . Due tothe half output swing, however, the opamp gain requirement inthe modified 1.5-bit stage is reduced by

dB

(15)Since in the medium-resolution pipelined ADC, the opamp

can be designed at a relatively low gain, a smaller capacitor canbe chosen to take the advantage of signal swing reduce. In thisdesign, the value of was chosen to be 100 fF which is theminimum capacitor size supported by the process chosen. Thefoundry design guide shows that the 100-fF capacitance has a

mismatch smaller than 0.6%. For an 8-bit pipelined ADCin a conventional implementation, the mismatch should be lessthan 0.39%.

Since the output amplitude is less than half of the full scale,the opamp bandwidth requirement in the modified 1.5-bit stageis

(16)

Assuming the capacitive load of the modified 1.5-bit stage is, the input transistor transconductance of the opamp can be

express as

(17)

In the conventional 1.5-bit stage, the signal swing equals thefull scale. Therefore, a better capacitor matching is required,and consequently a larger capacitor is needed. For the conven-tional 1.5-bit stage to achieve the same accuracy as the modified1.5-bit stage which has a capacitive load of and signal swingof , the capacitive load of the conventional 1.5-bit stageneeds to be . Hence, the input transistor transconductanceof the opamp in the conventional 1.5-bit stage is

(18)

Fig. 10. Telescopic opamp with gain boosting.

The opamp power consumption is proportional to the ofthe input transistor. Therefore, although the modified 1.5-bitstage has a smaller feedback factor compared with that of theconventional design, the power consumption of the modifiedstage is lower due to the smaller capacitive load. Moreover, thereduced signal swing and capacitor size reduce the opamp slewrate requirement as well, and, thus, an improved speed is ex-pected.

C. Opamp

The gain-boosted single-stage telescopic opamp used in theS/H circuit and the pipelined stages is shown in Fig. 10. Tran-sistors - form the main telescopic opamp. To improvethe opamp gain, transistors , , and , formtwo common-source amplifiers and introduce negative feedbackloops that make the source voltages of the common-gate tran-sistors and less sensitive to the output signal. The gainboosting is only applied to the nMOS cascode transistors. Theoutput impedance of the pMOS active load are increased byincreasing the channel length of and , since the sizeof these two devices have less effect on the opamp frequencyresponse. Since the opamp output swing requirement was re-duced, the gate voltages of and are modified to increasethe of for a higher dc gain. The sameopamps used in the S/H circuit and the first 1.5-bit stage have asimulated dc gain of 64 dB. The opamps in other pipeline stageshave the same architecture as Fig. 10 but with the biasing cur-rent scaled down along the pipeline.

D. Comparators

To reduce the static power consumption, the dynamic com-parator is used in the mixed-mode S/H circuit as shown inFig. 11. The differential pair and amplify the inputsignal and transistors form a regeneration latch. When

is high, and are reset to via and. When goes low, the differential pair and com-

pare the input and and generate voltage differenceat the drain of transistors and . This voltage difference isamplified by the positive feedback of the latch therefore



Fig. 11. Dynamic comparator used in S/H.

and goes to or ground according to the inputvoltages. The offset of this comparator can be expressed as [25]

(19)

where is the threshold voltage mismatch of transistorand . is the physical dimension mismatch between

and . is the load resistance mismatch, which is con-tributed by transistors . The offset voltage in thiscomparator is dominated by the mismatch between transistor

and . Mismatch caused by other transistors is reducedby the gain of and . The offset can be reduced by de-creasing , which is controlled by the tail currentof the differential pair. Therefore, the gate of is connectedto instead of clock to reduce the offset error. Fora 20% device dimension mismatch manually introduced, thiscomparator has an offset error of less than 7 mV in the worstcase simulation.

The comparator used in pipelined stages is shown in Fig. 12.The two threshold voltages and are generatedby the dimension ratio between and[25]. The gates of and are connected to a constant bi-asing voltage to reduce offset error. In the worst case sim-ulation, this comparator has an offset error of less than 22 mV.

E. CMOS Switches

The size of switches used in a pipelined ADC usually is lim-ited by the time constant and linearity. Since the signal swing isreduced, a smaller switch size is employed in the prototype ADCto reduce the capacitive load of the opamp and improve speed.The input sampling switches of the mixed-mode S/H are im-plemented in a bootstrapped configuration to minimize the non-linearity introduced by signal-dependent switch-on resistance[26]. Other switches are implemented in CMOS transmissiongate with a ratio of m m which has been provedto be sufficient to 8-bit application in simulation with 300-mVvoltage swing.

Fig. 12. Differential dynamic comparator in pipeline stages.

F. Decimation and Serialization Blocks

In order to make the prototype ADC testable on-wafer, the8-bit digital output are decimated by 8 and serialized. Therefore,only one output pad is needed to test the prototype ADC. Thedecimation and serialization blocks are shown in Fig. 13. Alsoshown is the timing diagram of the decimation and serializationblocks. First, the sampling clock is divided by 8. The CLK/8triggers eight D-Flip-Flops to store the output every eight sam-pling clock cycles. The serialize block outputs 1-bit output everysampling clock cycle, and it takes eight clock cycles to outputthe whole 8-bit output.

V. MEASURED RESULTS

The pipelined ADC has been fabricated using the chartered0.18- m 2P6M CMOS process. The microphotograph of the dieis shown in Fig. 14. This chip occupies mm and theactive area is mm . The measured power consumptionis 22 mW excluding the decimation, serialization, and outputbuffer with 1.8-V supply voltage.

The ADC is tested on-wafer. The differential input signals,the reference voltages, and analog supply and ground areapplied to the ADC through a Cascade multicontact Eye-Pass10-pin probe. This probe also has a 450-nF built-in decouplingcapacitor between power line and ground. The differential clocksignals are injected through a Cascade Infinity GSSG probe.The digital supply and ground are brought in by a Cascadedc probe. The analog supply and digital supply are connectedtogether outside the chip. The output data are tapped out bya Cascade Infinity GSG probe, stored in an oscilloscope andanalyzed using MATLAB.

The measured differential nonlinearity (DNL) and integralnonlinearity (INL) are 0.3 LSB and 0.34 LSB when samplingat 200 MSample/s, as plotted in Figs. 15 and 16, respectively.The INL curve has three jumps and is similar to the INL of apipelined ADC with 2-bit first stage. This is due to the combi-nation of the 1-bit S/H digital output and the 1.5-bit first stage



Fig. 13. Decimation and serialization blocks and timing.

Fig. 14. Microphotograph of the pipelined ADC.

Fig. 15. Measured DNL plot.

Fig. 16. Measured INL plot.

output, which makes this ADC have a similar INL plot as thatof a 2-bit first stage.

Fig. 17 shows the measured fast Fourier transform (FFT)plot of a 90.723-MHz input with 200 MSample/s, where about54.5 dB SFDR and 44.8 dB SNDR are observed. The distortion

Fig. 17. FFT plot of 90-MHz input at 200 MSample/s.

Fig. 18. SNDR and SFDR versus input frequency at 200 MSample/s.

is dominated by the third harmonic with the frequency ofMHz MHz MHz. Plotted

in Fig. 18 are the measured SNDR versus the SFDR as func-tions of the input signal frequency while the ADC samplesat 200 MSample/s. The SFDR drops at high input frequencydue to the increasing of aperture error in the mixed-mode S/Hcircuit, which increases the signal swing in pipeline stages.The measured SNDR and SFDR as functions of samplingfrequency are plotted in Fig. 19 with a 40-MHz input signal.The SNDR and SFDR are approximately constant for low



Fig. 19. SNDR and SFDR versus sampling frequency with 40-MHz input.

TABLE IPERFORMANCE SUMMARY

sampling rate and start to drop as the sampling rate gets largerthan 180 MHz. The effective number of bits (ENOB) whensampling a 40-MHz signal at 200 MSample/s is 7.2 bits, dropsto 7 bits at 220 MSample/s, and further down to 6.5 bits at250 MSample/s.

The measured ADC results are summarized in Table I. Thereported performance of 8-bit high speed pipelined ADCs arecompared in Table II in which the figure of merit (FOM) is de-fined as

(20)

where is power consumption and is sampling frequency.The FOM of this work is 0.74 pJ/converstion, which is compa-rable with other reports in similar technologies.

VI. CONCLUSION

This paper presents the mixed-mode sampling technique thatreduces the signal swing in a pipelined ADC. The reduced signalswing relaxes the opamp gain, bandwidth, slew rate, and capac-itor-matching requirements, which leads to high speed and lowpower consumption. A modified 1.5-bit stage is proposed to co-operate with the mixed-mode S/H circuit. Small capacitor sizesare used in the prototype ADC to verify the mixed-mode sam-pling technique. Fabricated in an 0.18- m CMOS process, the

TABLE IIPERFORMANCE COMPARISON

Fig. 20. Differential amplifier.

proposed pipelined ADC shows 7.2 ENOB at 200 MSample/swith only 22-mW power consumption.

APPENDIX

The opamp dc gain depends on input and output signal swing,which can be illustrated by the differential amplifier shown inFig. 20. In this amplifier, the current differencecan be expressed as

(21)

where , , and are the channel length, width, andtransconductance of , respectively. The output impedanceof the amplifier is . Assuming , the gain ofthe amplifier equals

(22)

where is the amplifier dc gain when the outputis zero. is the input transistor overdrivevoltage.



In a short-channel device, varies significantly with thedrain–source voltage . In the saturation region, this depen-dence can be approximated as

(23)

The variation of gives rise to the nonlinearity in an opamp.The amount of nonlinearity is heavily dependent on how muchthe output signal swing, i.e., how much the changes. Inaddition, the transistor tranconductance also varies with

, which further exacerbates the opamp nonlinearity sincethe voltage gain is determined by .

The nonlinear opamp dc gain is an important source of non-linearity error in the S/H circuit. This harmonic distortion can beanalyzed via charge conservation in SC circuits. If we replacethe in (1) with in (22) and ignore the capacitor mismatch,the transfer function of the S/H circuit in Fig. 1 can be rewrittenas

(24)

where is the voltage at the opamp input, which can be ap-proximated as

(25)

Therefore

(26)

REFERENCES

[1] J. M. Wilson, “The next generation of wireless LAN emerges with 802.11n,” Technol. Intel Mag., pp. 1–8, Aug. 2004.

[2] S. Limotyrakis, S. D. Kulchycki, D. K. Su, and B. A. Wooley, “A150-MS/s 8-bit 71-mW CMOS time-interleaved ADC,” IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1057–1067, May 2005.

[3] J. Huang and R. R. Spencer, “The design of analog front ends for1000BASE-T receivers,” IEEE Trans. Circuits Syst. II, Analog Digit.Signal Process., vol. 50, no. 10, pp. 675–684, Oct. 2003.

[4] “Part 11: Wireless LAN Medium Access Control (MAC) and PhysicalLayer (PHY) Specifications High-Speed Physical Layer in the 5 GHzBand,” Sep. 1999.

[5] “Part 11: Wireless LAN Medium Access Control (MAC) and PhysicalLayer (PHY) Specifications Amendment 4: Further Higher Data RateExtension in the 2.4 GHz Band,” Jun. 2003.

[6] T. H. Meng, B. McFarland, D. Su, and J. Thomson, “Design and im-plementation of an all-CMOS 802.11a wireless LAN chipset,” IEEECommun. Mag., pp. 160–168, Aug. 2003.

[7] M. Zargari, M. Terrovitis, S. H.-M. Jen, B. J. Kaczynski, D. K. Su, andB. A. Wooley, “A single-chip dual-band tri-mode CMOS transceiverfor IEEE 802.11a/b/g wireless LAN,” IEEE J. Solid-State Circuits, vol.39, no. 12, pp. 2239–2249, Dec. 2004.

[8] S. S. Mehta, D. Weber, M. Terrovitis, K. Onodera, T. H. Meng, and B.A. Wooley, “An 802.11g WLAN SoC,” IEEE J. Solid-State Circuits,vol. 40, no. 12, pp. 2483–2491, Dec. 2004.

[9] S. Khorram, H. Darabi, Z. Zhou, Q. Li, T. F. J. Trachewsky,and A. Rofougaran, “A fully integrated SoC for 802.11b in0.18- �m CMOS,” IEEE J. Solid-State Circuits, vol. 40, no.12, pp. 2492–2501, Dec. 2005.

[10] J. Arias, V. Boccuzzi, L. Quintanilla, L. Enríquez, D. Bisbal, M.Banu, and J. Barbolla, “Low-power pipeline ADC for wirelessLANs,” IEEE J. Solid-State Circuits, vol. 39, no. 8, pp. 1338–1340,Aug. 2004.

[11] J. Li and U.-K. Moon, “A 1.8-V 67-mW 10-bit 100-MS/s pipelinedADC using time-shifted CDS technique,” IEEE J. Solid-State Circuits,vol. 39, no. 9, pp. 1468–1476, Sep. 2004.

[12] I. Ahmed and D. A. Johns, “A 50-MS/s (35 mW) to 1-KS/s (15 ��)power scaleable 10-bit pipelined ADC using rapid power-in opampsand minimal bias current variation,” IEEE J. Solid-State Circuits, vol.40, no. 12, pp. 2446–2455, Dec. 2005.

[13] B. Xia, A. V. Garcia, and E. S. Sinencio, “A 10-bit 44-MS/s 20-mWconfigurable time-interleaved pipeline ADC for a dual-mode 802.11b/bluetooth receiver,” IEEE J. Solid-State Circuits, vol. 41, no. 3, pp.530–539, Mar. 2006.

[14] W. Kester, Data Conversion Handbook. Amsterdam, The Nether-lands: Elsevier, 2005.

[15] I. Mehr and L. Singer, “A 55-mW, 10-bit, 40-Msample/s nyquist-rateCMOS ADC,” IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 318–325,Mar. 2000.

[16] K. Lee and R. G. Meyer, “Low-distortion switched-capacitor filter de-sign techniques,” IEEE J. Solid-State Circuits, vol. SC-20, no. 6, pp.1103–1113, Dec. 1985.

[17] W. M. Sansen, H. Qiuting, and K. A. I. Halonen, “Transient analysis ofcharge transfer in SC filters-gain error and distortion,” IEEE J. Solid-State Circuits, vol. SC-22, no. 2, pp. 268–276, Apr. 1987.

[18] S. Jiang, M. A. Do, and K. S. Yeo, “A 200-MHz CMOS mixed-modesample-and-hold circuit for pipelined ADCs,” in Proc. IFIP Int. Conf.Very Large-Scale Integr., Nice, France, Oct. 2006, pp. 352–365.

[19] S. H. Lewis, “Optimizing the stage resolution in pipelined, multistageanalog-to-digital converter for video-rate applications,” IEEE J. Solid-State Circuits, vol. 39, no. 8, Aug. 1992.

[20] S. Bardsley, C. Dillon, R. Kummaraguntla, C. Lane, A. M. A. Ali, B.Rigsbee, and D. Combs, “A 100-dB SFDR 80-MSPS 14-bit 0.35- �mBiCMOS pipeline ADC,” IEEE J. Solid-State Circuits, vol. 41, no. 9,pp. 2144–2153, Sep. 2006.

[21] T. N. Andersen, B. Hernes, A. Briskemyr, F. Telstø, J. Bjørnsen, T.E. Bonnerud, and Ø. Moldsvor, “A cost-efficient high-speed 12-bitpipeline ADC in 0.18-�m digital CMOS,” IEEE J. Solid-State Circuits,vol. 40, no. 7, pp. 1506–1513, Jul. 2005.

[22] M. Yoshioka, M. Kudo, K. Gotho, and Y. Watanabe, “A 10b 125 MS/s40 mW pipelined ADC in 0.18 �m CMOS,” in ISSCC Dig. Tech. Pa-pers, Feb. 2005, pp. 282–283.

[23] C. C. Enz and G. C. Temes, “Circuit techniques for reducing the effectof op-amp inperfections: Autozeroing, correlated double sampling, andchopper stabilization,” Proc. IEEE, vol. 84, no. 11, pp. 1584–1614,Nov. 1996.

[24] D.-Y. Chang, “Design techniques for a pipelined ADC without usinga front-end sample-and-hold amplifier,” IEEE Trans. Circuits Syst. I,Reg. Papers, vol. 51, no. 11, pp. 2123–2132, Nov. 2004.

[25] L. Sumanen, M. Waltari, and K. A. Halonen, “A 10-bit 200-MS/sCMOS parrallel pipeline A/D converter,” IEEE J. Solid-State Circuits,vol. 36, no. 7, pp. 1048–1055, Jul. 2001.

[26] M. Dessouky and A. Kaiser, “Input switch configuration for rail-to-rail operation of switched opamp circuits,” Electron. Lett., vol. 35, pp.8–10, Jan. 1999.

[27] H.-C. Kim, D.-K. Jeong, and W. Kim, “A partially switched-opamptechnique for high-speed low-power pipelined analog-to-digital con-verter,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 4, pp.795–801, Apr. 2006.

[28] J. Mulder, C. M. Ward, C.-H. Lin, D. Kruse, K. Bult, and F. M. L.van der Goes, “A 21-mW 8-bit 125-MSample/s ADC in 0.09- mm0.13- �m CMOS,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp.2116–2125, Dec. 2004.



Shan Jiang received the B.S. degree (with honors)in microelectronics from Peking University, Peking,China, in 1998. He is currently working toward thePh.D. degree at the School of Electrical and Elec-tronic Engineering, Nanyang Technologies Univer-sity, Singapore.

From 1998 to 2003, he was a System Engineer withMotorola, Beijing, China. He is currently a DesignEngineer with Avago Technologies, Singapore. Hiscurrent work focuses on data conversion and opticalsensor technologies.

Manh Anh Do (SM’05) received the B.Sc. degreein physics from the University of Saigon, Saigon,Vietnam, in 1969 and the B.E. and Ph.D. degreesfrom the University of Canterbury, Canterbury, NewZealand, in 1973 and 1977, respectively, both inelectronics.

Between 1977 and 1989, he held various positions,including Design Engineer, Production Manager,and Research Scientist in New Zealand and SeniorLecturer with National University of Singapore.He joined the School of Electrical and Electronic

Engineering, Nanyang Technological University (NTU), Singapore, as a SeniorLecturer in 1989 and became an Associate Professor in 1996 and Professorin 2001. He has been a consultant for many projects in the electronic industryand was a key consultant for the implementation of the $200 million ElectronicRoad Pricing (ERP) project in Singapore from 1990 to 2001. His currentresearch is on mobile communications, RF IC design, mixed-signal circuits,and intelligent transport systems. Before that, he specialized in sonar designingand biomedical signal processing. He has authored and coauthored over 200papers in the areas of electronic circuits and systems. Between 1995 and 2005,he was Head of Division of Circuits and Systems, NTU. Currently, he is theDirector of Centre for Integrated Circuits and Systems, NTU.

Dr. Do is a Fellow of IET and is a Chartered Engineer. He was a councilmember of IET, U.K., from 2001 to 2004 and an Associate Editor for the IEEETRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES in 2005 and 2006.

Kiat Seng Yeo received the B.Eng. degree in elec-tronics (Hons) and the Ph.D. degree in electricalengineering from Nanyang Technological Univer-sity, Singapore, in 1993 and 1996, respectively.

He began his academic career as a Lecturer in 1996and was promoted to Assistant Professor in 1999 andthen to Associate Professor in 2002. He was Sub-Dean (Student Affairs) from 2001 to 2005. Duringthis period, he held several concurrent appointmentsas Program Manager of the System-on-Chip flagshipproject, Coordinator of the Integrated Circuit Design

research group and Principal Investigator of the Integrated Circuit Technologyresearch group at NTU. He is a member of the advisory committee of the Centrefor Science Research & Talent Development of Hwa Chong Junior College andacts as consultant/advisor to statutory boards and multinational corporations inthe areas of semiconductor devices, electronics, and integrated circuit design. Hehas authored three books, Low-Voltage, Low-Power VLSI Subsystems (McGraw-Hill, 2005), Low-Voltage Low-Power Digital BiCMOS Circuits: Circuit Design,Comparative Study, and Sensitivity Analysis (Prentice-Hall, 2000), and CMOS/BiCMOS ULSI: Low-Voltage, Low-Power (Prentice-Hall, 2002). The latter wastranslated to Chinese version and is currently a superior foreign textbooks inChina. He has filed and/or been granted more than six patents and has publishedover 200 articles on CMOS/BiCMOS technology and integrated circuit designin leading technical journals and conferences worldwide.

Prof. Yeo was the Technical Chair of the 8th and 9th International Sympo-sium on Integrated Circuits, Devices and Systems (ISIC-1999 and ISIC-2001,respectively), and he also served on the program committee of the InternationalSymposium on VLSI Technology, Systems, and Applications (VLSI-TSA) inTaiwan and the International Symposium on Low-Power and High-Speed Chips(COOL Chips) in Japan in 1999 and 2002, respectively. He has been appointedHead of Circuits and Systems for a period of three years starting July 2005.He is a technical reviewer for several prestigious international journals and waslisted in Marquis Who’s Who in the World and Marquis Who’s Who in Scienceand Engineering.

Wei Meng Lim received the B.E. (Hons.) andM.E. degrees from Nanyang Technology University(NTU), Singapore, in 2002 and 2004, respectively.

Upon graduation, he joined NTU as a ResearchStaff Member. His research interests include RFcircuit design, RF device characterization, andmodeling.


An 8-Bit 200-MSample-s Pipelined ADC With Mixed-mode Front-End S-H Circuit

Documents

ensure timely

nanyang technological

worst case

nanyang technologies

small capacitor

opamp dc gain

capacitor

time constant