Advanced Analog Building Blocks - Heidelberg University

Advanced Analog Building Blocks

CMOS SWITCHES

Wei SHEN (KIP)

1

CMOS as (ideal) Switch

• when switches are used in microelectronics design?

• Sampling , Track & Hold

• Selection of different configuration

• Switches capacitor circuits ……

2© Wei SHEN, Universität Heidelberg

• what is then required by an ideal switch ?

output tracks input , no leakage (no bipolar),

no delay and distortion

CMOS switches

What is the difficulty building CMOS switches :

tracking ranges (0 - Vdd) ,

response speed (Ron , Cpara) ,

distortion & non-linearity (channel charge injection)

attempt Remedy to the problems above bootstrap

© Wei SHEN, Universität Heidelberg 3

Tracking Ranges of CMOS SW

nevertheless, the starting state can be in saturation

first discharges in saturation mode

then enters triode mode


Vg

in out

If Vout tracks Vin , the end state of the MOS cannot be in saturation

because, Vin and Vout must be smaller than Vg by at least Vth

Drain / Source can be swapped in terms of switch connection, gate connects to Vdd or Gnd

in0

Vdd

Vdd

Tracking Ranges of CMOS SW

• For a full range voltage tracking, practical solution

However, larger size, control with 2 polarities, synchronization of the two controls......


Vg

in out

If Vout tracks Vin , the tracking range of NMOS switch is only [0, Vdd – Vth]

For a PMOS only [Vth , Vdd]

Vg

inout

Not(Vg)

Useful solution for signal lines to Vdd and Gnd, e.g. In the SAR ADC reference line switching

Speed of the switch

for sampling circuits, Ron

contributes to the time constant (time dependent)

Csample * Ron should be much less than the least time constant (max Frequency) in the signal processing chain


in

Vdd

the voltage trackis not exponential

Input voltage dependenttriode resistance linear to (Vdd - Vin)

larger W/L improves speedwith more distortion (parasitics)

Speed of the switch

• as the triode resistance is dependent on the terminal voltages, calculation can only be made for rough estimation

• If the Ron variation is constrained to a range of 4, Vin(max) limits to roughly half Vdd, if the speed is a concern


Complementary Switches


triode resistance for NMOS and PMOS alone

Complementary switches,PMOS should be roughly 2 – 3 times larger …

Complementary Switches


by correcting selecting the PMOS and NMOS sizes, the conducting resistance of theSwitch can become insensitive to the tracking voltages

however, this might be just illusion …… because1. only valid for a rather limited voltage range, where the triode model is correct2. the effect is quite overestimated, because of process corners

channel charge injection


from State ON to OFF of the MOSFET, the charge in the channel must flow somewherebut not during the ON state, because charge can be provided or suck by the input

Qch = WLCox (Vdd – Vin - Vth)

1. input voltage dependent2. transistor size dependent3. for the distorted voltage, involve all the parasitic capacitance (voltage dependent)4. substrate connection also plays a huge role

GOAL : input voltage insensitive, constant offset cancelled by differential connection

Distortion from Substrate


If the substrate is not connected to signal, complication arises from the body effectRather hard to cancel out,

But if connected to signal, the floating well will give more headaches……

Parasitics on the CMOS Switch


in0

Vdd

Vdd

the triode parasitic influences the speedthe off parasitic affects the charge injection induced offset

Clock Feedthrough


ΔV = Vck𝑊𝐶

𝑜𝑣

𝑊𝐶𝑜𝑣+𝐶𝐻

during the turning off process, the clock signal will coupleinto sampling node due to parasitic, however, input voltageinsensitive, differential structure cancels this effect

However ……

this model is not fully realistic, because, the channel is on during most of the time inthe switching process, and the coupling there has to involve the triode capacitance,then the whole complexity ……

Please use simulation !! Especially post-layout simulation

Clock Feedthrough


Clock feedthrough is such a delicate issue, because most transition time are much Faster than the RC time constant of the switch, then most charges cannot be swallowed by the input source terminal due to the ON state, it is simulated below

KT/C noise

• the on resistance of the switch gives noise on the sampling capacitor, thermal noise RMS

𝐾𝑇/𝐶


KT/C noise


KT/C noise puts a limit on the minimum sampling capacitance, almost no influencefrom the channel itself !!!

in the ADC sampling circuit the unit capa has to deliver a KT/C noise negligible compared to the quantization error

Channel Charge Cancellation


try to cancel the injection channel charge by turning on another channel with complementary clock

M2 is half M1

in this case, M2 is just a dummy channel for cancellation, no other operation, however, its overlap capacitance will affect the final charge redistribution

what about the phases of the two clock signals ……

Clock Feedthrough Cancellation


If M2 is half size of M1, then the charge cancels out, however,a half charge from M1 is only estimation, Cov is also plausible

Channel Charge Cancellation


Cancellation by using complementary MOSFETs, but only for particular input

the differential sampling doesnotcancel out the charge injection

Phase shift for complementary SW


Phase shift will cause a later switching in the circuit

Cimplication follows in terms ofClock feedthrough

Remedy

But …… threshold is not at middle

Bootstrap Switch

• Imperfection of CMOS switches comes from :

channel charge injection with input voltage dependence

(partially cancelled)

clock feedthrough with input voltage dependence

(hard to cancel)

threshold voltage with substrate coupling

Solution for the first two :

making the control voltage (clock) offset to the input voltage


Bootstrap Switch


the easiest accessible constant voltage in the chip is the power supply :

the control voltage follows the input voltageand then boosted by the power supply …

as the Vgs is high enough, the Ron can be rather small, therefore, the minimum size can be used

no terminal voltage difference should exceed Vdd

Bootstrap Switch


Bootstrap Switch

• 3 key blocks in the bootstrap switch

charging the offset capacitor

discharging the switch gate to gnd

phase control


Bootstrap Switch


capacitor charge up !!

channel injection !!Charge division with parasitics and C3Reduces battery voltage ! C3 big enough

Bootstrap Switch


M10 protection at 1-0 phase

Bootstrap Switch


M8 protection at 0-1 phase

Substrate connections

• Since transistors are operating above Vdd, caution has to be paid

substrate of M8 needs to be connected to source for protection, M8 is the most dangerous transistor

• the substrate input voltage dependency is not solved, but if the MOS is small, is not serious

extra tracking circuits needed to track the inputfor substrate bias, floating well with source is not good idea


Design and Layout Issues

• M7 – M10 are responsible for rise and fall time, should be increased until parasitic loading affects the speed

• M1 M2 M3 M7 are large voltage swing

Lightly doped drain approach necessary, but not mandatory, circular gate configuration ……


Open Issues


• switches designed for ADC & Continuous sampling circuits. not perfect for physical random signal , why ?

• Capacitance charge up

• Leakage current

Physical signal tracking


Leakage Current Prevention


Leakage prevention

Examples


Exercise

• Design a bootstrap switch for a loading capacitor 1pF.

• Rising and falling time around 300ps.

• The overall non-linearity should be better than 12bits


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