A 72% PAE, 10-Watt, CMOS-LDMOS Switch-Mode Power Amplifier for Sub-1GHz Application

A 72% PAE, 10-Watt, CMOS-LDMOS Switch-Mode

Power Amplifier for Sub-1GHz Application

Ronghui Zhang1, Mustafa Acar1, Steven Theeuwen1, Mark P. van der Heijden1, Domine M. W. Leenaerts1,2

1NXP Semiconductors, the Netherlands,

2Eindhoven University of Technology, the Netherlands

Abstract — A low-cost silicon-based high efficiency CMOS-

LDMOS switch-mode power amplifier (SMPA) line-up operating for sub-1GHz application is presented. The switch-mode operated LDMOS device is driven by high-speed, high voltage

driver, implemented in a standard 0.14µm CMOS process technology. The CMOS driver uses high voltage extended-drain devices and delivers a 5.0VPP output voltage swing up to 1GHz.

The power stage is formed by the latest LDMOS transistor designed for base station applications. The load-pull measurement results show that the proposed SMPA line-up

achieves a drain efficiency (η) >80.5% and a power-added efficiency >72.6% from 450MHz to 1000MHz with an output power Pout >10W and a power gain > 26.5dB.

Index Terms — Broadband, CMOS, extended-drain MOS, high voltage, LDMOS, power amplifiers, power driver.

I. INTRODUCTION

In wireless infrastructure systems, radio frequency (RF)

power amplifiers (PAs) are considered as key blocks which

have a great impact on the power level, efficiency, linearity

and cost of the transmitter system. High efficiency and high

linearity power amplifiers are always of interest in modern

communication systems. Unfortunately, conventional linear

PAs such as class-A/AB/B PAs have good linearity but low

efficiency. On the contrary, the switch-mode power amplifiers

(SMPAs) like class-D/E/F PAs can achieve 100% efficiency

theoretically. With the techniques of envelope tracking (ET)

or linear amplification using nonlinear components (LINC),

the SMPA based transmitters can maintain high efficiency and

high linearity simultaneously. In the transmitters for base

station applications, the power stage is either formed by

gallium nitride (GaN) or laterally diffused metal-oxide-

semiconductor (LDMOS). Although the wide band-gap GaN

device is usually regarded as a superior technology because of

its high current density, fast switching speed, and low output

capacitance, LDMOS is still the mainstream RF power

technology in the current wireless infrastructure market due to

its reliable RF performance and low cost [1].

In order to drive the LDMOS as a switch, an RF driver with

high output voltage swing (>5Vpp) and short rise/fall time is

desirable [2][3]. Since the digital blocks in the transmitters are

based on deep-submicron CMOS technology, it is preferable

to interface the high power devices of SMPAs with digital

blocks using a CMOS-based driver. However, the

implementation of a PA module including the CMOS driver

and LDMOS for wideband operation is a challenging task due

to the associated low breakdown voltage of CMOS

technology. In recent years, devices with increased breakdown

voltage such as extended-drain MOS (EDMOS) have gained

interest [4]. Such devices can deliver a high voltage signal

(>5V) in a reliable manner. In the meanwhile, the high volume

applications in base station, broadcast and radar-microwave

drive LDMOS performance to be continuously improved by

decreasing the output capacitance and increasing current

capability. This has resulted in the latest NXP LDMOS

generation with some additional advantages such as

ruggedness and better thermal behavior [1].

In this paper, a possible silicon based PA solution for sub-

1GHz application is proposed using a broadband high voltage

(HV) RF driver in baseline 0.14µm CMOS in combination

with a low-cost RF LDMOS technology. To overcome the

breakdown limitations, the CMOS driver is implemented with

HV EDMOS devices. In the final stage an LDMOS device has

been chosen having a cut-off frequency of 14GHz and low

output capacitance, making switch-mode operation up to 1

GHz frequencies feasible. Section II describes the design

details of the broadband HV CMOS driver and its

measurement results. Section III gives a description of

LDMOS. In section IV, the overall circuit implementation and

measurement results of SMPA line-up are presented. Section

V concludes the proposed design.

II. HIGH VOLTAGE RF DRIVER DESIGN

To drive LDMOS transistor as a switch with small on-

resistance, a CMOS driver must deliver a pulse signal with an

amplitude exceeding 5Vpp up to 1GHz, which is conflicted

with the low supply voltage of deep-submicron CMOS

technology. To address this issue, in this work the output

driver stage is formed by a dedicated high voltage, extended-

drain, thin-oxide MOS transistors, which is implemented in

0.14µm CMOS technology. The maximum voltage limit of

EDNMOS/PMOS is 6V. The measured fT of EDNMOS and

EDPMOS are beyond 23GHz and 10GHz, respectively.

Fig. 1 shows the simplified overall schematic of CMOS-

LDMOS SMPA line-up. The HV output stage of CMOS

driver is realized by using EDMOS based inverter. The

EDNMOS transistors MN4 are directly driven by a tapered

buffer, implemented as three-stage inverter chain in low-

voltage high-speed standard CMOS technology, which

simplifies the integration of the RF driver with other analogue

and digital CMOS blocks on a single die. Besides driving

EDNMOS directly, the output pulse signal of tapered buffer is

also fed into the EDPMOS transistors MP4 via an AC-coupled

capacitor C3. The gate bias voltage of MP4 is set by external

voltage VBP. The output swing of the tapered buffer is

determined by VDDL-VSS=1.8V while that of EDMOS HV

driver is set by VDDH-VSS and can be increased up to the

maximum voltage of EDMOS devices.

Considering a given LDMOS transistor, the device sizes of

CMOS driver are chosen to satisfy the required rise and fall

time of 10% period. The size ratio of PMOS (MP1/2/3) to

NMOS (MN1/2/3) in tapered buffer and EDMOS HV driver is

approximately 2. All the transistors have minimum gate

length. The design details of the CMOS driver are given in

Table I. In order to propagate pulse signal to drive EDPMOS,

a metal-fringe based capacitor C3 (50pF) is implemented,

whose self-resonance frequency is more than 1GHz. The

internal supply lines are decoupled with the poly based

capacitor C1 (1.14nF) and metal-fringe based capacitor C2

(220pF).

To verify the proposed CMOS driver, an on-wafer test

structure is implemented (see Fig. 2). Accounting for the

current limitation of the probe system, the size of on-wafer

test structure is one third of the size in Table I. The test driver

is loaded with a 7pF capacitor to mimic an LDMOS power

device, which fairly estimates the performance. Fig. 3 shows

the measured time-domain output voltage waveforms1 of

CMOS driver at 0.5GHz and 1.0GHz with a 5V supply

voltage. As can be seen, the CMOS driver can deliver

approximately 5Vpp output swing up to 1GHz. The 10%-to-

90% rise and fall time is less than 0.1T, where T is the period

1For 0.5GHz signal, the x-axis is normalized to 2ns while it is

normalized to 1ns for 1.0GHz signal.

of the operation frequency. The dc power consumptions of the

whole CMOS driver at 0.5GHz and 1GHz are 320mW and

460mW, respectively.

III. LDMOS

The RF power device is an LDMOS transistor from the

latest generation as developed for base station applications. It

has a break down voltage of more than 65V and a snap-back

voltage of 84V.The cut-off frequency of LDMOS is 14 GHz,

as realized by a gate length of 300 nm. In the last decades, the

performance of LDMOS was continuously improved by

reducing the output capacitance and increasing the maximum

current capability. This evolution in output capacitance,

maximum current and cut-off frequency has opened the way

to use LDMOS in more applications, which were assumed to

be the domain of GaN devices. The chosen total gate width for

the final stage device is 20 mm giving a peak output power of

~20W for linear operation. LDMOS has a threshold voltage of

2V and is capable of withstanding easily the 5V square wave

driver voltage due to the thick 25 nm thick gate oxide.

IV. SMPA LINE-UP MEASUREMENT RESULTS

Fig. 4 shows the photograph of the implemented CMOS-

LDMOS SMPA line-up. The dimensions of CMOS driver and

LDMOS are 1.88×1.4mm2 and 1.5×1.2mm

2, respectively. The

distance between the CMOS and LDMOS dies and the gap

between the output of LDMOS and PCB were kept as close as

possible to limit the influence of the bond wires on the RF

Fig. 3. Measured output voltage waveforms of HV CMOS driver

at 0.5GHz (solid line) and 1.0GHz (dashed line) (VDDH=5.0V,

VDDL=1.8V, VBP=4.1V, VBN=0.9V).

TABLE I

DEVICE SIZES OF CMOS DRIVER

Width [µm] M1 M2 M3 M4

PMOS

NMOS

1920

960

3840

1920

7680

3840

10800

4800

-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1-3

-2

-1

0

1

2

3

Normalized time

Ou

tpu

t vo

ltag

e [

V]

0.5GHz

1.0GHz

Fig. 1.Simplified overall schematic of SMPA line-up including

HV CMOS driver and LDMOS.

Fig. 2.Microphotograph of the on-wafer test structure of HV

CMOS driver.

asd

VDDH

VDDL

RN

VBN

RFIN

CMOS driver

Standard CMOS

tapered buffer

VBP

RP

LDMOS

VSS

MP4

MN4

EDMOS HV

driver

MP1

MN1

MP2

MN2

MP3

MN3C1

VDDL

VSS

C2

C3

VDDH

VSS

VDD

Standard

CMOS

tapered buffer

EDPMOS

EDNMOS

C3

7p

F lo

ad

1.4mm

0.5

6 m

m

RF

IN

RF

OU

T

performance. The LDMOS is biased at VDD=20V, and the

CMOS driver is biased at VDDH=5.0V and VDDL=1.8V with

VBN=0.6V and VBP=4.4V. The proposed SMPA module was

characterized by using passive fundamental tuning load-pull

system2 from 450MHz to 1000MHz. Fig. 5 shows the

measured maximum power-added efficiency (PAE) including

all power consumption of CMOS driver and LDMOS and its

corresponding drain efficiency, output power and power gain.

Without harmonic impedance tuning, the measured drain

efficiency and PAE maintains > 80.5% and > 72.6% across

450MHz-1000MHz with an output power >40.3dBm and a

power gain>26.5dB. Comparison of the realized PA’s

performance to state-of-the-art results for multi-stage LDMOS

PAs up to 1GHz is shown in Table II. Compared with the

reported LDMOS PAs in [5] and [6], the proposed CMOS-

LDMOS SMPA provides higher PAE and flatter gain across

octave frequency range. The CMOS based driver further

lowers the cost of the whole PA line-up.

V. CONCLUSION

This work presents a high efficiency low-cost silicon based

switch-mode power amplifier line-up. Extended-drain MOS

devices are utilized to implement wideband high output

voltage CMOS driver. Together with an RF power LDMOS in

the final stage, the proposed SMPA achieves an output power

of more than 40.3dBm with a drain efficiency of >80% and

PAE of >72% from 450MHz to 1000MHz. It is a promising

candidate for broadband advanced transmitters such as polar

or outphasing systems.

REFERENCES

[1] S. J. C. H. Theeuwen, et al., “LDMOS technology for RF power amplifiers,” IEEE Trans. Microwave Theory & Tech., vol. 60, no. 6, pp. 1755-1763, June 2012.

2 The passive load-pull system only tunes the load impedance at

fundamental frequency. The second harmonic load impedance is not

tuned. The source impedance is not tuned as well and set to 50Ω.

[2] D. A. Calvillo-Cortes, et al., “A 65nm CMOS pulse-width-controlled driver with 8Vpp output voltage for switch-mode RF PAs up to 3.6GHz,” in IEEE ISSCC Digest, pp. 58-60, Feb. 2011.

[3] M. Acar, et al., “0.75 Watt and 5 Watt drivers in standard 65nm CMOS technology for high power RF applications,” in IEEE RFIC Sysm. Dig., pp. 283-286, June 2012.

[4] J. Sonsky,et al., “Innovative high voltage transistors for complex HV/RF SoCs in baseline CMOS,” in IEEE Int. Symp. VLSI-TSA, pp. 115-116, Apr. 2008.

[5] “PTMA080152M data sheet”, Infineon, Munich, Germany. [6] “MD8IC970N data sheet”, Freescale, Tempe, USA.

Fig. 5. Measured maximum PAE and its corresponding drain

efficiency, output power and power gain versus frequency

(VDD=20V, VDDH=5.0V, VDDL=1.8V, VBN=0.6V, VBP=4.4V.)

TABLE II

COMPARISON MULTI-STAGE LDMOS PAS

2011 [5] 2011 [6] This work

Freq. [MHz] 920-960 850-940 450-1000

Pout [W] 25 35 10.7-13.6

Gain [dB] 29 29.4-33.4 26.6-27.6

PAE [%] 52-57 39-44 72.6-85.5

DE [%] N.A. N.A. 80.5-89.8

Driver stage

technology LDMOS LDMOS

0.14µm

CMOS

Power stage

technology LDMOS LDMOS LDMOS

0.4 0.5 0.6 0.7 0.8 0.9 120

25

30

35

40

45

Po

ut

[dB

m],

Gain

[d

B]

Frequency [GHz]

Gain

Pout

DE

PAE

0.4 0.5 0.6 0.7 0.8 0.9 150

60

70

80

90

100

DE

, P

AE

[%

]

Pout

Gain

DE

PAE

Fig.4. Photograph of the CMOS-LDMOS SMPA line-up.

CMOS

driverLDMOS

RF

OU

T

RF

IN

VDDL

VDDL

VDDH

VDDH

VBN

VBN

VBP

VBP