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8259A PROGRAMMABLE INTERRUPT CONTROLLER (8259A/8259A · PDF fileDecember 1988 Order Number: 231468-003 8259A PROGRAMMABLE INTERRUPT CONTROLLER (8259A/8259A-2) Y 8086, 8088 Compatible

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  • December 1988 Order Number: 231468-003

    8259APROGRAMMABLE INTERRUPT CONTROLLER

    (8259A/8259A-2)

    Y 8086, 8088 Compatible

    Y MCS-80, MCS-85 Compatible

    Y Eight-Level Priority Controller

    Y Expandable to 64 Levels

    Y Programmable Interrupt Modes

    Y Individual Request Mask Capability

    Y Single a5V Supply (No Clocks)Y Available in 28-Pin DIP and 28-Lead

    PLCC Package(See Packaging Spec., Order 231369)

    Y Available in EXPRESS Standard Temperature Range Extended Temperature Range

    The Intel 8259A Programmable Interrupt Controller handles up to eight vectored priority interrupts for the CPU.It is cascadable for up to 64 vectored priority interrupts without additional circuitry. It is packaged in a 28-pinDIP, uses NMOS technology and requires a single a5V supply. Circuitry is static, requiring no clock input.

    The 8259A is designed to minimize the software and real time overhead in handling multi-level priority inter-rupts. It has several modes, permitting optimization for a variety of system requirements.

    The 8259A is fully upward compatible with the Intel 8259. Software originally written for the 8259 will operatethe 8259A in all 8259 equivalent modes (MCS-80/85, Non-Buffered, Edge Triggered).

    2314681

    Figure 1. Block Diagram

    DIP

    2314682

    PLCC

    23146831

    Figure 2. Pin

    Configurations

  • 8259A

    Table 1. Pin Description

    Symbol Pin No. Type Name and Function

    VCC 28 I SUPPLY: a5V Supply.

    GND 14 I GROUND

    CS 1 I CHIP SELECT: A low on this pin enables RD and WR communicationbetween the CPU and the 8259A. INTA functions are independent ofCS.

    WR 2 I WRITE: A low on this pin when CS is low enables the 8259A to acceptcommand words from the CPU.

    RD 3 I READ: A low on this pin when CS is low enables the 8259A to releasestatus onto the data bus for the CPU.

    D7D0 411 I/O BIDIRECTIONAL DATA BUS: Control, status and interrupt-vectorinformation is transferred via this bus.

    CAS0CAS2 12, 13, 15 I/O CASCADE LINES: The CAS lines form a private 8259A bus to controla multiple 8259A structure. These pins are outputs for a master 8259Aand inputs for a slave 8259A.

    SP/EN 16 I/O SLAVE PROGRAM/ENABLE BUFFER: This is a dual function pin.When in the Buffered Mode it can be used as an output to controlbuffer transceivers (EN). When not in the buffered mode it is used asan input to designate a master (SP e 1) or slave (SP e 0).

    INT 17 O INTERRUPT: This pin goes high whenever a valid interrupt request isasserted. It is used to interrupt the CPU, thus it is connected to theCPUs interrupt pin.

    IR0IR7 1825 I INTERRUPT REQUESTS: Asynchronous inputs. An interrupt requestis executed by raising an IR input (low to high), and holding it high untilit is acknowledged (Edge Triggered Mode), or just by a high level on anIR input (Level Triggered Mode).

    INTA 26 I INTERRUPT ACKNOWLEDGE: This pin is used to enable 8259Ainterrupt-vector data onto the data bus by a sequence of interruptacknowledge pulses issued by the CPU.

    A0 27 I AO ADDRESS LINE: This pin acts in conjunction with the CS, WR, andRD pins. It is used by the 8259A to decipher various Command Wordsthe CPU writes and status the CPU wishes to read. It is typicallyconnected to the CPU A0 address line (A1 for 8086, 8088).

    2

  • 8259A

    FUNCTIONAL DESCRIPTION

    Interrupts in Microcomputer Systems

    Microcomputer system design requires that I.O de-vices such as keyboards, displays, sensors and oth-er components receive servicing in a an efficientmanner so that large amounts of the total systemtasks can be assumed by the microcomputer withlittle or no effect on throughput.

    The most common method of servicing such devic-es is the Polled approach. This is where the proces-sor must test each device in sequence and in effectask each one if it needs servicing. It is easy to seethat a large portion of the main program is loopingthrough this continuous polling cycle and that such amethod would have a serious detrimental effect onsystem throughput, thus limiting the tasks that couldbe assumed by the microcomputer and reducing thecost effectiveness of using such devices.

    A more desirable method would be one that wouldallow the microprocessor to be executing its mainprogram and only stop to service peripheral deviceswhen it is told to do so by the device itself. In effect,the method would provide an external asynchronousinput that would inform the processor that it shouldcomplete whatever instruction that is currently beingexecuted and fetch a new routine that will servicethe requesting device. Once this servicing is com-plete, however, the processor would resume exactlywhere it left off.

    This method is called Interrupt . It is easy to see thatsystem throughput would drastically increase, andthus more tasks could be assumed by the micro-computer to further enhance its cost effectiveness.

    The Programmable Interrupt Controller (PIC) func-tions as an overall manager in an Interrupt-Drivensystem environment. It accepts requests from theperipheral equipment, determines which of the in-coming requests is of the highest importance (priori-ty), ascertains whether the incoming request has ahigher priority value than the level currently beingserviced, and issues an interrupt to the CPU basedon this determination.

    Each peripheral device or structure usually has aspecial program or routine that is associated withits specific functional or operational requirements;this is referred to as a service routine. The PIC,after issuing an Interrupt to the CPU, must somehowinput information into the CPU that can point theProgram Counter to the service routine associatedwith the requesting device. This pointer is an ad-dress in a vectoring table and will often be referredto, in this document, as vectoring data.

    2314683

    Figure 3a. Polled Method

    2314684

    Figure 3b. Interrupt Method

    3

  • 8259A

    The 8259A is a device specifically designed for usein real time, interrupt driven microcomputer systems.It manages eight levels or requests and has built-infeatures for expandability to other 8259As (up to 64levels). It is programmed by the systems softwareas an I/O peripheral. A selection of priority modes isavailable to the programmer so that the manner inwhich the requests are processed by the 8259A canbe configured to match his system requirements.The priority modes can be changed or reconfigureddynamically at any time during the main program.This means that the complete interrupt structure canbe defined as required, based on the total systemenvironment.

    INTERRUPT REQUEST REGISTER (IRR) ANDIN-SERVICE REGISTER (ISR)

    The interrupts at the IR input lines are handled bytwo registers in cascade, the Interrupt Request Reg-ister (IRR) and the In-Service (ISR). The IRR is usedto store all the interrupt levels which are requestingservice; and the ISR is used to store all the interruptlevels which are being serviced.

    PRIORITY RESOLVER

    This logic block determines the priorites of the bitsset in the IRR. The highest priority is selected andstrobed into the corresponding bit of the ISR duringINTA pulse.

    INTERRUPT MASK REGISTER (IMR)

    The IMR stores the bits which mask the interruptlines to be masked. The IMR operates on the IRR.Masking of a higher priority input will not affect theinterrupt request lines of lower quality.

    INT (INTERRUPT)

    This output goes directly to the CPU interrupt input.The VOH level on this line is designed to be fullycompatible with the 8080A, 8085A and 8086 inputlevels.

    INTA (INTERRUPT ACKNOWLEDGE)

    INTA pulses will cause the 8259A to release vector-ing information onto the data bus. The format of thisdata depends on the system mode (mPM) of the8259A.

    DATA BUS BUFFER

    This 3-state, bidirectional 8-bit buffer is used to inter-face the 8259A to the system Data Bus. Controlwords and status information are transferredthrough the Data Bus Buffer.

    READ/WRITE CONTROL LOGIC

    The function of this block is to accept OUTput com-mands from the CPU. It contains the InitializationCommand Word (ICW) registers and OperationCommand Word (OCW) registers which store thevarious control formats for device operation. Thisfunction block also allows the status of the 8259A tobe transferred onto the Data Bus.

    CS (CHIP SELECT)

    A LOW on this input enables the 8259A. No readingor writing of the chip will occur unless the device isselected.

    WR (WRITE)

    A LOW on this input enables the CPU to write con-trol words (ICWs and OCWs) to the 8259A.

    RD (READ)

    A LOW on this input enables the 8259A to send thestatus of the Interrupt Request Register (IRR), InService Register (ISR), the Interrupt Mask Register(IMR), or the Interrupt level onto the Data Bus.

    A0

    This input signal is used in conjunction with WR andRD signals to write commands into the various com-mand registers, as well as reading the various statusregisters of the chip. This line can be tied directly toone of the address lines.

    4

  • 8259A

    2314685

    Figure 4a. 8259A Block Diagram

    5

  • 8259A

    2314686

    Figure 4b. 8259A Block Diagram

    6

  • 8259A

    THE CASCADE BUFFER/COMPARATOR

    This function block stores and compares the IDs ofall 8259As used in the system. The associatedthree I/O pins (CAS0-2) are outputs when the 8259Ais used as a master and are inputs when the 8259Ais used as a slave. As a master, the 8259A sendsthe ID of the interrupting slave device onto theCAS02 lines. The slave thus selected will send itspreprogrammed subroutine address onto the DataBus during the next one or two consecutive INTApulses. (See section Cascading the 8259A.)

    INTERRUPT SEQUENCE

    The powerful features

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