8255

8255 INTRODUCTION:The 8255 is a programmable peripheral interface i.e. PPI 8255. It is a general purpose

programmable parallel I/O device. It contains 3 I/O ports which can be programmed in different modes. Those 3 I/O ports can be viewed as three 8212 IC’s with much more additional facilities provided with it. To program the function to all three I/O Ports it contains a register called as control register. The control register gives the signals which are used to define the function of each I/O Port & in which mode they should operate 8255 is general purpose in nature & provides many facilities for connecting different devices. So used frequently in different applications.

(1) 24 Programmable I/O pins.

(2) Fully Compatible with Intel microprocessor families. (3) TTL compatible.

(4) Direct Bit set/reset capability. (5) Improved DC driving capability.

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Features of 8255:

Pin Description

Q1. Draw the pin diagram of 8255 programmable peripheral interface (PPI) and explain

function of each pin.

Ans.: The pin diagram of 8255 programmable peripheral interface (PPI) is shown in figure.

The functions of various pins of 8255 PPI are as follows:

(1) D0 – D7: Data bus: These are 8 bit bidirectional data bus lines, connected to system data bus for the data transfer between 8086 & 8255. On these data lines 8086 will send control word data to initialize 8255, send data, read data, etc.

(2) : Chip select: This is an active low input signal used to select 8255 chip. If , then 8255 will be enabled and respond to and signals otherwise and signals are neglected.

(3) : Read: This is an active low input signal used in coordination with other signals to send data to CPU through data lines.

(4) : Write: This is an active low input signal used in coordination with other signals to write data to 8255. The data on D0 – D7

data line will be transferred to selected port of 8255.

(5). A0 – A1: Address lines: These are input active high address lines used to distinguish different ports of 8255 such as Port A, Port B, Port C and control register. These lines are internally used by 8255 to generate addresses as follows.

A1 A2 Selected Port0 0 Port A0 1 Port B1 0 Port C1 1 Control Register

(6) Reset: This is an active high input signal used to reset 8255. When 8255 is reset it clear control word register & all ports are set to input mode.

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8255 PIN DIAGRAM

8255PPI

1

2

3

4

5

6

7

8

9

10

11

12

13

15

14

16

17

18

20

19

40

23

21

22

24

26

25

27

29

28

30

32

31

35

33

34

39

36

38

37

RESET

VCC

PA4

PA5

PA6

PA7

PB3

PB4

PB5

PB6

PB7

D7

D6

D5

D4

D3

D2

D1

D0

WR

GND

PA3

PA2

PA1

PA0

A1

A0

PC7

PC6

PC5

PC4

PC0

PC1

PC2

PC3

PB0

PB1

PB2

RD

CS

(7) Port A (PA0 – PA7): These are 8 bit bidirectional I/O pins used to send data to peripheral or to read data from peripheral. The contents are transferred to/from part A.

(8) Port B (PB0 – PB7): These are 8 bit bidirectional I/O pins that are used as latched output

lines or buffered input lines in the same way as PA0 – PA7.

(9) Port C (PC0 – PC7): These are 8 bit bidirectional I/O pins can be divided in two sections, PC0 to PC3 & PC4 to PC7. These two sections can be individually used to load or transfer 4 bits of data from two separate port C sections i.e. upper port C & lower port C.

Q2. Draw the block diagram of 8255 programmable peripheral interface (PPI) and explain

function of each block.

Ans.: The block diagram of 8255 programmable peripheral interface (PPI) is shown in

figure. It consists of following blocks.

1. Data bus buffer 2. Real/write control logic 3. Group A & Group B Control

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BLOCK DIAGRAM OF 8255

D0 – D7

A0

CS

RD

WR

DATA

BUS

BUFFER

Group AControl

Group BControl

READ/WRITE

CONTROL LOGICA1

Reset

Group BPort CLower

Group APort CUpper

Group APort A

PA7 – PA0

PC7 – PC4

PC3 – PC0

Group BPort B

PB7 – PB0

4. Port A & Port B 5. Port C1. Data Bus Buffer:

The 8 bit bidirectional, tri state data bus buffer is used to interface 8255 data bus with system data bus. It is internally connected to internal data bus & its outer pins D0 – D7 are connected to system data bus directly. The direction of data buffer is decided by read & write control signals. When read is activated, it transmits data to the system data bus & when write is activated, it receives data from system data bus. The data bus buffer transfers or receives data & control formats for 8255.

2. Real / Write Control Logic:

The block accepts input from system control bus & address bus. The control signals are and and address signals used are A0, A1, & . From the above 5 signals and are connected to or depending on, which mapping is used. A0 & A1 are directly connected to address lines A0 & A1. is connected to address chip select decoder.

The 8255 operation/selection is enabled/disabled by signal. A0, A1selects or activates a specific port. , decides what operation is to be performed i.e. write data to 8255 or read data from 8255.

3. Group A & Group B Control:

The 8255 I/O ports are divided in 2 sections, Group A and Group B. Group A consists of port A and port C upper, group B consists of port B and port C, lower. Each group is programmed through software, the GA & GB control block, receives commands form the R/W control logic to accept bit pattern form CPU. GA control will control GA

ports and GB control will control GB ports. The bit pattern given by CPU consists of information to control the operation of GA & GB & the mode which they should be operated.

4. Port A & Port B:

These are 8 bit bidirectional data output latch/buffer and one 8 bit data input buffer. The function of port A & B is decided by control bit pattern available in G A & GB

control. The function of ports A and B are also dependent on mode in which you are operating port A and port B.

5. Port C:

This is 8 bit bidirectional data output latch/buffer and one 8 bit data input buffer. It is divided in 2 sections port C upper & port C lower, which can be programmed and used separately as a 4 bit I/O ports. These ports C can be used as simple I/O as handshake signals and as status signal inputs. For hand shake signals and status signals it is used in coordination with port A & port B. The direct bit set / reset capability is only provided by port C.

8255 INITIALISATION

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Q3. What are the modes of operation of 8255 programmable peripheral interface (PPI). Explain in detail the BSR mode with suitable example.

Ans.: The 8255 programmable peripheral interface can be operated in the following modes.1. BSR mode2. I/O modesThere are three I/O modes of operation for 8255 PPI.

(1) Mode 0 – Basic Input / Output.(2) Mode 1 – Strobed Input / Output.(3) Mode 3 – Bidirectional Input / Output.

The 8255 IC provides one control register called as control word register. It is selected when A0 = 1 & A1= 1 with = 0 & = 0. i.e. a write operation. The read operation is not allowed for control register. The bit patterns loaded in control word register specify I/O function for each port and the mode of operation in which the ports are to be used. There are 2 different control word formats which specify 2 basic modes (1) BSR – Bit set reset mode & (2) I/O mode. This is decided by D7 bit of control register when, D7 = 1 it is a I/O mode and when D7 = 0 it is a BSR mode.

BSR mode:The BSR mode is bit set reset. The mode uses eight bits of port C only. The

individual bit of port C can be set or reset by writing control word in the control resister. The pin of port C i.e. Bit 7 to set or reset is chosen using Bit select bits b b b

i.e. D3 D2 & D1 of control word register. The bit to set or reset is decided by bit S/R i.e. D0. The BSR mode affects only one bit of port C at a time. The bit set using BSR mode remains set unless and until you change the bit. The bit to be set/ reset is decided by control word. So to set any bit of port C, bit pattern is loaded in control register. Even though a BSR mode is selected it will not affect I/O mode.

Q4. Explain I/O mode control register format of 8255 in detail. Obtain the control word to configure,

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Control word format of BSR mode for 8255

Port C bit Set/Reset

0 X b b S/RX X b

D7 D6 D5 D4 D3 D2 D1 D0

Don’t CareBSR mode Bit Select

D3, D2 and D1 are from 000 to 111 for

PC0 to PC7

(i) Port A and port B as input ports and port C as output port(ii) Port A as input port and port B and port C as output ports(iii) Port A as output port and port B and port C as input ports

in mode 0.

Ans.: There are three I/O modes of operation for 8255 PPI.(1) Mode 0 – Basic Input / Output(2) Mode 1 – Strobed Input / Output(3) Mode 2 – Bidirectional Input / OutputThe I/O modes are programmed using control register. If D7 bit = 1 the control word is

for I/O modes. The format of control word is as shown below.

Function of each bit in the control word register for I/O mode is as follows:(1) Bit D7: When this D7 = 1 then I/O mode is selected, if D7 = 0 then BSR mode is

selected & function of bits D0 to D6 changes.(2) Bit D6 & D5: In I/O mode the bits D6 & D5 specifies the different I/O modes for

group A i.e. Mode 0, Mode 1 & Mode 2 for port A and port C Upper.(3) Bit D4 & D3: If these bit = 1 the respective port specified is used as input port & if these

bit = 0, the port is used s output port. These bits gives the basic function of operation to ports of group A only i.e. port A & port C (4 bit upper).

(4) Bit D2: In I/O mode the bit D2 specifies the different I/O modes for group B i.e. Mode 0 & Mode 1 for port B & port C lower.

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Control word format for I/O Mode of 8255

I/O Mode

1 Mode Mode PB PCLPA PCU

D7 D6 D5 D4 D3 D2 D1 D0

00 = Mode 0 01 = Mode 1 1X = Mode 2

Group AMode Selection

1 = Input 0 = Output

Group APort B (PA7 – PA0)

1 = Input 0 = Output

Group BPort C lower(PC3 – PC0)

1 = Input 0 = Output

Group BPort C lower(PC3 – PC0)

0 = Mode 0 1 = Mode 1

Group BMode Selection

1 = Input 0 = Output

Group BPort B (PB7 – PB0)

(5) Bit D1 & D0: If these bit = 1 the respective port specified is used as input port and if bit = 0 the port is used as output port. These bits give the basic function of operation to ports of group B only i.e. port B and port C (4 bits lower).

From the above explanation you can observe that all the 3 mode i.e. Mode 0, Mode 1, Mode 2, are only for group A ports but for group B only 2 modes i.e. Mode 0 and Mode 1 are provided. The ports port A, port B, port C lower and port C upper can be programmed separately as separate bits are used to program them.

(i) The control word format required to configure, port A and port B as input ports and port C as output port will be 92 H as shown below.

1 0 0 1 0 0 1 0

(ii) The control word format required to configure, port A as input port and port B and port C as output ports will be 90 H as shown below.

1 0 0 1 0 0 0 0

(iii) The control word format required to configure, port A as output port and port B and port C as input ports will be 8B H as shown below.

1 0 0 0 1 0 1 1

When the reset out of 8086 is high, as it is connected to reset of 8255, 8255will get resettled i.e. it will clear control word register previous contents & all the ports are set to input mode. Now when reset signal is removed by 8086, the condition of 8255 is maintained as it is. The ports of 8255 can be programmed for other modes by sending appropriate bit pattern to control register.

I/O OPERATION MODES:

Mode 0 (Simple Input /Out put mode):In mode 0, all 3 ports i.e. port A, port B, & port C (PCL & PCU) provide simple input

or output operation separately. The data is simply read form a port or it is simply written to a port. In mode 0 there is no restriction between function of ports, you can program input or output function to all ports i.e. PA, PB, PCL & PCU.

The port C, 2 section port C upper & port C lower can be individually programmed as 4 bit ports.

The features of Mode 0:(i) Two 8 bit ports PA & PB & two 4 bit ports PCL & PCU.

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8255 Initialization

(ii) All the ports can be separately programmed as input or output.(iii) If the port is programmed as output, the outputs are latched.(iv) If the port is programmed as input, the inputs are latched.(v) As 4 ports are to be used, 16 different I/O configurations are possible.(vi) No facility for interrupt driven I/O.

Mode 0 Input mode:The 8255 is initialized in input mode by using control register. Now the port will work

as input port. When CPU wants to read data from an input port, the CPU will first send address of port on address lines so , A0 & A1will select the appropriate port. After selecting a port, CPU will send a control signal to read waveform for mode 0 input modes is as shown in figure.

Timing Waveforms for Mode 0 Input Mode

Mode 0 Output mode:The 8255 initialized in output mode by using control register. Now the port will work

as output port. When CPU wants to send data to an output port, the CPU will first send address of port on address lines so , A0 & A1 will select the appropriate port. After selecting a port CPU will send data & control signal to write data to port through data bus D0 – D7. As the port is in output mode the contents will get latched & these are made available to the external peripheral. The timing waveform for mode 0 output mode is as shown in figure.

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Timing Waveforms for Mode 0 Output Mode

INTRODUCTION to 8251The software approach of serial data transfer is by using parallel port or SID / SOD

pins, the work of 8085 is increased considerably so a special device 8251 can be used to do all

the job. Only the thing to be done by a processor is initialize the chip 8251 and just go on

sending data to 8251. 8251 will do the job of sending data out, accepting data bits,

generation /removing other signals attached with data, check different condition etc.

This 8251 IC is designed by Intel which is dedicated to communication. It is a

universal synchronous / Asynchronous Receiver / Transmitter (USART). The communication

between processor & 8251 is done in parallel mode only. 8251 will convert this parallel data

into serial stream & transmit on serial output line. At the same time it receives serial data on

input line convert it to parallel from and transfers to processor.

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Features of 8251 USART:1) Supports both synchronous & asynchronous modes of operation.2) In synchronous mode 5 – 8 bits characters, Internal or external character

synchronization at receiver, Automatic sync insertion at transmitter.3) In asynchronous mode 5 – 8 bits characters clock rate selectable 1,16 or 64 time baud

rate, Break character generation, 1, 1½ or 2 stop bits, false start bit detection, Automatic break detect circuitry available.

4) Synchronous baud rate – Dc to 64 K baud.5) Asynchronous baud rate – Dc to 19.2 K baud.6) Transmitter & receiver contain full duplex, double buffered system.7) Error detection – parity, over run, framing.8) Compatible with 8085 CPU.9) 28 pin DIP package & all inputs / outputs are TTL compatible.10) Single +5V supply.

PIN DESCRIPTION

Q1. Draw the pin diagram of 8251 communication interface and explain the function of each pin.

Ans.: The pin diagram of 8251

communication interface is shown in figure. The functions of various pins are as follows.

1) Data bus (D0 – D7): There are bidirectional data lines connected to system data bus. On which the microprocessor will send or receive data from 8251.

2) Chip Select ( ): This is a chip select input signal used to select 8251 it self, when = 0 the 8251 will accept other signals & accordingly operate on that. If = 1 8251

is not selected.

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1

2

3

4

5

6

7

89

10

11

12

1314

28

27

26

25

24

23

22

211120

19

18

17

16

15

8251 PIN DIAGRAM

RESET

GND

D4

RXRDY

D1D2

D3

D5

D0

D6

D7

VCCRXD

CLK

TXD

TXEMPTY

SYNDET/BRKDET

TXRDY

CS

WR

TXC

RD

C / D

RXC

DTR

RTSDSR

CTS

3) Clock input (CLK): This is an input clock signal to 8251. This CLK input is used for communication between CPU & 8251. The only condition with CLK is this frequency must be greater then 30 times the RXC or TXC i.e. receiver & transmitter frequency.

4) Reset Input (RESET): This pin is a Reset input pin generally connected to Reset out of 8085. This pin is used to force 8251 in idle mode i.e. reset condition. The 8251 will remain in this mode unless a new set of mode & command words are written i.e. reprogrammed or reinitialized condition. To reset 8251 fully it requires Reset input low for 6 clock pulse.

5) Write input ( ): This point is an input signal to 8251. This is used to load information in 8251. When this pin is low the data bus buffer accepts data from system data bus & transfers to appropriate selected part of 8251. Generally this pin is connected to write control single of microprocessor i.e. or depending a mapping to be used.

6) Read input ( ): This pin is an input signal to 8251. This is used to transfer information form 8251 to microprocessor. When this pin is low, the data bus buffer accepts data from selected part & sends it onto system data bus for microprocessor. Generally this pin is connected to read control signal of microprocessor i.e. or

.7) Control / Data (C / ): This is an input pin, used to differentiate between 2 sections

control section & Data section. When C / = 1 the control section is enabled. C / = 0 the data section is enabled. Generally this pin is connected to address line A0. When you send / receive data with address A0 = 1, you are loading or reading control / status information. When you send / receive data with address A0 = 0, you are loading or reading data information.

8) Data set ready ( ): This is an input signal. It is general purpose, 1 bit inverting input port, used to test MODEM control condition such as Data set ready. The condition of this pin can be checked using status read operation.

9) Data terminal ready ( ): This is an output signal. It is general purpose -1 bit inverting output port, used to send MODEM control condition such as Data terminal ready. The condition of this pin can be set by programming appropriate bit in command instruction word.

10) Request to send ( ): This is an output signal. Ti is general purpose, inverting output port, used to send MODEM control condition such as Request to send. The condition of this pin can be set by programming appropriate bit in command instruction word.

11) Clear to send ( ): This is an input signal. It is 1 bit inverting port, conditioned with TxE bit. If TxE bit in command byte is set to one the pin low enables the 8251 to transmit serial data. If any of the above condition is made deactivate, the data available before such condition is transmitted & 8251 will stop after that.

12) Transmit data (TxD): It is an output pin used to output composite serial stream of data, on the falling edge of TxC. The TxD pin is held in logic high i.e. marking condition after i) The set condition or ii) When TxEn or off condition or iii) Tx Empty condition.

13) Transmitter clock ( ): This is an input pin, used to give clock to transmitter. This pin decides the rate at which data is transmitted. 1) In asynchronous mode the rate is fraction of the actual frequency. This fraction is selected by programming mode

word. The different fractions available are . In synchronous mode the rate

is fixed & is equal to frequency. In both cases the data bit is transmitted on falling edge of clock.

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14) Transmitter ready (TxRDy) : This is an output signal, used to signal CPU that the transmitter is ready to accept data. Generally TxRDy is connected to interrupt system of CPU, upon receiving interrupt CPU will branch to ISR & send a data to be transmitted to transmitter or TxRDy if not connected to interrupt can be checked using status read command & decision automatically reset by i.e. when a data is loaded from CPU to transmitter.

15) Transmitter empty (TxE): This is an output signal, used to signal peripheral that the transmitter has no character to transmit. The TxE is automatically reseted upon receiving a character form CPU. In synchronous mode, the TxE line is used to indicate that the transmitter doesn’t contain a character to send to receiver so transmitter is sending sync characters. Those sync characters are used as filler in data stream. The line TxE is used by receiver to delete those sync characters as those are not data bits. In asynchronous mode TxE is not having any signification as it is a character oriented system.

16) Receive data (RxD): It is an input pin, used to input composite serial stream of data on the rising edge of . The RxD input of receiver is generally connected to output of transmitter. The signals transmitted on TD will be accepted by RxD pin.

17) Receiver clock ( ): This is an input pin, used to give clock to receiver. This pin decides the rate at which data is received.

(1) In asynchronous mode the rate is fraction of actual RxC frequency. This fraction is

selected by programming mode word. The different fraction available are

(2) In synchronous mode the rate is fixed & is equal to frequency. In both cases the data bit is received or RxD input is sampled on rising edge or RxC clock.

18) Receiver ready(RxRDY): This is an output signal used to signal CPU that adata character is ready for transfer to CPU. Generally RxRDY is connected to interrupt system or CPU, upon receiving interrupt CPU will branch to ISR & read a data from receiver or if RxRDY is not connected to interrupt, it can be checked using status read command & decision of reading data is taken on that.

19) Sync detect / Break detect (SYNDET/ BRKDET): This pin is bidirectional pin & function of this pin depends on mode selected for receiver.

a) Synchronous mode: In this mode this pin is used as sync detect. There are two possible conditions input & output, which is programmed through mode word. When SYNDET is used as output it indicate that you are using 8251’s internal sync detect circuit & the output of this pin goes high when 8251receiver has received the sync character. When SYNDET is used as input, it indicates that you are using external sync detect circuit, on positive going signal on this pin the receiver will start assembling data on the rising edge of . The SYNDET pin status is also available in status word. The SYNDET bit will automatically get reset when status read operation is performed. When external SYNDET is programmed the internal SYNDET is disabled.

b) Asynchronous: In this mode this pin is used as break detect. The output of this pin is activated to indicate break in character. If programmed stop bits are not available for two consecutive stop bit sequences (including start bit, data bits and parity bit) the output of this pin goes high. At normal operation each data byte contains start bit & stop bits. If by any means stop bits are not available. i.e. RXD remains low for stop bits, it represents problem in line connected between transmitter & receiver. This is indicated by BRKDET. The status of this pin is also available in status word. This bit in status word is reset upon chip reset or if RXD pin returns to logic high.

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8251 BLOCK DIAGRAM AND FUNCTIONAL DESCRIPTION

Q2. Draw the block diagram of 8251 communication interface and explain function of each block.

Ans.: The 8251 block diagram is a shown in fig. it contain following block.

1. Data Bus Buffer 2. Read /Write Control Logic3. Transmitter Section 4. Receiver Section 5. Modem Control

Data Bus Buffer:This is 3 state bidirectional, 8 bit buffer used to interface internal data bus of 8251 to

the system data bus. The direction of data transfer through data bus buffer is decided by & . If is active the data is transferred from internal data bus to D0 – D7 pins. If is activate the data is transferred from D0 – D7 pins to internal data bus. Though the name data bus buffer is given, this buffer transfers control word, status word, data for transmitter & data from receiver, depending on signal given by R/W control logic.

Read / Write Control logic :

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BLOCK DIAGRAM OF 8251

D0 – D7 DATA

BUS

BUFFER

CS

RD

WR

READ/WRITE

CONTROL LOGIC

CLK

Reset

C/D

MODEM Control

DSR

CTS

RTS

DTR

Internal Data Bus

SYNDET/BRKDET

ReceiveControl

RXC

TXDTransmitBuffer (P C)

RXDReceive

Buffer (S P)

Transmit Control

TXRDYTXE

TXC

This is a control block for overall device. This block accepts different control signal. Such as , , C/ , , CLK & Reset from control bus & generate control signal for devices operation. The 8251 itself will get selected when is C/ = 1. Control part C/ = 0. data part.

8251 contain:a) 2 data buffer register

1) Data buffer register for transmitter, 2) Data buffer register for receiver.b) 2 control / status registers

1) 16 bit control word register named as 2 separate registers mode work & command register.2) 8 bit statuses register.First the decision on control / data part is taken then the control signals &

decided one of the two as shown in following table.

C/ Data transfer0 0 0 1 8251 data register of receiver to data bus.

0 0 1 0 Data bus to 8251 data register of transmitter.

0 1 0 1 Status word to data bus.

0 1 1 0 Date bus to control register.

1 x x x Data bus tri-stated.

The C/ is connected to A0 address line & to decoder logic. This gives 2 separate addresses for control / data parts. & are connected to or

control signal depending on which mapping we are using. The CLK is used to synchronize the data transfer between 8251 & 8085 CPU. It also provides internal timing for operation of 8251. it is connected to CLK out of 8085. The reset is used to reset 8251 & it is connected to reset out of 8085.Transmitter Section:

This section consist of transmit buffer & transmit control block. The expanded

detailed block diagram of this section is as shown in fig.

The expanded block diagram of transmitter section shows 3 blocks

(1). Transmit buffer register. (2). Output register (3). Transmit control logic.

The transmitter buffer register accepts parallel data form the data bus buffer via internal bus, if = 0, C/ = 0, = 1 & = 0. the contents of the transmitter buffer are automatically transferred to output register if the output register doesn’t contain any data i.e. empty. The data is shifted out serially on the TXD pin along with data appropriate bits are also added depending on mode selected i.e. (1). For asynchronous mode start bit & stop bits are added to data byte. (2). for synchronous mode sync characters are transferred before the data bytes.

In addition to this, if for 8251 parity is programmed; appropriate parity bit is added after each data bytes in both modes.

If transmit buffer register doesn’t contain data then TXRDY is generated by transmit control to signal CPU, to send next data for transmission. If output register doesn’t contain

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data then TXE is generated by transmit control to signal peripheral about unavailability of data for transmission.

The transmission will begin if TX is enabled in command register, = 0 & data available in output register. Otherwise TXD line will be in marking states i.e. TXD = high under following conditions.a) Transmitter is disabled in command reg.b) = 1c) TXE signal generated i.e. output register is empty.d) Upon master reset signal.

Receiver Section:

This section consists of Receiver buffer & receiver control blocks. The expanded detailed block diagram of this section is as shown in fig.

The expanded block diagram of receiver section show 3 blocks. (1) Receiver buffer register. (2) Serial input register & (3) Receiver control logic.

The receiver section accepts serial data on RXD pin. The input register converts the serial data into parallel form. The working of conversion depends on mode selected. In asynchronous mode it will check for marking status first, and then it checks for start bit, them the bits after start bit are converted to parallel form & are transferred to receiver buffer registers. In synchronous mode after SYNDET signal input register will go on accepting data bits, convert to parallel form & load into receiver buffer register.

For asynchronous mode, 8251 contain false start bit detection circuit to avoid the detection of noise transient low as a start bit. The working of this circuit is it first detects logic 1 i.e. making state on RXD line & goes on checking RXD line after that\ when the RXD line goes low, the circuit samples the line again after a half bit time. If it is still low then it is a valid start bit.

After data bits are accepted receiver checks programmed parity bit, if it is not same then a error bit in status register is set.

When the data byte is transferred from input register to receiver buffer register the control logic generates a signal RXRDY to signal CPU about availability of data byte to be read by CPU.

To avoid reading wrong data bits, each time the line in sampled on the rising edge of clock pulse, this gives approximate centre of the data bit.

Modem Control:

For sending data over long distances the telephone lines are used. The telephone lines are analog in nature so MODEM’S are used to convert digital data to analog data. To control or communicate MODEM’s with 8251, 8251 provides a block called as MODEM control. The MODEM control block uses different lines such as for MODEM. The connection between 8251 & MODEM will be as shown in fig.

As the MODEM signals are general purpose in nature, these can be used for functions other than MODEM control.

The handshake signals working are as follows: 1. Data terminal ready: When the terminal is made ON, it will perform

different operation & when it is ready for data transmission / reception, it generates a signal to indicate its readiness for data transfer.

2. Data set ready: When the MODEM is turned ON, & it is ready to transmit / receive data. It generates a signal to indicate its readiness for data transfer.

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3. : Request to send: When the terminal is ready to transmit data & has a data character to be transmitted, the terminal asserts a signal to the MODEM.

4. : Clear to send: When the MODEM is ready to transmit data, it asserts signal to terminal. The terminal upon receiving sends serial data

character to the MODEM. The communication between terminal & MODEM is generally achieved using RS 232 cable. The generalized connection of 2 terminals is as shown in figu.

In this case the terminal is called as DTE data terminal equipment & MODEM is called as DCE data communication equipment.

To provide full duplex system the two terminals can be connected as shown in figure.Both the terminals are supporting full duplex communication so both will generate

appropriate control signals & check the signals & will perform the data transfer in both directions.

8251 CONTROL WORD

Q3. Explain the mode instruction control word format of asynchronous mode of 8251 communication interface.

Ans.: The 8251 contains 16 bit control word register divided in two sections of 8 bits each. 1) Mode Word Register2) Command Word Register The 8251 is programmed to perform operations by loading control registers. After

programming i.e. initialization the 8251 is ready for data transfer in the mode specified. Mode Word:

The mode word defines the general basic operating characteristics of the 8251 such as asynchronous / synchronous operation, number of bits per character,Parity mode used. If asynchronous, then baud rate & number of stop bits, if synchronous then information about synchronous characters & detection circuit. The definition of different bits of mode word is as follows for both asynchronous mode. Mode Word Format (Asynchronous Mode):

1. The bits D1 & D0 define the 2 modes of operation. If D1 = 0 & D0 = 0. If is a synchronous mode you are programming. If D1 & D0 both are not equal to zero then you are programming asynchronous mode. In case of asynchronous mode 3 possible conditions of D1 & D0 are specified 01, 10, & 11. These bits decide the baud rate factor 1x specifies, 1 bit is transmitted / received in 1 clock pulse, 16 x specifies 1 bit is transmitted / received in 16 clock pulses, & 64 x specifies 1 bit is transmitted / received in 64 clock pulses.

So the clock pulses & baud rate factor decides the baud rate for transmission / reception. It is compulsory that the baud rate of transmitter & receiver must be same. The baud rate factor you have selected may be different but baud rate of data transfer remains same for transmitter & receiver.

2. The bits D3 & D2 defines the length of characters you are using. If allows the use of 8 bits, 7 bit, 6 bit, & 5 bits characters. As we are using 8251 with 8 bit microprocessor, if we are using 5 bits character for transmitter then those 5 bits must be least significant data bits i.e. D1 to D0 & other bits D5, D6 & D7 will be don’t care

16

bits. If we are using 5 bits character for receiver, the unused bit will be low. Remember that the parity bit is not considered as data bit.

3. The data bit D5 & D4 defines:(i) For transmitter whether you are using parity or not. If using which parity, even

or odd. The D4 bit is parity enable if D4 = 0 the parity bit is not added after data bits. If D4 = 1 a parity bit added after data bits. If D5 = 1 then even parity bit is added & D5 = 0 then odd parity bit is added.

(ii) For receiver the functions remain same but the specified condition for parity are checked & if they are not matching then a parity error bit is set in status reg.

4. The bit D7 & D6 defines the number of stop bits you are using D7 = 0 & D6 = 0 is not allowed. D7 = 0 & D6 = 1 then 1 stop bit is added after parity bit is programmed or if

parity bit is not programmed then after data bits. D7 = 1 & D6 = 0 then stop bits

are added. The ½ bit specifies it remain high for ½ bit time. So in all the output

remains high as a stop bit for bit time. D7 = 1 & D6 = 1 then 2 stop bits are

added. After stop bits i.e. logic high for programmed bit time the transmitter will remain high to indicate marking state. For receiver the programmed stop bits are checked after data & parity if programmed. If they are not matching an error bit is set in status register.

Q4. Explain the mode instruction control word format of synchronous mode of 8251 communication interface.

Ans.: The 8251 contains 16 bit control word register divided in two sections of 8 bits each. 1) Mode Word Register2) Command Word Register The 8251 is programmed to perform operations by loading control registers. After

programming i.e. initialization the 8251 is ready for data transfer in the mode specified. Mode Word:

The mode word defines the general basic operating characteristics of the 8251 such as asynchronous / synchronous operation, number of bits per character, Parity mode used. If asynchronous, then baud rate & number of stop bits, if synchronous then information about synchronous characters & detection circuit. The definition of different bits of mode word is as follows for synchronous mode.Mode Word Format (Synchronous Mode):

Bit D0 = 0 & D1 = 0. Specific synchronous mode, the function of D2 to D6 are same as asynchronous mode.

The bit D7 defines whether you are suing single sync character or using double sync character. If bit D7 = 1 it is single sync character. If D7 = 0 it is double sync character. These sync characters are used as header to each data block. Also these sync character are transmitted if data is not available & is indicated by a signal TxE.

At the receiver end those programmed sync characters are checked when match occurs receiver starts to assemble data bytes.

The bit D6 defines whether you are using SYNDET pin as input or output. When SYNDET is used as input, it specifies that you are using external sync detect circuit & it will generate SYNDET signal, when match of sync character occurs. Upon receiving the signal receiver will start assembling data. When SYNDET is used as output, it specifies that you are

17

using internal sync detect circuit & 8251 will generate SYNDET signal, when match of sync character occurs. When SYNDET signal is generated 8251 receiver section will start assembling data.

14.2 F EATURES OF P ROGRAMMABLE I NTERVAL T IMER: 1. Three independent 16 bit down counters.2. Programmable counter modes.3. Counting facility in both binary and BCD number system.4. Compatible with 8085/8086.5. Single +5v supply.6. 24 pin dual in – line package.7. For 8253 – Dc to 2 MHz operating frequency range.

For 8254 – DC to 8 MHz operating frequency range.

Q1. Draw the pin diagram of 8253 programmable interval timer (PIT) and explain pin functions.

Ans.: The pin diagram of 8253 programmable interval timer (PIT) is shown in the following figure. The functions of various pins are as described below.

Symbol Name & Function 1. D0 – D7: Data bus: These are 8 bit I/O data bus lines, connected to system data

bus for data transfer between 8085 and 8253. On those data lines 8085 will send count value for counter, initialize 8253 in different modes, read counters etc.

2. : Chip select: This is an active low input used to select the 8253 IC. If

= 0 then 8253 will be active and take part in data transfer otherwise 8253 will be in deactivate state.

3. : Read: This is an active low input signal, used in coordination with other signal to send data from appropriate counter to data to data line D0 – D7.

4. : W r i t e : T h i s i s a n a c t i v e l o w i n p u t s i g n a l , u s e d i n c o o r d i n a t i o n w i t h o t h e r s i g n a l s t o w r i t e d a t a t o l o a d c o u n t e r s o r t o i n i t i a l i z e c o u n t e r s . T h e d a t a o r b i t p a t t e r n a v a i l a b l e o n Dselect part of 8253.

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Pin Description:

8253 PIN DIAGRAM

GND

D4

OUT0

D1

D7

D6

D5

D0

D3

D2

GATE0

CLK0

1

2

3

4

5

6

7

89

10

11

12

2423

22

211120

19

18

1716

15

1314

VCC

A2

CS

WR

RD

A1

CLK2

CLK1

OUT2

OUT1

GATE2

GATE1

5. A0 – A1: Address lines: These are input active high, address lines used to

distinguished different parts of 8253 such as counter 0, counter 1, and counter 2, mode word register. These lines are internally used by 8253 to generate addresses, as follows:

6. CLK0: Clock input: These lines are clock input to 3 independent counters CLKcounter 0, counter 1 and counter 2. The pulses applied at these pins

CLK2: will be counted by respective counters.

7. Gate0: Gate Control: These are active high, input signals used to allow externalGate1: hardware to control the respective counter. It is having different Gate2: function in different operation modes. The basic function is to start and

stop counter. If these lines are high, counter is counting pulses and if it is low, counter will stop counting.

8. OUT0: Output: These lines are active high output lines, used to give output of OUT1: counter. The output will be dependent on mode selected. Such as logic OUT2: 0, logic 1 or a frequency output. The details of this pin will be

discussed with 8253 modes.

Q1. Draw the block diagram of 8253 programmable interval timer (PIT) and explain the function of each block.

Ans.: The block diagram of 8253 programmable interval timer (PIT) is shown in the following figure. The functions of various blocks are as described below.

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A1 A0 Selected Port0 0 Counter 00 1 Counter 11 0 Counter 21 1 Counter Register

1. Data bus buffer: The tri-state bidirectional 8 bit data bus buffer used to interface 8253 data bus with system data bus. It is internally connected to internal data bus and its outer pins D0 – D7 are connected to system data bus directly. The direction of data buffer is decided by read and writes control signals. When read is activated, it transmits data to the system. When write is activated, it receives data from system data bus.

2. Read /Write Logic:

This block accepts inputs form system control bus and address bus. The control signals are & and address signals used are A0 – A1 and . Form the above 5 signals & are connected to depending on, which mapping is used. A0 & A1 are directly connected to address lines A0 & A1. is connected to address decoder.

The 8253 operation / selection is enable / disabled by signal. A0 – A1 selects or activates a specific part you are interested and & decides what operation you are going to perform, whether you are writing data to 8253 or reading data from 8253.

3. Control Word Register:

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FUNCTIONAL BLOCK DIAGRAM OF 8253

D0 – D7 DATA

BUS

BUFFER

Internal Data Bus

CS

RD

WR READ/WRITE LOGIC

A1

A0

Control Word

Register

CLK2

OUT2

Gate2COUNTER2

CLK1

OUT1

Gate1COUNTER1

CLK0

OUT0

Gate0COUNTER0

This register of 8253 gets selected when A0 = 1 and A1 = 1. It is used to write command word, which specific the counter to be used, its mode of operation and the data transfer to be used i.e. read or write the data bytes (LSB, MSB or both).

The data can only be written into control word register, on read operation is allowed.

4. Counters:

The three independent 16 bit down counters can be programmed separately through control word register to decide mode of counter. Each counter is having 2inputs CLK and Gate. Form the CLK is used as input to counter and gate to control counter. The counters gives output on OUT pin, which is dependent on mode you have programmed. The value you have loaded in counter will be decremented by counter at each clock input pulse.

C ONTROL W ORD R EGISTER F ORMAT

Q3. What is control word register? Explain control word register format of 8253 timer in detail. Enlist the operating modes of 8253 timer.

Ans.:

Note: In above format all the other bit functions are some for 8253 and 8254 except SCO= 1 and SC1 = 1. In 8253 this combination is not allowed but in 8254 this combination is used to give read back command.

i) The control word register bits SC1 and SC0 select the counter you are initializing. When SC0 = 0 and SC1 = 0, the control word for counter 0 is set so counter 0 will work according to initialization. Similarly other counter control words can be selected and used to initialize the counters. Remember A0 and A1 also select counters but they are used to read / load counters by microprocessor.

ii) The bits RL0 and RL1 are used to decide the number of data bytes you are reading / loading to selected counter i.e. LSB byte MSB byte or both LSB and MSB bytes.

iii) The bits M2, M1 & M0 decides the mode you are using for selected counter, MODE0-MODE5.

iv) The bit BCD decides the mode of counting whether you are using BCD counter or binary counter.

M ODE’S OF O PERATION

Q4. What are different operating modes of 8253 timer? Explain mode 0 in detail with signal diagram.

Ans.:The programmable timer IC provide following modes of operation selected by control

word register bits M2 , M1 & M0.

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1) Mode 0: Interrupt on terminal count:

Control word format required for mode 0 will be as follows. We are assuming counter 0, read / load LSB data byte only & BCD counter.

= 11 HThe initialization & loading of counter will be in two steps, the counter will start

operation on mode selected & count value loaded. To implement this we have to use two control signals.

The three cases are as shown in fig. 14.4 and their details are as follows.Case i ). The control word register & counter0 are loaded by using so it will go low

twice. First to load control word register for counter0 data will be 11 H. Second to load count value to counter0 the data loaded is 05 H. When the control word register is loaded with mode 0 the out 0 output goes low at next negative going edge, when the data 05 H is loaded it is considered as count value & transferred to counter on next negative going edge of CLK0 after & counter will go on counting the CLK0 pulses. The counter decrements count by 1 each time, when counter reaches zero the out0 pin will go high & remain high. Assuming the status of Gate input is high.

Case ii ). The control word register loaded with 11 H data & LSB data loaded is 03. The counter will start counting only if the gate 0 input is high. If the gate input becomes low the counter stops counting, again when gate become high it will continue counting up to zero. When reaches zero the out pin will be made high.

Case iii ). All other points are same CW = 11 H, LSB data loaded is 04 H, gate input is high. The counter start, counting the CLK input pluses but before counter reaches to zero, if a new count value is loaded then counter will take new count value & restart decrementing count value up to zero. When it reaches zero it will make out pin high. If we are using 16 bit counter (i.e. LSB & MSB) and the counting is going on & if we loaded counter before it reaches zero. Loading LSB the current count stops & loading MSB restart with new value.

The output in all 3 cases is made high when count reaches zero. It remains high until a new count value is loaded or mode of operation is changed. This output can be used as interrupt so name given interrupt on terminal count.

Q5. What are different operating modes of 8253 timer? Explain mode 1 operation in detail with signal diagram.

Ans.:The control word format required for mode 1 will be as follows assuming

counter 0, read / load LSB data byte only & BCD counter.

= 13 H.The three cases are as shown.

Case i): The counter 0 is initialized in mode 1 by using data 13 H & loaded by count value 03 H, so we require two signals to do so. The output goes high when

22

0 0 0 1 0 0 0 1

2) Mode 1: Programmable one shot:

0 0 0 1 0 0 1 1

the control word is initialized in model. The mode is programmable one shot i.e. mono-stable having high as a stable state & low as unstable stats, the counter remain low for count value pulses. By just initializing & loading counter does not start the counter, the condition of gate is required to start counter. The positive going edge on gate input will start counter so it is called as trigger input. When the positive going edge occur at gate input after that, the count value is transferred to counter on negative going edge of clock input to counter. The counter output change to low & counter goes on decrementing the count value by 1 on every negative going edge of CLK input. When the counter becomes zero the output is changed back to high i.e. a stable states. If you want to reset counter you can give another positive going edge on gate input & counter will restart counting by making output low.

Case ii ): The control register is loaded with 13 H & count value with 03 H & a trigger pulse is applied at Gate0, input. The counter will start as case (i), but if another trigger pulse is applied before the counter reaches zero, the positive edge on trigger will restart counter from initial value loaded & will go on decrementing up to zero. On reaching zero the output will be made high.

Case iii): The control register is loaded with 13H & count value 04H & a trigger pulse is applied at Gate0 input. The counter will start same as case (i). But if another count value is loaded before it reaches zero. The new count value will not be considered for counter & counter will continue counting. But if a trigger pulse is applied after loading new count value before previous counter reaches zero or after counter reaches zero the new count value is transferred to counter & counter will restart counting from new count value.

Function of Gate:Rising edge on gate input is used as trigger pulse & counter initiates

counting resets output & transfers present count value to counter.

Q6. What are different operating modes of 8253 timer? Explain mode 2 operation in detail with signal diagram.

Ans.: Control word format required for Mode 2 will be as follows, assuming counter 0, Read / load LSB only, & BCD counter.

= 15 HThe three cases are as shown in details are as follows:

Case i): The counter 0 is initialized by using data 15H & loaded by count 04H. So we require two signals. When control word is initialized in Mode 2 the output is made high on next negative going edge of CLK input. When LSB is loaded with data, that data is transferred to counter on next negative going edge of clock & counter starts counting each time it decrement counter by 1. When the counter reaches 1 it makes output low & the output is again made high when counter becomes zero i.e. the output remains low for only one clock pulse. When the counter becomes zero the count value is reloaded in counter & counter continues counting. The gate is maintained high for case (i).

23

3) Mode 2: Rate Generator / Pulse Generator :

0 0 0 1 X 1 0 1

Case ii): The control word register is loaded with 15H & data loaded is 4 & gate is high the counter will start counting same as case (i) But at any instant gate goes low the counter stops counting & if gate is again & counter starts counting & if gate is again & counter starts counting form count value.

Case iii): The control word register is loaded with 15H, LSB data with 04H & gate input is high. The counter starts counting. Before it reaches to zero, if a new count value is loaded this new value is not considered. The counter continues up to one, changes output to low, on next negative edge of CLK input the counter becomes zero it changes output to high & new count value is transferred to counter & counter continues with new count value.

24

8255 PIN DIAGRAM

8255PPI

1

2

3

4

5

6

7

8

9

10

11

12

13

15

14

16

17

18

20

19

40

23

21

22

24

26

25

27

29

28

30

32

31

35

33

34

39

36

38

37

RESET

VCC

PA4

PA5

PA6

PA7

PB3

PB4

PB5

PB6

PB7

D7

D6

D5

D4

D3

D2

D1

D0

WR

GND

PA3

PA2

PA1

PA0

A1

A0

PC7

PC6

PC5

PC4

PC0

PC1

PC2

PC3

PB0

PB1

PB2

RD

CS

BLOCK DIAGRAM OF 8255

D0 – D7

A0

CS

RD

WR

DATA

BUS

BUFFER

Group AControl

Group BControl

READ/WRITE

CONTROL LOGICA1

Reset

Group BPort CLower

Group APort CUpper

Group APort A

PA7 – PA0

PC7 – PC4

PC3 – PC0

Group BPort B

PB7 – PB0

25

Control word format for I/O Mode of 8255

I/O Mode

1 Mode Mode PB PCLPA PCU

D7 D6 D5 D4 D3 D2 D1 D0

00 = Mode 0 01 = Mode 1 1X = Mode 2

Group AMode Selection

1 = Input 0 = Output

Group APort B (PA7 – PA0)

1 = Input 0 = Output

Group BPort C lower(PC3 – PC0)

1 = Input 0 = Output

Group BPort C lower(PC3 – PC0)

0 = Mode 0 1 = Mode 1

Group BMode Selection

1 = Input 0 = Output

Group BPort B (PB7 – PB0)

26

1

2

3

4

5

6

7

89

10

11

12

1314

28

27

26

25

24

23

22

211120

19

18

17

16

15

8251 PIN DIAGRAM

RESET

GND

D4

RXRDY

D1D2

D3

D5

D0

D6

D7

VCCRXD

CLK

TXD

TXEMPTY

SYNDET/BRKDET

TXRDY

CS

WR

TXC

RD

C / D

RXC

DTR

RTSDSR

CTS

BLOCK DIAGRAM OF 8251

D0 – D7 DATA

BUS

BUFFER

CS

RD

WR

READ/WRITE

CONTROL LOGIC

CLK

Reset

C/D

MODEM Control

DSR

CTS

RTS

DTR

Internal Data Bus

SYNDET/BRKDET

ReceiveControl

RXC

TXDTransmitBuffer (P C)

RXDReceive

Buffer (S P)

Transmit Control

TXRDYTXE

TXC

27

C/ Data transfer0 0 0 1 8251 data register of receiver to data bus0 0 1 0 Data bus to 8251 data register of transmitter

0 1 0 1 Status word to data bus.0 1 1 0 Date bus to control register.

1 X X X Data bus tri-stated.

A1 A0 Selected Port0 0 Counter 00 1 Counter 11 0 Counter 21 1 Counter Register

RXRDY

8253 PIN DIAGRAM

GND

D4

OUT0

D1

D7

D6

D5

D0

D3

D2

GATE0

CLK0

1

2

3

4

5

6

7

89

10

11

12

2423

22

211120

19

18

1716

15

1314

VCC

A2

CS

WR

RD

A1

CLK2

CLK1

OUT2

OUT1

GATE2

GATE1

28

FUNCTIONAL BLOCK DIAGRAM OF 8253

D0 – D7 DATA

BUS

BUFFER

Internal Data Bus

CS

RD

WR READ/WRITE LOGIC

A1

A0

Control Word

Register

CLK2

OUT2

Gate2COUNTER2

CLK1

OUT1

Gate1COUNTER1

CLK0

OUT0

Gate0COUNTER0

29

8255 PIN DIAGRAM

8255PPI

1

2

3

4

5

6

7

8

9

10

11

12

13

15

14

16

17

18

20

19

40

23

21

22

24

26

25

27

29

28

30

32

31

35

33

34

39

36

38

37

RESET

VCC

PA4

PA5

PA6

PA7

PB3

PB4

PB5

PB6

PB7

D7

D6

D5

D4

D3

D2

D1

D0

WR

GND

PA3

PA2

PA1

PA0

A1

A0

PC7

PC6

PC5

PC4

PC0

PC1

PC2

PC3

PB0

PB1

PB2

RD

CS

30