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8085 procesor ,goankor

Jan 25, 2016




  • \8080A-Bcsedmputer


    80E5 microprocassor is s much impaovcdion of its pcdeccsso., thc 8080A. Th. E0t5

    o0 iB chip dlost of thc logic circuiEy forcompotidg lasks lnd for communicatiog

    pc.iphqrls, Ho!vcy6, eighl of its bus liqc!; thlt i!

    sd.r rdtq! e$Ldeq Ihis chrptir discussrsl0t5 architccole h detarl and illustratcs lcch-

    for dcmukiplcxing the bus and gcneradng lhcconnol signals.

    I..t ., thc chaptcr dcs.nbcs a typical 80t5.miquomputcr &sigocd with gcn.rel puposc

    and VO dcviccsi i! slso illusEstcs rhc busi8 signrls in cxcculing an in$ruclion. ln addi.

    lh. chaptcr includes illustrations of special-d.vicca such as th. 8155 end 8?55/8355.

    dair mc.nory maF io thc Intcl SDK-85 system.

    tr Draw a logic rchemaric lo g.neriitc flour conuolsrgnals, Ltsrn8 thr 8085 Io/M, 6 and m sig-nals: 0) M=E!,lR. (2) ),r.Mw-, (3) foR, and(4) IOW-. Explain $e fun('ions of !hcs. co.Eolslgffils.

    ! List rhc various inlcmal units thal m.k up thc8085 archrrccrurE. and explain thcrr fun$ions rndecodiog and execuriog an instructior.

    - Draw the block diagram of an 8085-bascd

    , thc chlpacr inclu&s a discussion of th.microproccssot aod rtlatcd deviccs, and

    th. 80804 with ttr. 8085.

    lEogniz. thc furctioos of various pinr of thrD85 micloproccasorErplain fu bus timiogs in fcrchinS an insrudiontorn rlrmory,Erplain how to dcmultiplcx thc AD-Mo bustsidS a latch.


    Descnbe thc E080A MPU in Erms of its compo-neni dclices. thc 8080A mlcroprocctsoa, tha8228 sysrem conlroller, and tha 8224 oscillelor.Lisr rh. f.arures of rhc 8085 microprocatsorand compare lhem with lhosc of lhe 8080A


    Analyzc a mcmory ircrfacing circuil, and specifylhc mcmory map of a 8rv.n mcmory deviccRccognizc lhc pon addrss ofa givcn I,/O devic..List additioml siSnals found in such sp.ciallydcsigncd dcliccs as lh. 8155 and ihe 8755/8355,and analyze lhe inicrfacing circurl oflhe SDK-85

    3 THE 8085 MPU1The lerm }licro Proce.sing Unil ,uPL lr .rmilar 16 lhe tern Cenlrai Plocessing Ln::r C PL' , used rn rad flrond I .ompule rs fvr rlcfin

    -thc IIIPU as r d.vicc or r SrouP of dcvicer(5s i unrll rhar can.ommunrcale *ilh-pcriphcrals. Drovid.liminS signals. dlrtct data floL'ld gcrform computing uskt as spt(rfied bv the inshilrcn\ in memory) fn( .rnrl s.jhalc thc necessary lines ior the! bus, lhe dala bus. and the conlrol tignah. anwould rcquire only a lgllllqll and a cl!g!19! equllalenr freqrienc]'dgrerminmco!1po!enl, ro bc complerelt funrtron.rl

    l ElH.r rurlss bul of rhe 8085 mrtoprot.ssor is multiplar.d (dtESi6-tr d.r. br.. tlibll; seed tl) b. d.rnrltPl.Ed.

    2. Api'rofrtu$iHt iiaa Fd t9 bq gct!.t!d io inerfice mrhory atd. UO vithtOas. (lnt.l has sode. spccialized. rnemol}] and I o dcvices thal do not rcquirq scoanol siSnals).

    -Osing thrs d.scnpdon, lhe 8085 microprocesso! can almost qualify as an MPU b

    with rhc fouoerng rwo lim(Juons

    'tlis scclion lhows how to demultrpler rhe bui and genemle the contol signals 3:dascribing the 8085 microprocessor and rllustrales the bus limings

    3.l l The 8085 MicroprocessorThc 8OE5 is !n E-brl g.n.ral purPos. microproccssor capabjc of addrtsal$ 6rKmcmor) The dc\rcc ha' lonr prns. rcqurr' a 15 V \,ngle pow.r sirpPly' and cen oFi\rrth a l-MHz srngl..phasc clock. The 8085 ls an enhanced version ol its prcdecessor'8080A. rrs innluctidn set is upw.r.rd-compatible with lhal of the 8080A. m.aning tha(81185 rnnrudion rr ,ncludes all the 8080A 1n\tructions plus some sddilioncl onsgrnns urfi.r for thc 8080A will bc e\ceutcd by rhc 8085. bu! rhe 8085 rnd thc-8Jrc n,,r n,n (umDrtrble.

    - F curc ,". tic tng,, p nout Jr lhe h085 nrcroproccsrrr .\,1 ll.! s'Bnal'b! cl3s\rIed lnto ir\ groups r l, lddrcrs bus. l:, dsla bu,. O) conEol !,d strtua ai(,1) powlr supplv and !ignalr. (5 I inlcrrupu tnd p.riphcral i0 itialcd li8nlb.(6) s.nrl l/O potts.

  • E {l Bq ! FY


    ADDNESS BUSThc 808J has cight signal lin.s, AF,{!, which at! unidirlcrioml and used as th. hig}-ordcr addrcss bus.

    MUI.NPLEXTD ADDRESgDATA BUSThr siSnd linas ADi to ADo arc bidirE doaal, thy scrvc a duel purpo3.. Th.y ar! uscdas th. low-ordcr.ddnss bus as l,cil a3 th. bus. In r&culint rr'insEuction, dudntItrc a.rliar pan of $G cialc, lincs arc l]sad i thc low-ordcr add.Br bua. Durini li.lsrlr pln of r. cycl., thcsc lfura .rt ulad a! ria dltr tos. (Thi5 b .l!o t own as


    nuhiplcxing thc bus.) Howev.r, thc low-odcr addtrss bu. can b. scpsJatid ftom thcasiSrrls by llsilg a lilch.

    zi- Ll

    tz -rl lIItIIIcEIx

    muhrplcxcd bus and generate a s.pant s.r of cighr addrEss lincs, A. lo &.l',- -

    = [D-Rcrd: Thrs rs a Rcad conrrol signal {ac0!c low,. This signai rndicatcs lhat

    CONTROL AND STATUS SIGNATSThis group ol qignals includcs rwo conEol srSnals (R-O and wR-). three sho! sipalr(lO/M. 51 aod So) ro idcntify lhe naruc of th. opcratiofl, and one spccial lignal (A!E) toindicalc $c b.ginning of the opciedon. Thesc si8nlh arc as All-Ad&ir. l-rlch Efliblc: This i3 a positiv. going iuls. gcn.rat.d evry tjmc !h!

    t085 b8ins an operarion (machinc cycle); i! indicsr.s thal dl. bits oo AD7-ADo sr:sddrcss bils. This signal is uscd pnmanly !o larch lhe lo\r'order from Ur

    selectcd I O or memory dcvrcc rs ro be raad and d4a sra ava,labl. on rhc data bu!f YR-wfllc: This is a Write conEol signal (activc low). This signal indicar.s thai

    dala fi tha data bus are ro b writtan inlo a sclacEd m.olory or rO location.! lO[: Thrs is a status signal used io differcndalc betwcn L'o and mcmory ope.stionr

    *hii'ir,s trigtt. ir indicates an I/O opcradoni whcn i is low, ir lndicai.3; mcmoopcrarron. Thrs signal rs combincd *uh FD (Rcsd) and EF rwntc) !o gcn.rrE UOImmor) control rgnals.

    ,Q;sr'r!d $t These slatus signah. similar lo lO/M. can identify vsrious opantions.' thay aJr ra&ly used in small syrrcms. (AU thc operadons ard their associ.Ed sra

    signah alt listcd in Tablc Ll for r.fcrcncc.)POWER SUPPLY A}iD CLOCK FREQUENCT'Thc pow.r supply and frequcn y signah ar as follows.

    vcc: .5 voh power supply.Vs: Oround Reference.


    IItldatEFILdqE''i. , at-

    3,- "


    afbl90tc dit

    This signal ca, b. used as lhe system




    l lLE J,l6085 Mochinc Cycle Stcrtus ond C(.nbol

    X.ctla. Cych SrofilSt lllr

    s, ConEol SIrmItOFod. F.r.h

    90 R.ld

    ID=0ID=oSf,=oTD=OI[=olFlT - oID.*f,-ztrdNfI= I

    h&tru$ Actno,rhdg.lLlltlold


    lqll00ll00lll0 0)x xlx xl

    Z . Tr*.r Oran u!.L6)

    AND EMERNATLY INITIATED OPEhATIONS80E5 has fivc intcnupr signals thsl ca. bc uscd to hLmrpt a prcgram cxecutton. Onc

    $c siSnals, INTR (lnt.nupt, is idehtical ao thc 8080A micmprocessor inc.-si8r8l (IND; lhc ofiars a{lrnhrrcemctlls to lhe t060A. Thc microproccasor oc-/ledgcs an i lnu by th. INTA (Illernrpt Acknowlcdg.) sigml. (The intenup(ID.ddition !o $c int rupts. rhr! pins-RESET. HOLD. and READY-a.crpt

    cxt.rnally inidatcd signals as iryuts. To rcspond to thc HOLD rcqucsr, il has ona signalHLDA (Hold Acknowlcdse). Thc functions of rhcsc siSnals wcrc prcviously dis-in Sadon 2.13. Tha RESET is again described b.low, and orhcn aIc lisrcd i,l

    3,2 for rcfcrcnce.

    EBEIIN-: When the signal on $is pin goes loiv, thc prognm countcr is sct to zero,thc buscs arE ri-statcd, and fi. MPU is ns.rRESET OiJT: ThN signsl indicates ihat th. MPU h r.sct. Thc signd can bc us.d!o rrlat odrr drviccs,

    YO PORIit 8Ot5 hrs lwo rignals to implei:i.nt the serisl transmissionr SID (Sarial Input Data) and

    (Scrial Ouip,ut Darr). They will b. dit ussed ir Chsptcr 16 on S.rial UO.In this chapter. we will locus on lhe fitst thrcc groups of signals. whila othcn will

    discusscd io lder chaptcrs.

    '12 Bus Timingsundetstand lhc furcdors of vafious signals of lhe 8085, we mus! cramiic thc timingsthcsc signals i, rtlation !o thc systcm clock. Tha bcst way lo illusEatc $. rilning ia

    iu clamPle,

  • 62



    . t ttE 3.2


    . iim (oqur)a nsr ?.S (hFltr)

    tsT 6.5RST

    ',5. T&$ 0rptlo. fiOU) Onpur). HLDA (o!rpu)..READY (lnpul)

    6ld ErandllY InilldladI m .R.qucsti Tlit is us.d a! a gcner.l'pwP6. is timilar

    to lh. INT siSnal of rh. E080Alnr.rdpt Acknowl.dg.: T}is is urtd lo ackno*ledge an i.tcrruPt'R.slan Inr.RFs: ec vectoEd inErrupF and rarsfer dE program

    .orrcl io sp.cific dlcmory lo.ations. Th.v have highcr Eiond's tharfie INTR inttrupl. Among 6re, the pionlv ordc, is 7'5 6'5.and 5 5.

    Tnr rt. nonmatlabl. mreruPl.nd hs lh. hrth'r Pno rvThir sitnal indicaGs thar a F.iPn.El ruch as a DMA (OiEct v.mory

    Accesg coniroll.t is rcquestin8 he use of lhe addGss.nd dlla bus's'Hold Acknovl.dgr This signal acknowl.d8cs rhe HOLD equsrThis si8n.l is usad Io dclay lh. mrcropc.ssor Read or wfl.le cvcl's until

    a slow rcspondinS pcipheml is lt.d-'- ro scnd c acc'pt &la Uhcn thissisnal 8oas IoB. he micrcproc.sor wars for an inrgnl nuhber [email protected] cycles un(il il Soes hi8h.




    Rcfer ro rhc cxamplc in lhc last chapter{2.:4): lliustratc f,i timing ofdal! flo$ wh'n thtinsrrucrion code d I OO I I I I (4FH-MOV C.A)' storcd in location 2005H' isbeing fctchad.

    To fetch thc byte (4FH). the MPU needs to identifylhc mcmory location 2005Hand'nableth. data flovfmm mc or-v. This is cellcd lhe Fctch cycle' The data flow is shown inFigure 3.2;lhc limings (Figure 3.3) are.rPlaio'd b'low.


    O Srrp l: The Fogrsrn countlt Placcs lhc l6bil rncmory ld&Gsr on lhe 'ddrc