8085 ppt

WEL COME TO

THE WORLD OF

PROCESSOR

Components THE COMPUTER.

INPUT CPU OUTPUT

MEMORY

FOR EXAMPLE

KEY BOARD CPU LCD

MEMORY

2 ADD PROGRAM 5

2

+

,+

3

,3 ,5

COMMUNICATION PROCESS

C

O

N

T

R

O

LI/O

DEVICES

ADDRESS BUSMEMORY

DATA BUS

ADD./DATA

BASIC COMPUTER SYSTEM

INPUT DEVICE

OUTPUT DEVICE

I/O PORTS CPU MEMORY

DATA BUS

CONTROLBUS

ADDRESS BUS

INSIDE THE CPU

Microprocessor is aMULTIPURPOSEPROGRAMMABLE CLOCK DRIVEN.REGISTER BASED SEMICONDUCTOR DEVICE OF LOGIC CIRCUITS. MANUFACTURED USING VLSI.

MICROPROCESSOR CAN DO READS BINARY INSTRUCTIONS FROM MEMORY.ACCEPTS DATA AS INPUT.PROCESSES DATA ACCORDING TO THOSE

INSTRUCTIONS.PROVIDES RESULTS AS OUTPUT.

GENERATION OF PROCESSOR

GENERATION - 4004 Introduced in 1970

First microprocessor 4 bit architecture !

2,250 transistors 12 mm2

Clock: 108 kHz

GENERATION - 8085

Introduced in 1974

8-bit architecture Still used in some

microcontroller applications !

GENERATION - 8086

Introduced in 1979 29,000 transistors 33 mm2

Clock: 5 MHz 16 bit architecture

GENERATION - 80386

Introduced in 1985 275,000 transistors 43 mm2

Clock: 16 MHz 32 bit architecture

GENERATION - 80486 Introduced in 1989 1,200,000

transistors 81 mm2

Clock: 25 MHz 32 bit architecture

1st pipelined implementation of IA32

GENERATION – INTEL PANTIUM

• Introduced in 1993• 3,100,000 transistors• 296 mm2

• Clock: 60 MHz• 32 bit architecture

– 1st superscalar implementation of IA32

INTEL PANTIUM 3

Introduced in 1999 9,500,000 transistors 125 mm2

Clock: 450 MHz 32 bit architecture

BASIC STRUCTURE OF µp

REGISTERSDATA BUSADDRESS BUS

ALU

CONTROL &

TIMING

Basic terminologyClock frequency.Bus.Width of data bus.Width of address bus.i/o addressing capability.Instructions.

BUS ORGANIZATION

WHAT IS MEMORY?

1000H 1001H 1002H 1003H 1004H 1005H 1006H 1007H

2000H 2001H 2002H 2003H 2004H 2005H 2006H 2007H

3000H 3001H 3002H 3003H 3004H 3005H 3006H 3007H

MEMORY READLIFT

3007H

TOM CRUISE

MEMORY READ OPERATION

µp ADD. MARµp READ SIGNALREAD MAR & PUT DATA

ON MBRµp READS MBR BY DATA

BUS RAM

MAR

MBR

µP

A

D

MEMORY WRITE OPERATION

µp ADD. MAR. µp WRITE SIGNAL.µp DATA MBR.MEMORY STORES THE DATA STORED INTO MBR INTO THE LOCATION WHOSE ADDRESS IS IN MAR.

RAM

MAR

MBR

µP

A

D

DATA FLOW

ACC FLIPFLOP

ALUINSTRUCTIO

NDECODER

B CED

H LSPPC

200120022003200420052006 . . . . . . . . . . .3005

1156A598FD19

CECONTROL

UNIT

INTERNAL DATA BUS

2011 8C

RAM ROM

A0A1A2

AN-1

RAM R/W MEM

MEMORY MAPPING

THE RANGE OF ADDRESS USED BY µp TO ACCESS TOTAL MEMORY.

HOW TO FIND ADDRESS RANGE ?FIND WIDTH OF ADDRESS BUS. = 16 BITMEANS LENGTH OF BITS STARTING FROM 0 &

ENDING WITH 15. = 0 – 15WRITE 8-4-2-1 FORMAT AS BELOW & PUT 0 FOR

LOWER RANGE & 1 FOR UPPER.8 4 2 1 8 4 2 1 8 4 2 1 8 4 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = 0000 H1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 = FFFF H

INTERFACING OF MEMORY CHIPS

STEP – 1 : WHICH CHIP IS GIVEN ?

IF RAM IS GIVEN : RD & WR BOTH TERMINAL ARE PRESENT ON CHIP.

IF ROM IS GIVEN : ONLY RD TERMINAL IS PRESENT ON CHIP.

INTERFACING OF MEMORY CHIPS

STEP – 2 : FINDING ADDRESS RANGE.

IT CAN BE DECIDED FROM MEMORY CAPACITY GIVEN.

CONVERT THE CAPACITY INTO POWER OF 2.

INTERFACING OF MEMORY CHIPSEX.: 4K RAM = 4 X 1K = 22 X 210

= 22+10

= 212

= A0 TO A11 ADDRESS LINES ARE DIRECT CONNECTED.

REMAINING A12 TO A15 ARE USED FORCHIP SELECTION

INTERFACING OF MEMORY CHIPS

4K 4 K

CALCULATING ADDRESS RANGEA15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0-

0000H0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1-

1FFFHCHIP DIRECT

SELECT. CONNECTED

CHANGE IN ADDRESS RANGE WITH CHANGE IN HARDWARE

A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A00 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0-

6000H0 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1-7FFFH CHIP DIRECT SELECT.

CONNECTED

BUS ORGANIZATION

Vcc

GND

4039383736353433323130292827262524232221

1234567891011121314151617181920

X1X2

RESET OUT

RESET IN

AD0AD1AD2AD3AD4AD5AD6AD7

A15A14A13A12A11A10A9A8

SODSID

TRAPRST 7.5RST6.5RST5.5INTRINTA

HOLDHLDA

CLK OUT

READYIO/MS1RDWRALES0

8085 MACHINE CYCLEIO/M S1 S0 OPERATION0 0 1 MEMORY WRITE0 1 0 MEMORY READ1 0 1 I/O WRITE1 1 0 I/O READ0 1 1 OPCODE FETCH1 1 1 INTERRUPT

ACKNOWLEDGE* 0 0 HALT* X X HOLD* X X RESET* = TRI STATE , X = UNSPECIFIDE